1/10
July 2001
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 3.3V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ574 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type Flip-Flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. In order to enhance PC
board layout, the 74LVQ574 offers a pinout having
inputs and outputs on opposite side of the
package. All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVQ574M
74LVQ574MTR
TSSOP
74LVQ574TTR
TSSOP
SOP
74LVQ574
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
LOGIC DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3-State Output Enable
Input (Active LOW)
2, 3, 4, 5, 6,
7, 8, 9
D0 to D7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7
3-State Outputs
11
CLOCK
Clock Input (LOW-to-HIGH
Edge Trigger)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74LVQ574
3/10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10
ns/V
74LVQ574
4/10
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
3.0 to
3.6
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
I
O
=-12 mA
2.58
2.48
2.48
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
0.44
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= V
CC
or GND
0.1
1
1
A
I
oz
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
5.0
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
I
OLD
Dynamic Output
Current (note 1, 2)
3.6
V
OLD
= 0.8 V max
36
25
mA
I
OHD
V
OHD
= 2 V min
-25
-25
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.5
0.8
V
V
OLV
-0.8
-0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3
2
V
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
V
74LVQ574
5/10
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Flip
Flop)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
2.7
7.4
12.0
14.0
16.0
ns
3.3
(*)
6.1
9.0
10.5
12.0
t
PLZ
t
PHZ
Output Enable
Time
2.7
8.0
12.0
14.0
16.0
ns
3.3
(*)
6.5
9.0
10.5
12.0
t
PZL
t
PZH
Output Disable
Time
2.7
8.0
12.0
14.0
16.0
ns
3.3
(*)
6.5
9.0
10.5
12.0
t
W
CK Pulse Width
HIGH or LOW
2.7
4.0
2.0
4.0
4.0
ns
3.3
(*)
3.0
1.5
3.0
3.0
t
sL
t
sH
Setup Time D to
CK, HIGH or LOW
2.7
3.0
0.0
3.0
3.0
ns
3.3
(*)
2.0
0.0
2.0
2.0
t
hL
t
hH
Hold Time CK to D,
HIGH or LOW
2.7
1.0
0.0
1.0
1.0
ns
3.3
(*)
1.5
0.0
1.5
1.5
f
MAX
Maximum Clock
Frequency
2.7
100
150
80
60
MHz
3.3
(*)
120
180
100
80
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
2.7
0.5
1.0
1.0
1.0
ns
3.3
(*)
0.5
1.0
1.0
1.0
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
3.3
4
pF
C
OUT
Output
Capacitance
3.3
7
pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10MHz
15
pF
74LVQ574
6/10
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
2V
CC
t
PZH
, t
PHZ
Open
74LVQ574
7/10
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PULSE WIDTH (f=1MHz; 50% duty cycle)
74LVQ574
8/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.2
0.004
0.008
a2
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
M
0.75
0.029
S
8 (max.)
SO-20 MECHANICAL DATA
PO13L
74LVQ574
9/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.004
0.006
A2
0.8
1
1.05
0.031
0.039
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
8
0
8
L
0.45
0.60
0.75
0.018
0.024
0.030
TSSOP20 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
0087225C
74LVQ574
10/10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
http://www.st.com
PDF 
ZIP