74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
February 1999
s
HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at V
CC
= 3.3V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
I
CC
= 2
A (MAX.) at T
A
= 25
o
C
s
LOW NOISE:
V
OLP
= 0.2 V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
s
PCI BUS LEVELS GUARANTEED AT 24mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ74M
74LVQ74T
1/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCT ION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
TRUTH TABLE
I NPUTS
OUT PUT S
F UNCTI ON
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
X:Don't Care
Thislogic diagram has notbe used to esimate propagation delays
74LVQ74
2/10
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature:
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (V
CC
= 3V) (note 2)
0 to 10
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
74LVQ74
3/10
DC SPECIFICATIONS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
V
IH
High Level Input Voltage
3.0 to
3.6
2.0
2.0
V
V
IL
Low Level Input Voltage
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
V
I
(* )
=
V
IH
or
V
IL
I
O
=-50
A
2.9
2.99
2.9
V
I
O
=-12 mA
2.58
2.48
I
O
=-24 mA
2.2
V
OL
Low Level Output
Voltage
3.0
V
I
(*)
=
V
IH
or
V
IL
I
O
=50
A
0.002
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
I
O
=24 mA
0.55
I
I
Input Leakage Current
3.6
V
I
= V
CC
or GND
0.1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
2
20
A
I
OLD
Dynamic Output Current
(note 1, 2)
3.6
V
OLD
= 0.8 V max
36
mA
I
OHD
V
OHD
= 2 V min
-25
mA
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
.
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
V
OLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
3.3
C
L
= 50 pF
0.2
0.8
V
V
OLV
-0.8
-0.2
V
IHD
Dynamic High Voltage
Input (note 1, 3)
3.3
2
V
IL D
Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
). f=1MHz
74LVQ74
4/10
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
t
PLH
t
PHL
Propagation Delay Time
CK to Q
2.7
8.0
19.0
21.0
ns
3.3
(*)
6.5
13.0
14.0
t
PLH
t
PHL
Propagation Delay Time
PR or CLR to Q
2.7
7.0
16.0
19.0
ns
3.3
(*)
6.0
12.0
13.0
t
w
Pulse Width CK, HIGH
or LOW
2.7
1.5
7.0
10.0
ns
3.3
(*)
1.5
5.0
7.0
t
w(L)
Pulse Width PR or CLR,
LOW
2.7
1.5
7.0
10.0
ns
3.3
(*)
1.5
5.0
7.0
t
s
Setup Time D to CK
HIGH or LOW
2.7
-0.2
5.0
6.0
ns
3.3
(*)
-0.2
4.0
5.0
t
h
Hold Time Q to CK
HIGH or LOW
2.7
0.2
2.0
2.0
ns
3.3
(*)
0.2
2.0
2.0
t
REM
Recovery Time PR or
CLR to Q
2.7
-1.0
1.0
1.0
ns
3.3
(*)
-1.0
1.0
1.0
f
MAX
Maximum Clock
Frequency
2.7
60
200
40
MHz
3.3
(*)
100
250
100
t
OSLZ
t
OSHL
Output to Output Skew
Time (note 1, 2)
2.7
0.5
1.0
1.5
ns
3.3
(*)
0.5
1.0
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
C
IN
Input Capacitance
3.3
4
pF
C
PD
Power Dissipation
Capacitance (note 1)
3.3
f
IN
= 10 MHz
33
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/n(per circuit)
74LVQ74
5/10
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