1/12
August 2004
s
HIGH SPEED:
f
MAX
= 150 MHz (TYP.) at V
CC
= 3.3V
s
5V TOLERANT INPUTS
s
POWER-DOWN PROTECTION ON INPUTS
s
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX273 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP WITH CLEAR fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX273
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
WITH CLEAR (5V TOLERANT INPUTS)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74LVX273MTR
TSSOP
74LVX273TTR
TSSOP
SOP
Rev. 3
74LVX273
2/12
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
X : Don't Care
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
PIN N
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asynchronous Master
Reset (Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
Flip-Flop Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
CLOCK
Clock Input (LOW-to-HIGH
Edge Triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
FUNCTION
CLEAR
D
B
Q
L
X
X
L
CLEAR
H
L
L
H
H
H
H
X
Q
n
NO CHANGE
74LVX273
3/12
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
Table 6: DC Specifications
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3V)
0 to 100
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0
2.0
2.0
2.0
3.6
2.4
2.4
2.4
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0
0.8
0.8
0.8
3.6
0.8
0.8
0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
3.0
I
O
=-4 mA
2.58
2.48
2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
74LVX273
4/12
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics (Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.8
V
V
OLV
-0.8
-0.3
V
IHD
Dynamic High Voltage
Input (note 1, 3)
3.3
2.0
V
ILD
Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
2.7
15
9.0
16.9
1.0
20.5
1.0
22.0
ns
2.7
50
11.5
20.4
1.0
24.0
1.0
25.5
3.3
(*)
15
7.1
11.0
1.0
13.0
1.0
14.5
3.3
(*)
50
9.6
14.5
1.0
16.5
1.0
18.0
t
PHL
Propagation Delay
Time
CLEAR to Q
3.3
(*)
15
9.3
17.6
1.0
20.5
1.0
22.0
ns
3.3
(*)
50
11.8
21.1
1.0
24.0
1.0
25.5
5.0
(**)
15
7.3
11.5
1.0
13.5
1.0
15.5
5.0
(**)
50
9.8
15.0
1.0
17.0
1.0
18.0
t
W(L)
CLEAR pulse Width,
HIGH
2.7
50
5.0
6.0
6.0
ns
3.3
(*)
5.0
5.0
5.0
t
W
CLOCK pulse Width,
HIGH
2.7
50
5.5
6.5
6.5
ns
3.3
(*)
5.0
5.0
5.0
t
S
Setup Time Q to
CLOCK HIGH or LOW
2.7
50
5.5
6.5
6.5
ns
3.3
(*)
4.5
4.5
4.5
t
h
Hold Time Q to
CLOCK HIGH or LOW
2.7
50
1.0
1.0
1.0
ns
3.3
(*)
1.0
1.0
1.0
t
REM
Recovery Time
CLEAR to Q
2.7
50
2.5
2.5
2.5
ns
3.3
(*)
2.0
2.0
2.0
f
MAX
Maximum Clock
Frequency
2.7
15
55
110
55
50
MHz
2.7
50
45
60
40
35
3.3
(*)
15
95
150
80
75
3.3
(*)
50
60
90
55
50
t
OSLH
t
OSHL
Output to Output
Skew Time (note 1,2)
2.7
50
0.5
1.0
1.5
1.5
ns
3.3
(*)
50
0.5
1.0
1.5
1.5
74LVX273
5/12
Table 4: CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
ad. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per circuit)
Figure 5: Test Circuit
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
3.3
5
10
10
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10MHz
40
pF
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