EMIF09-02726Sx
August 1999 - Ed: 2
SSOP20
PIN-OUT CONFIGURATION
O 8
O9
O 7
O6
I7
I 8
I9
I6
O 3
O 4
O 2
O 1
I 2
I 3
I 4
I 5
I 1
O 5
GND
GND
9
C
E
L
L
S
D
D
I
O
EMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.
TM
SO-20
ASD is a trademark of STMicroelectronics
R
I/O
= 27
, tolerance +/-20%
C
IN
= 130pF
Typical response to IEC1000-4-2
(16 kV air discharge)
Cost-effectiveness compared to discrete
solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High reliability offered by monolithic integration
BENEFITS
Where EMI filtering in ESD sensitive equipment is
required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
MAIN APPLICATIONS
The EMIF09-02726sx is a highly integrated array
designed to suppress EMI / RFI noise in all
systems
subjected
to
electromagnetic
interferences.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
DESCRIPTION
IEC 1000-4-2
15kV
(air discharge)
8 kV
(contact discharge)
COMPLIESWITH THE FOLLOWING STANDARD:
EMIF09-02726Sxfiltering response curves
1/12
Symbol
Parameter
Value
Unit
V
PP
Maximum electrostatic discharge in following
measurement conditions:
MIL STD 883C - METHOD 3015-6
IEC1000-4-2 - air discharge
IEC1000-4-2 - contact discharge
25
16
9
kV
P
PP
Peak pulse power (8/20
s)
200
W
T
stg
T
j
Storage temperature range
Junction temperature
- 55 to + 150
150
C
C
T
OP
Operating temperature range
- 40 to + 85
C
ABSOLUTE MAXIMUM RATINGS (T
amb
=
25
C)
V
I
V
F
V
RM
PP
I
RM
I
F
I
Slope = 1 / Rd
V
BR
V
CL
Symbol
Parameter
V
RM
Stand-offvoltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
V
F
Forward voltage drop
C
IN
Input capacitance per line
Rd
Dynamic impedance
I
RM
Leakage current
I
PP
Peak pulse current
Symbol
Test conditions
Min.
Typ.
Max.
Unit
I
RM
V
RM
= 5.25 V, between any I/O pin and GND
20
A
V
BR
I
R
= 1 mA, between any I/O pin and GND
6.1
7.2
V
V
F
IF = 200 mA, between any I/O pin and GND
1.25
V
Rd
I
PP
= 15 A, t
p
= 2.5
s (note 2)
0.3
C
0V bias
V
RMS
= 30mV
F = 1MHz (note 3)
130
pF
Note 1: V
CL
corresponds to the voltage level seen at the output pin
Note 2: Rd is given per diode
Note 3: C is given per diode
EMIF09-02726Sx
2/12
0
25
50
75
100
125
150
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Ppp[Tj initial]/Ppp[Tj initial=25
C]
Tj initial(
C)
Fig. 1: Peak power dissipation versus initial junc-
tion temperature.
1
10
100
10
100
1000
2000
Ppp(W)
tp(
s)
Fig. 2: Peak pulse power versus exponential pulse
duration (Tj initial=25
C).
5
6
7
8
9
10
11
12
13
14
15
0.1
1.0
10.0
30.0
Ipp(A)
tp=2.5
s
Input Vcl
Output Vcl
Vcl(V)
Fig. 3: Clamping voltage versus peak pulse cur-
rent (Tj initial=25
C).
Rectangular waveform: tp = 2.5
s
1
2
5
10
100
120
140
160
180
200
220
C(pF)
F=1MHz
Vosc=30mV
VR(V)
Fig. 4: Input capacitance versus reverse applied
voltage (typical values).
25
50
75
100
125
150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IR[Tj] / IR[Tj=25
C]
Tj(
C)
Fig. 5: Relative variation of leakage current versus
junction temperature (typical values).
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.01
0.10
1.00
5.00
IFM(A)
VFM(V)
Fig. 6: Peak forward voltage drop versus peak for-
ward current (typical values).
Rectangular waveform: tp = 2.5
s
EMIF09-02726Sx
3/12
ESD protection by the EMIF09-02726Sx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors are an ideal choice for ESD protection. They are capable of clamping the
incoming transient to a low enough level such that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operatingvoltage of the device, the TVS array becomes a low impedancepath diverting the
transient current to ground.
The EMIF09-02726Sx array is the ideal board level protection of ESD sensitive semiconductor
components. It provides best efficiency when using separated inputs and outputs, in the so called 4-points
structure.
Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The EMIF09-02726Sx should be placed as near as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protected line should be minimized.
All conductive loops, including power and ground loops should be minimized.
The ESD transient return path to ground should be kept as short as possible.
Ground planes should be used whenever possible.
Fig. 7: Example of connectionfor one cell of the EMIF09-02726Sx
Logic
Transceiver
I1
O1
I2
O2
I3
O3
I4
O4
I5
O5
GND
GND
I6
O6
I7
O7
I8
O8
I9
O9
EMIF09-02726Sx
1284-A
Connector
Fig. 8: Recommended PCB layout to benefit from 4-point structure
TO DO
EMIF09-02726Sx
footprint
Logic
Transceiver,
ASIC,...
O 3
O 4
O 2
O 1
I 6
I 7
I 8
I 9
I 2
I 3
I 4
I 5
I 1
GND
GND
O 5
O 6
O 7
O 8
O 9
Logic
Transceiver,
ASIC,...
O 3
O 4
O 2
O 1
I 6
I 7
I 8
I 9
I 2
I 3
I 4
I 5
I 1
GND
GND
O 5
O 6
O 7
O 8
O 9
NOT TO DO
EMIF09-02726Sx
footprint
EMIF09-02726Sx
4/12
TECHNICAL INFORMATION
ESD PROTECTION
The EMIF09-02726Sx is particularly optimized to perform high level ESD protection. The clamping voltage
is given by the formula:
V
CL
= V
br
+ R
d
.I
PP
The protection function is splitted in 2 stages. As shown in figure A1, the ESD strike is clamped by the first
stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a
configuration makes the output voltage very low at the Vout level.
To determine the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance
value Rd. Considering that : R>>Rd, Rg>>Rd and Rload>>Rd, the voltages are given by the following
formulas:
Vin
=
R
g
.
V
br
+
R
d
.
V
g
R
g
Vout
=
R.V
br
+
R
d
.
Vin
R
The result of the calculation made for V
G
= 8kV, Rg= 330
(IEC1000-4-2 standard), V
br
=6.6V, Rd=0.3
and R=27
is:
Vin = 13.87V
Vout = 6.75 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side because the
current involved after the resistance R is low.
Fig. A1: ESD clamping behavior
ESD
Surge
Vin
Vout
Rload
S1
S2
Rg
R
Rd
Rd
Vbr
Vbr
Vg
Device to be protected
EMIF09-02726Sx
EMIF09-02726Sx
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