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ESDA14V2-4BF1
QUAD BIDIRECTIONAL TRANSILTM ARRAY
FOR ESD PROTECTION
DESCRIPTION
The ESDA14V2-4BF1 is a monolithic array
designed to protect up to 4 lines in a bidirectional
way against ESD transients.
The device is ideal for situations where board
space saving is requested.
July 2002 - Ed: 6B
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
s
Computers
s
Printers
s
Communication systems and cellular phones
s
Video equipment
This device is particularly adapted to the protection
of symmetrical signals.
APPLICATIONS
Flip Chip package
GND
A1
A3
C1
C3
FUNCTIONAL DIAGRAM
A.S.DTM
s
High ESD protection level
s
High integration
s
Suitable for high density boards
BENEFITS
- IEC61000-4-2: 15 kV (air discharge)
8 kV
(contact discharge)
- MIL STD 883E-Method 3015-7: class3
25kV (Human Body Model)
COMPLIES WITH THE FOLLOWING STANDARDS:
s
4 Bidirectional TransilTM functions
s
ESD Protection: IEC61000-4-2 level 4
s
Stand off voltage: 12 V MIN.
s
Low leakage current < 1
A
s
50W Peak pulse power ( 8/20 )
FEATURES
A
B
C
3
1
2
PIN CONFIGURATION (Ball Side)
ESDA14V2-4BF1
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Symbol
Test conditions
Value
Unit
V
PP
ESD discharge - MIL STD 883E - Method 3015-7
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
15
8
kV
P
PP
Peak pulse power (8/20
s)
50
W
T
j
Junction temperature
125
C
T
stg
Storage temperature range
-55 to +150
C
T
L
Lead solder temperature (10 seconds duration)
260
C
T
op
Operating temperature range (note 1)
-40 to +125
C
Note 1: Variation of parameters will be given in the final datasheet
ABSOLUTE RATINGS (T
amb
= 25C)
Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
C
Capacitance
Rd
Dynamic resistance
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
I
V
V
BR
CL
VRM
I PP
I RM
V
Slope = 1/Rd
Type
V
BR
@
I
R
I
RM
@ V
RM
Rd
T
C
min.
max.
max.
typ.
max.
max
note 1
note 2
0V bias
V
V
mA
A
V
10
-4
/C
pF
ESDA14V2- 4BF1
14.2
18
1
1
12
3.2
10
15
0.1
3
Note 1: Square pulse, IPP = 3A, tp = 2.5
s
Note 2:
VBR =
T(Tamb-25C) x VBR(25C)
ESDA14V2-4BF1
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0.1
1.0
10.0
0
10
20
30
40
50
60
Vcl(V)
Ipp(A)
tp = 2.5s
Fig. 1: Clamping voltage versus peak pulse current
(Tj initial = 25C) Rectangular waveform tp = 2.5s.
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
VR(V)
F=1MHz
Vosc=30mV
RMS
Tj=25C
C(pF)
Fig. 2: Capacitance versus reverse applied voltage
(typical values).
1
10
100
1000
25
50
75
100
125
Tj(C)
IR[Tj] / IR[Tj=25C]
Fig. 3: Relative variation of leakage current versus
junction temperature (typical values).
Connector
IC
to be
protected
A1
A3
C1
C3
B2
APPLICATION EXAMPLE
ESDA14V2-4BF1
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With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
As a transient voltage suppressor, ESDA14V2-4BF1 is an ideal choice for ESD protection by suppressing
ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is
prevented on the device protected by ESDA14V2-4BF1.
ESDA14V2-4BF1 serves as a parallel protection elements, connected between the signal line and ground.
As the transient rises above the operating voltage of the device, the ESDA14V2-4BF1 becomes a low
impedance path diverting the transient current to ground.
The clamping voltage is given by the following formula:
V
V
R I
CL
BR
d
pp
=
+
.
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
1. ESD protection by ESDA14V2- 4BF1
TECHNICAL INFORMATION
ESDA14V2-4BF1
Rg
Rd
V
BR
Vg
R load
ESD Surge
Device
to be
protected
V(i/o)
Ip
Fig. A1: ESD clamping behavior
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical
resistance value Rd. By taking into account the following hypothesis :
R
g
> R
d
and Rload > R
d
we have:
V i o
V
R
V
R
BR
d
g
g
( /
)
=
+
The results of the calculation done for V
g
= 8 kV, R
g
= 330
(IEC 61000-4-2 standard), V
BR
= 14.2 V (min.)
and R
d
= 3.2
(typ.) give:
V(i/o) = 91.8 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
V(i/o)
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ESDA14V2-4BF1
Fig. A2: ESD test board
TEST BOARD
V(i/o)
EB14
15
Fig. A4: Remaining voltage during ESD surge
Fig. A3: ESD test configuration
V(i/o)
B2
A1, C1, A3 or C3
15kV
ESD Air discharge
The measurements done here after show very clearly (Fig. A4) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to +V
BR
(positive way, Fig. A4a) and -V
BR
(negative way,
Fig. A4b).
V(i/o)
V(i/o)
a: Response in the positive way
b: Response in the negative way
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