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ESDALC6V1P6
March 2003 - Ed: 2A
QUAD LOW CAPACITANCE TRANSILTM
ARRAY FOR ESD PROTECTION
SOT666
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
s
Computers
s
Printers
s
Communication systems and cellular phones
s
Video equipment
This device is particularly adapted to the protection
of symmetrical signals.
MAIN APPLICATIONS
Application Specific Discretes
A.S.D.
I/O1
I/O2
GND
GND
I/O4
I/O3
FUNCTIONAL DIAGRAM
s
4 UNIDIRECTIONAL TRANSILTM FUNCTIONS.
s
BREAKDOWN VOLTAGE V
BR
= 6.1V MIN.
s
LOW DIODE CAPACITANCE (12pF @ 0V)
s
LOW LEAKAGE CURRENT < 500 nA
s
VERY SMALL PCB AREA < 2.6 mm
2
FEATURES
The ESDALC6V1P6 is a monolithic array designed
to protect up to 4 lines against ESD transients.
This device is ideal for applications where both
reduced line capacitance and board space saving
are required.
DESCRIPTION
s
High ESD protection level.
s
High integration.
s
Suitable for high density boards.
BENEFITS
s
IEC61000-4-2 level 4: 15 kV (air discharge)
8 kV (contact discharge)
s
MIL STD 883E-Method 3015-7: class 3
25kV HBM (Human Body Model)
COMPLIES WITH THE FOLLOWING STANDARDS :
ESDALC6V1P6
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Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
T
Voltage tempature coefficient
V
F
Forward voltage drop
C
Capacitance per line
R
d
Dynamic resistance
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
V
I
V
CL
V
BR
V
RM
I
F
V
F
I
RM
I
PP
Slope: 1/R
d
Symbol
Parameter
Test conditions
Value
Unit
V
PP
ESD discharge - IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
15
8
kV
P
PP
Peak pulse power (8/20 s) (see note 1)
T
j
initial = Tamb
30
W
T
j
Junction temperature
125
C
T
stg
Storage temperature range
- 55 to + 150
C
T
L
Maximum lead temperature for soldering during 10s at N/A
260
C
T
op
Operating temperature range
- 40 to + 125
C
Note 1: for a surge greater than the maximum values
,
the diode will fail in short-circuit.
ABSOLUTE RATINGS (T
amb
= 25C)
Types
V
BR
@
I
R
I
RM
@
V
RM
Rd
T
C
min.
max.
max.
typ.
max.
typ.
@ 0V
V
V
mA
A
V
10
-4
/C
pF
ESDALC6V1P6
6.1
7.2
1
0.5
3
1.5
4.5
12
Note 1 : Square pulse Ipp = 15A, tp=2.5
s.
Note 2 :
VBR =
T* (Tamb -25C) * VBR (25C)
Symbol
Parameter
Value
Unit
R
th(j-a)
Junction to ambient on printed circuit on recommended pad layout
220
C/W
THERMAL RESISTANCES
ESDALC6V1P6
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0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
25
50
75
100
125
150
P
[T initial] / P
[T initial=25C)
PP
j
PP
j
T (C)
j
Fig. 1: Relative variation of peak pulse power
versus initial junction temperature.
10
100
1000
1
10
100
P
(W)
PP
T (s)
p
T initial=25C
j
Fig. 2: Peak pulse power versus exponential pulse
duration.
0.1
1.0
10.0
100.0
0
10
20
30
40
50
60
70
I
(A)
PP
V
(V)
CL
t =2.5s
T initial=25C
p
j
Fig. 3: Clamping voltage versus peak pulse
current (typical values, rectangular waveform).
1.E-03
1.E-02
1.E-01
1.E+00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I
(A)
FM
V
(V)
FM
T =25C
j
T =125C
j
Fig. 4: Forward voltage drop versus peak forward
current (typical values).
C(pF)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
4
5
6
F=1MHz
V
=30mV
T =25C
OSC
RMS
j
V (V)
R
Fig. 5: Junction capacitance versus reverse
voltage applied (typical values).
I [T ] / I [T =25C]
R
j
R
j
1
10
100
1000
25
50
75
100
125
T (C)
j
V =3V
R
Fig. 6: Relative variation of leakage current versus
junction temperature (typical values).
ESDALC6V1P6
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TECHNICAL INFORMATION
Connector
IC
to be
protected
I/O2
I/O1
I/O4
I/O3
Fig. A1: Application example.
With the focus of lowering the operation levels, the
problem of malfunction caused by the environment
is critical. Electrostatic discharge (ESD) is a major
cause of failure in electronic systems.
As
a
transient
voltage
suppressor,
the
ESDALC6V1P6 is an ideal choice for ESD protec-
tion by suppressing ESD events. It is capable of
clamping the incoming transient to a low enough
level such that any damage is prevented on the de-
vice to be protected by ESDALC6V1P6.
ESDALC6V1P6 serves as a parallel protection
element, connected between signal line and
ground. As the transient rises above the operating
voltage
of
the
device,
the
ESDALC6V1P6
becomes a low impedance path diverting the
transient current to ground.
1. ESD protection by ESDALC6V1P6
The clamping voltage is given by the following formula:
V
CL
= V
BR
+ R
d
.I
PP
As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor.
R
d
R
G
V
G
V
BR
V
CL
= V
+R x I
BR
d
PP
V
BR
I
PP
V
CL
V(i/o)
Device
to be
protected
ESD surge
ESDALC6V1P6
V
I
I
PP
R
LOAD
1
R
d
slope =
Fig. A2: ESD clamping behavior.
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical
resistance value R
d
. By taking into account the following hypothesis:
R
G
> R
d
and R
load
> R
d
we have:
( )
V i o
V
R
V
R
BR
d
g
g
/
=
+
The results of the calculation done for V
G
= 8kV, R
G
= 330
(IEC61000-4-2 standard), V
BR
= 6.4V (typ.)
and R
d
= 1.5
(typ.) give:
( )
V i o
Volts
/
.
=
42 8
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
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15kV ESD
Air discharge
V(i/o)
ESDALC6V1P6
Fig. A3: ESD test board.
GND
I/O1, I/O2, I/O3 or I/O4
V(i/o)
15kV ESD
Air discharge
Fig. A4: ESD test configuration.
a: Response in the positive way
b: Response in the negative way
Fig. A5: Remaining voltage during ESD surge.
The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to V
BR
(positive way, figure A5a) and -V
F
(negative way,
figure A5b).
One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative
ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.
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