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ESDALC6V1P6
QUAD LOW CAPACITANCE TRANSILTM ARRAY
FOR ESD PROTECTION
REV. 3
SOT-666IP
(Internal Pad)
July 2004
MAIN APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Computers
Printers
Communication systems and cellular phones
Video equipment
This device is particularly adapted to the
protection of symmetrical signals.
FEATURES
4 Unidirectional TransilTM functions
Breakdown voltage V
BR
= 6.1 V min.
Low diode capacitance (12pF @ 0V)
Low leakage current < 500 nA
Very small PCB area < 2.6 mm
2
DESCRIPTION
The ESDALC6V1P6 is a monolithic array
designed to protect up to 4 lines against ESD
transients.
The device is ideal for situations where board
space saving is required.
BENEFITS
High ESD protection level
High integration
Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2 level 4:
15kV (air discharge)
8kV
(contact discharge)
MIL STD 883E-Method 3015-7: class3
25kV HBM (Human Body Model)
Order Codes
Part Number
Marking
ESDALC6V1P6
D
ASDTM
FUNCTIONAL DIAGRAM
I/O1
I/O2
GND
GND
I/O4
I/O3
ESDALC6V1P6
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ABSOLUTE RATING (T
amb
= 25C)
THERMAL RESISTANCES
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
Symbol
Parameter
Value
Unit
V
PP
ESD discharge
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
15
8
kV
P
PP
Peak pulse power (8/20s) (see note 1) T
j
initial = T
amb
30
W
T
j
Junction temperature
125
C
T
stg
Storage temperature range
-55 to +150
C
T
L
Maximum lead temperature for soldering during 10 s at 5mm for case
260
C
T
op
Operating temperature range
-40 to +125
C
Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit.
Symbol
Parameter
Value
Unit
R
th(j-a)
Junction to ambient on printed circuit on recommended pad layout
220
C/W
Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
T
Voltage temperature coefficient
V
F
Forward voltage drop
C
Capacitance
Rd
Dynamic resistance
Part Number
V
BR
@ I
R
I
RM
@ V
RM
R
d
T
C
min.
max.
max.
typ.
max.
typ.
@ 0V
V
V
mA
A
V
10
-4
/C
pF
ESDALC6V1P6
6.1
7.2
1
0.5
3
1.5
4.5
12
V
I
V
CL
V
BR
V
RM
I
F
V
F
I
RM
I
PP
Slope: 1/R
d
ESDALC6V1P6
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Fig. 1: Peak power dissipation versus initial
junction temperature.
Fig. 2: Peak pulse power versus exponential pulse
duration (Tj initial = 25C).
Fig. 3: Clamping voltage versus peak pulse
current (Tj initial = 25C). Rectangular waveform
tp = 2.5s.
Fig. 4: Peak forward voltage drop versus peak
forward current (typical values).
Fig. 5: Capacitance versus reverse applied
voltage (typical values).
Fig. 6: Relative variation of leakage current versus
junction temperature (typical values).
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
25
50
75
100
125
150
P
[T initial] /
[T initial=25C]
PP
j
j
P
PP
T initial (C)
j
10
100
1000
1
10
100
t (s)
p
P
(W)
PP
T initial = 25C
j
0.1
1.0
10.0
100.0
0
10
20
30
40
50
60
70
V
(V)
CL
I
(A)
PP
tp = 2.5s
1.E-03
1.E-02
1.E-01
1.E+00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I
(A)
FM
V
(V)
FM
T = 25C
j
T = 125C
j
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
4
5
6
V (V)
R
C(pF)
F=1MHz
V
=30mV
T =25C
OSC
RMS
j
1
10
100
1000
25
50
75
100
125
T (C)
j
I [T ] / I [T =25C]
R
j
R
j
V = 3V
R
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TECHNICAL INFORMATION
1. ESD protection by ESDALC6V1P6
With the focus of lowering the operation levels, the
problem of malfunction caused by the environment
is critical. Electrostatic discharge (ESD) is a major
cause of failure in electronic systems.
As a transient voltage suppressor, ESDALC6V1P6
is an ideal choice for ESD protection by
suppressing ESD events. It is capable of clamping
the incoming transient to a low enough level such
that any damage is prevented on the device
protected by ESDALC6V1P6.
ESDALC6V1P6 serves as a parallel protection
elements, connected between the signal line and
ground. As the transient rises above the operating
voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current
to ground.
The clamping voltage is given by the following formula:
V
CL
= V
BR
+ R
d
.I
PP
As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A2: ESD clamping behavior.
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical
dynamical resistance value R
d
. By taking into account the following hypothesis:
we have:
The results of the calculation done V
G
= 8kV, R
G
= 330
(IEC61000-4-2 standard), V
BR
= 6.4V (typ.) and
R
d
= 1.5
(typ.) give:
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
R
d
R
G
V
G
V
BR
V
CL
= V
+R x I
BR
d
PP
V
BR
I
PP
V
CL
V(i/o)
Device
to be
protected
ESD surge
ESDALC6V1P6
V
I
I
PP
R
LOAD
1
R
d
slope =
R
G
R
d
""and""R
lo ad
R
d
>
>
V i o
/
(
) V
B R
R
d
+
V
G
R
G
--------
=
V i o
/
(
)
42.8 Volts
=
Fig. A: Application example.
Connector
IC
to be
protected
I/O2
I/O1
I/O4
I/O3
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The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to V
BR
(positive way, figure A5a) and -V
F
(negative way,
figure A5b).
One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative
ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.
Fig. A3: ESD test board.
Fig. A4: ESD test condition.
Fig. A5: Remaining voltage during ESD surge.
15kV ESD
Air discharge
V(i/o)
ESDALC6V1P6
GND
I/O1, I/O2, I/O3 or I/O4
V(i/o)
15kV ESD
Air discharge
a: Response in the positive way
b: Response in the negative way
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