1/9
September 2002
s
DISPLAY BLANKING OF ALL ILLEGAL
INPUT COMBINATIONS
s
LATCH STORAGE OF CODE
s
INSTRUMENT DISPLAY DRIVER
s
DASHBOARD DISPLAY DRIVER
s
COMPUTER/CALCULATOR DISPLAY
DRIVER
s
TIMING DEVICE DRIVER (CLOCKS,
WATCHES, TIMERS)
s
PIN FOR PIN REPLACEMENT OF
HCF4056B (PIN 7 CONNECTED TO V
SS
)
s
DIRECT LED DRIVING CAPABILITY
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
MAXIMUM INPUT CURRENT OF 1A AT 18V
OVER FULL PACKAGE TEMPERATURE
RANGE; 100nA at 18V AND 25C
s
NOISE MARGIN (FULL PACKAGE
TEMPERATURE RANGE):
1V at V
DD
= 5V ;
2V at V
DD
= 10V;
2.5V at V
DD
= 15V
s
100% TESTED FOR QUIESCENT CURRENT
AT 20V
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4543B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4543B is a BCD-TO-7-SEGMENT LATCH/
DECODER/LCD DRIVER designed primarily for
liquid crystal display (LCD) applications. It is also
capable of driving light emitting diodes (LED),
incandescent, gas-discharge, and fluorescent
displays. This device is functionally similar to and
serves as direct replacement of HCF4056B when
pin 7 is connected to V
SS
. It differs from
HCF4056B in that it has a display blanking
capability instead of a level shifting function and
requires only one power supply. When HCF4056B
is used in the level shifting mode, two power
supplies are required. When the HCF4543B is
used for LCD applications, a square wave must be
applied to the phase input and the backplane of
HCF4543B
BCD-TO-7-SEGMENT LATCH/DECODER/LCD DRIVER
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4543BEY
SOP
HCF4543BM1
HCF4543M013TR
DIP
SOP
HCF4543B
2/9
the LCD device. For LED applications a logic 1 is
required at the PHASE input for common cathode
devices; a logic 0 is required for common-anode
devices (see truth table).
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
* : For Liquid-Crystal readouts apply a square to Ph.
For common cathode LED readouts, select Ph=0
For common anode LED readouts, select Ph=1
**: Depends upon the BCD code previously applied when LD=1
: Above Combination
PIN No
SYMBOL
NAME AND FUNCTION
9, 10, 11, 12,
13, 15, 14
a to g
Decoded Outputs
5, 3, 2, 4
A, B, C, D
Data Inputs
1
LD
Latch Disable Inputs
6
PH
Phase Inputs
7
BI
Blanking Input
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
INPUT CODE
OUTPUT STATE
DISPLAY
CHARACTER
LD
BI
PH*
D
C
B
A
a
b
c
d
e
f
g
X
H
L
X
X
X
X
L
L
L
L
L
L
L
BLANK
H
L
L
L
L
L
L
H
H
H
H
H
H
L
0
H
L
L
L
L
L
H
L
H
H
L
L
L
L
1
H
L
L
L
L
H
L
H
H
L
H
H
L
H
2
H
L
L
L
L
H
H
H
H
H
H
L
L
H
3
H
L
L
L
H
L
L
L
H
H
L
L
H
H
4
H
L
L
L
H
L
H
H
L
H
H
L
H
H
5
H
L
L
L
H
H
L
H
L
H
H
H
H
H
6
H
L
L
L
H
H
H
H
H
H
L
L
L
L
7
H
L
L
H
L
L
L
H
H
H
H
H
H
H
8
H
L
L
H
L
L
H
H
H
H
H
L
H
H
9
H
L
L
H
L
H
L
L
L
L
L
L
L
L
BLANK
H
L
L
H
L
H
H
L
L
L
L
L
L
L
BLANK
H
L
L
H
H
L
L
L
L
L
L
L
L
L
BLANK
H
L
L
H
H
L
H
L
L
L
L
L
L
L
BLANK
H
L
L
H
H
H
L
L
L
L
L
L
L
L
BLANK
H
L
L
H
H
H
H
L
L
L
L
L
L
L
BLANK
L
L
L
X
X
X
X
**
**
INVERSE OF OUTPUT COMBINATIONS ABOVE
DISPLAY AS
ABOVE
HCF4543B
3/9
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4543B
5/9
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
BCD TO 7 SEGMENT LATCH/DECODER/DRIVER FUNCTIONAL DIAGRAM
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
t
PHL
Propagation Delay Time
5
600
1200
ns
10
200
400
15
150
300
t
PLH
Propagation Delay Time
5
500
1000
ns
10
200
400
15
150
300
t
THL
Transition Time
5
180
360
ns
10
90
180
15
65
130
t
TLH
Transition Time
5
180
360
ns
10
90
180
15
65
130
t
WH
Latch Disable Pulse Width
5
250
125
ns
10
100
50
15
80
40
t
SU
Address Setup Time
5
60
15
ns
10
20
-5
15
10
-5
t
H
Address Hold Time
5
25
-5
ns
10
20
10
15
20
0
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