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Электронный компонент: L4901A

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L4901A
DUAL 5V REGULATOR WITH RESET
June 2000
PIN CONNECTION
HEPTAWATT (Vertical)
(Plastic Package)
ORDERING NUMBER : L4901A
.
OUTPUT CURRENTS : I
01
= 400mA
I
0 2
= 400mA
.
FIXED PRECISION OUTPUT VOLTAGE
5V
2%
.
RESET FUNCTION CONTROLLED BY INPUT
VOLTAGE AND OUTPUT 1 VOLTAGE
.
RESET
FUNCTION
EXTERNALLY
PRO-
GRAMMABLE TIMING
.
RESET OUTPUT LEVEL RELATED TO OUT-
PUT 2
.
OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
.
LOW LEAKAGE CURRENT, LESS THAN 1
A
AT OUTPUT 1
.
LOW QUIESCENT CURRENT (Input 1)
.
INPUT OVERVOLTAGE PROTECTION UP TO
60V
.
RESET OUTPUT HIGH
.
OUTPUT TRANSISTORS SO A PROTECTION
.
SHORT CIRCUIT AND THERMAL OVER-
LOAD PROTECTION
DESCRIPTION
The L4901A is a monolithic low drop dual 5V
regulator designed mainly for supplying microproc-
essor systems.
Reset and data save functions during switch on/off
can be realized.
1/10
BLOCK DIAGRAM
SCHEMATIC DIAGRAM
PIN DESCRIPTION
N
Name
Fun ction
1
Input 1
Low Quiescent Current 400mA Regulator Input.
2
Input 2
400mA regulator input.
3
Timing
Capacitor
If Reg. 2 is switched-ON the delay capacitor is charged with a 10
A constant current. When Reg.
2 is switched-OFF the delay capacitor is decharged.
4
GND
Common Ground.
5
Reset
Output
When pin 3 reaches 5V the reset output is switched high.
Therefore t
RD
= C
t
(
5V
10
A
); t
RD
(ms) = C
t
(nF)
6
Output 2
5V 400mA Regulator Output. Enabled if V
o
1 > V
RT
and V
IN 2
> V
IT
. If Reg. 2 is switched-OFF
the C
02
capacitor is discharged.
7
Output 1
5V 400mA regulator output with Low leakage (in switch-OFF condition).
L4901A
2/10
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
IN
DC Input Voltage
Transient Input Overvoltage (t = 40ms)
24
60
V
V
I
o
Output Current
Internally Limited
T
j
Storage and Junction Temperature
40 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th (j-c)
Thermal Resistance Junction-case
Max.
4
C/W
ELECTRICAL CHARACTERISTICS (V
IN
= 14, 4V, T
amb
= 25
C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
i
DC Operating Input Voltage
20
V
V
01
Output Voltage 1
R Load 1k
4.95
5.05
5.15
V
V
02 H
Output Voltage 2 HIGH
R Load 1k
V
01
0.1
5
V
01
V
V
02 L
Output Voltage 2 LOW
I
02
= 5mA
0.1
V
I
01
Output Current 1
V
01
= 100mV
400
mA
I
L01
Leakage Output 1 Current
V
IN
= 0, V
01
3V
1
A
I
02
Output Current 2
V
02
= 100mV
400
mA
V
I01
Output 1 Dropout Voltage (*)
I
01
= 10mA
I
01
= 100mA
I
01
= 300mA
0.7
0.8
1.1
0.8
1
1.4
V
V
V
V
IT
Input Threshold Voltage
V
01
+ 1.2
6.4
V
01
+ 1.7
V
V
ITH
Input Threshold Voltage Hyst.
250
mV
V
01
Line Regulation 1
7V < V
IN
< 18V, I
01
= 5mA
5
50
mV
V
02
Line Regulation 2
7V < V
IN
< 18V, I
02
= 5mA
5
50
mV
V
01
Load Regulation 1
5mA < I
01
< 400mA
50
100
mV
V
02
Load Regulation 2
5mA < I
01
< 400mA
50
100
mV
I
Q
Quiescent Current
I
02
= I
01
5mA
0 < V
IN
< 13V
7V < V
IN
< 13V
4.5
1.6
6.5
3.5
mA
I
Q1
Quiescent Current 1
I
01
5mA, I
02
= 0, V
IN2
= 0
6.3V < V
IN
< 13V
0.6
0.9
mA
V
RT
Reset Threshold Voltage
V
02
0.15
4.9
V
02
0.05
V
V
RTH
Reset Threshold Hysteresis
30
50
80
mV
V
RH
Reset Output Voltage HIGH
I
R
= 500
A
V
02
1
4.12
V
02
V
V
RL
Reset Output Voltage LOW
I
R
= <0>5mA
0.25
0.4
V
t
RD
Reset Pulse Delay
C
t
= 10nF
3
5
11
ms
t
d
Timing Capacitor Discharge Time
C
t
= 10nF
20
s
V
01
T
Thermal Drift
20
C
T
amb
125
C
0.3
0.8
mV/
C
V
02
T
Thermal Drift
20
C
T
amb
125
C
0.3
0.8
mV/
C
SVR1
Supply Voltage Rejection
f = 100Hz, V
R
= 0.5V
Io = 100mA
50
84
dB
SVR2
Supply Voltage Rejection
50
80
dB
* The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under
constant output current condition.
L4901A
3/10
TEST CIRCUIT
APPLICATION INFORMATION
In power supplies for
P systems it is necessary to
provide power continuously to avoid loss of infor-
mation in memories and in time of day clocks, or to
save datawhen the primary supply is removed.The
L4901A makes it very easy to supply such equip-
ments ; it provides two voltage regulators (both 5 V
high precision) with separate inputs plus a reset
output for the data save function.
CIRCUIT OPERATION (see Figure 1)
After switch on Reg. 1 saturates until V
01
rises to
the nominal value.
When the input 2 reaches V
IT
and the output 1 is
higher than V
RT
the output 2 (V
02
) switches on and
the reset output (V
R
) also goes high after a pro-
grammable time T
RD
(timing capacitor).
V
02
and V
R
are switched togetherat low level when
one of the following conditions occurs :
- an input overvoltage
- an overload on the output 1 (V
01
< V
RT
) ;
- a switch off (V
IN
< V
IT
- V
ITH
) ;
and they start again as before when the condition
is removed.
An overload on output 2 does not switch Reg. 2,
and does not influence Reg. 1.
The V
01
output features :
- 5 V internal reference without voltage divider
between the output and the error comparator ;
- very low drop series regulator element utilizing
current mirrors ;
permit high output impedance and then very low
leakage current error even in power down condi-
Figure 1
L4901A
4/10
tion.
This output may thereforebe usedto supply circuits
continuously, such as volatile RAMs, allowing the
use of a back-up battery. The V
01
regulator also
features low consumption (0.6 mA typ.) to minimize
battery drain in applicationswhere the V
1
regulator
is permanently connected to a battery supply.
The V
02
output can supply other non essential 5 V
circuits which may be powered down when the
system is inactive, or that must be powered down
to prevent uncorrect operation for supply voltages
below the minimum value.
The reset output can be usedas a "POWER DOWN
INTERRUPT", permitting RAM access only in cor-
rect power conditions,or as a "BACK-UP ENABLE"
to transfer data into in a NV SHADOW MEMORY
when the supply is interrupted.
APPLICATIONS SUGGESTIONS
Figure 2 shows an application circuit for a
P
system typically used in trip computers or in car
radios with programmable tuning.
Reg. 1 is permanently connected to a battery and
supplies a CMOS time-of-day clock and a CMOS
microcomputer chip with volatile memory.
Reg. 2 may be switched OFF when the system is
Figure 2
Figure 3 : P.C. Board Component Layout of Figure 2.
L4901A
5/10
inactive.
Figure 4 shows the L4901A with a back up battery
on the V
01
output to maintain a CMOS time-of-day
clock and a stand by type N-MOS
P. The reset
output makes sure that the RAM is forced into the
low consumption stand by state, so the access to
memory is inhibit and the back up battery voltage
cannot drop so low that memory contents are cor-
rupted.
In this case the main on-off switch disconnects both
regulators from the supply battery.
The L4901A is also ideal for microcomputer sys-
tems using battery backup CMOS static RAMs. As
shown in Figure 5 the reset output is used both to
Figure 4
Figure 5
L4901A
6/10
disable the
P and, through the address decoder
M74HC138, to ensure that the RAMS are disabled
as soon as the main supply starts to fall.
Another interesting application of the L4901A is in
P system with shadow memories (see Figure 6).
When the input voltage goes below V
IT
, the reset
ouput enables the execution of a routine that saves
the machine's state in the shadow RAM (xicor x
2201 for example).
Thanks to the low consumption of the Reg. 1 a
Figure 6
Figure 7 :
Quiescent Current (reg.1) versus
Output Current
Figure 8 :
Quiescent Current (reg.1) versus
Input Voltage
L4901A
7/10
Figure 9 :
Total Quiescent Current versus
Input Voltage
Figure 10 : Regulator 1 Output Current and Short
Circuit Current versus Input Voltage
Figure 11 : Regulator 1 Output Current and Short
Circuit Current versus Input Voltage
Figure 12 : Supply Voltage Rejection
Regulators 1 and 2 versus Input Rip-
ple Frequence
L4901A
8/10
Heptawatt V
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.8
0.189
C
1.37
0.054
D
2.4
2.8
0.094
0.110
D1
1.2
1.35
0.047
0.053
E
0.35
0.55
0.014
0.022
E1
0.7
0.97
0.028
0.038
F
0.6
0.8
0.024
0.031
F1
0.9
0.035
G
2.34
2.54
2.74
0.095
0.100
0.105
G1
4.88
5.08
5.28
0.193
0.200
0.205
G2
7.42
7.62
7.82
0.295
0.300
0.307
H2
10.4
0.409
H3
10.05
10.4
0.396
0.409
L
16.7
16.9
17.1
0.657
0.668
0.673
L1
14.92
0.587
L2
21.24
21.54
21.84
0.386
0.848
0.860
L3
22.27
22.52
22.77
0.877
0.891
0.896
L4
1.29
0.051
L5
2.6
2.8
3
0.102
0.110
0.118
L6
15.1
15.5
15.8
0.594
0.610
0.622
L7
6
6.35
6.6
0.236
0.250
0.260
L9
0.2
0.008
M
2.55
2.8
3.05
0.100
0.110
0.120
M1
4.83
5.08
5.33
0.190
0.200
0.210
V4
40
(typ.)
Dia
3.65
3.85
0.144
0.152
A
L
L1
C
D1
L5
L2
L3
D
E
M1
M
H3
Dia.
L7
L6
F1
H2
F
G
G1
G2
E1
F
E
L9
V4
L4
H2
V
V
HEPTAMEC
H1
OUTLINE AND
MECHANICAL DATA
L4901A
9/10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification
mentioned in this publication are subject to change without notice. This publication supe rsedes and replaces all information
previouslysupplied. STMicroelectronics products are not authorized for use as critical comp onents in life support devices or systems
without express written approval of STMicroelectronics.
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L4901A
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