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Электронный компонент: L4973D3

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L4973V3.3 - L4973V5.1
L4973D3.3 - L4973D5.1
3.5A STEP DOWN SWITCHING REGULATOR
UPTO 3.5ASTEP DOWN CONVERTER
OPERATING INPUT VOLTAGE FROM 8V TO
55V
3.3V AND 5.1V (
1%) FIXED OUTPUT, AND
ADJUSTABLE OUTPUTS FROM:
0V TO 50V (3.3V type)
5.1V TO 50V (5.1 type)
FREQUENCY ADJUSTABLE UP TO 300KHz
VOLTAGE FEED FORWARD
ZERO LOAD CURRENT OPERATION (min
1mA)
INTERNAL CURRENT LIMITING (PULSE BY
PULSE AND HICCUP MODE)
PRECISE 5.1V (1.5%) REFERENCE VOLT-
AGE EXTERNALLY AVAILABLE
INPUT/OUTPUT SYNCHRONIZATION FUNC-
TION
INHIBIT FOR ZERO CURRENT CONSUMP-
TION (100
A Typ. at V
CC
= 24V)
PROTECTION AGAINST FEEDBACK DIS-
CONNECTION
THERMAL SHUTDOWN
OUTPUT OVERVOLTAGE PROTECTION
SOFT START FUNCTION
DESCRIPTION
The L4973 is a step down monolithic power
switching regulator delivering 3.5A at fixed volt-
ages of 3.3V or 5.1V and using a simple external
divider output adjustable voltage up to 50V.
Realized in BCD mixed technology, the device
April 2000
L4973
V
CC
(8V to 55V)
C
IN
C2
R
OSC
C
OSC
D1
L1
C
OUT
V
O
(3.3V or 5.1V)
C
BOOT
4,5,6,
13,14,15
7
9
8
1
11
3
10
D97IN554A
17
R
COMP
C
COMP
C
SS
2
16
12
TYPICAL APPLICATION CIRCUIT (POWERDIP)
POWERDIP (12+3+3)
SO20(12+4+4)
ORDERING NUMBERS:
L4973V3.3 (Powerdip)
L4973D3.3
(SO20)
L4973V5.1 (Powerdip)
L4973D5.1
(SO20)
MULTIPOWER BCD TECHNOLOGY
1/16
uses an internal power D-MOS transistor (with a
typical Rdson of 0.15ohm) to obtain very high effi-
ciency and very fast switching times.
Switching frequency up to 300KHz are achievable
(the maximum power dissipation of the packages
must be observed).
A wide input voltage range between 8V to 55V
and output voltages regulated from 3.3V to 40V
cover the majority of the today applications.
Features of this new generation of DC-DC con-
verter includes pulse by pulse current limit, hiccup
mode for output short circuit protection, voltage
feed forward regulation, soft start, input/output
synchronization, protection against feedback loop
disconnection, inhibit for zero current consump-
tion and thermal shutdown.
Packages available are in plastic dual in line, DIP-
18 (12+3+3) for standard assembly, and SO20
(12+4+4) for SMD assembly.
PIN CONNECTIONS (Top view)
OSC
OUT
OUT
GND
GND
V
CC
GND
V
CC
BOOT
1
3
2
4
5
6
7
8
9
INH
VFB
COMP
GND
GND
GND
V5.1
SS
SYNC
18
17
16
15
14
12
13
11
10
D94IN162A
POWERDIP (12+3+3)
OSC
OUT
OUT
GND
GND
GND
GND
V
CC
V
CC
VFB
COMP
GND
GND
GND
GND
V5.1
SS
SYNC
1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
BOOT
INH
D94IN163A
SO20 (12+4+4)
VREF
GOOD
5.1V
COMP
VFB
SYNC
BOOT
DRIVER
HICCUP CURRENT
LIMITING
INTERNAL
REFERENCE
SS
INH
ZERO CURRENT
INHIBIT
D94IN161B
+
-
3.3V
V5.1
E/A
SOFT
START
5.1V
3.3V
THERMAL
SHUTDOWN
INTERNAL
SUPPLY
5.1V
-
+
PWM
CURRENT
LIMITING
R
S
Q
Q
CBOOT
CHARGE
OSCILLATOR
OUT
OUT
GND
OSC
V
CC
V
CC
17(19)
11(12)
12(13)
18(20)
1(1)
2(2)
3(3)
9(10)
8(9)
7(8)
16(18)
10(11)
4,5,6,13,14,15
(4,5,6,7,14,15,16,17)
Pin x = Powerdip
Pin (x) = S020
BLOCK DIAGRAM
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
2/16
PIN FUNCTIONS
Powerdip
SO20
NAME
DESCRIPTION
11
12
COMP
E/A output to be used for frequency compensation
10
11
INH
A logic signal (active high) disables the device (sleep mode operation).
If not used it must be connected to GND; if floating the device is disabled.
9
10
BOOT
A capacitor connected between this pin and the output allows to drive the
internal D-MOS.
18
20
SYNC
Input/Output synchronization.
7,8
8,9
Vcc
Unregulated DC input voltage
2,3
2,3
OUT
Stepdown regulator output.
12
13
VFB
Stepdown feedback input. Connecting the output directly to this pin results
in an output voltage of 3.3V for the L4973V3.3 and 5.1V. An external
resistive divider is required for higher output voltages. For output voltage
less than 3.3V, see note ** and Figure 32.
16
18
V5.1
Reference voltage externally available.
4,5,6
13,14,15
4,5,6,7
14,15,16,17
GND
Signal ground
1
1
OSC
An external resistor connected between the unregulated input voltage and
Pin 1 and a capacitor connected from Pin 1 to ground fixes the switching
frequency. (Line feed forward is automatically obtained)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
DIP-18
S0-20
V
7
,V
8
V
9
,V
8
Input voltage
58
V
V
2
,V
3
V
2
,V
3
Output DC voltage
Output peak voltage at t = 0.1
s f=200KHz
-1
-5
V
V
I
2
,I
3
I
2
,I
3
Maximum output current
int. limit.
V
9
-V
8
V
10
-V
8
14
V
V
9
V
10
Bootstrap voltage
70
V
V
11
V
12
Analogs input voltage (V
CC
= 24V)
12
V
V
17
V19
Analogs input voltage (V
CC
= 24V)
13
V
V
12
V
13
(V
CC
= 20V)
6
-0.3
V
V
V
18
V
20
(V
CC
= 20V)
5.5
-0.3
V
V
V
10
V
11
Inhibit
Vcc
-0.3
V
V
P
tot
Power dissipation a T
pins
90
C
(T
amb
= 70
C no copper area)
(T
amb
= 70
C 4cm copper area on PCB)
DIP
12+3+3
5
1.3
2
W
W
W
Power dissipation a T
pins
= 90
C
SO20
4
W
T
J
,T
STG
Junction and storage temperature
-40 to 150
C
THERMAL DATA
Symbol
Parameter
Powerdip
SO20
Unit
R
th(j-pin)
Thermal Resistance Junction to pin
Max.
12
15
C/W
R
th(j-amb)
Thermal Resistance to Ambient
Max.
60 (*)
80 (*)
C/W
(*) Package mounted on board.
L4973V3 - L4973V5 - L4973D3 - L4973D5
3/16
ELECTRICAL CHARACTERISTICS ( Refer to the test circuit,V
CC
= 24V; T
j
= 25
C, C
OSC
= 2.7nF;
R
OSC
= 20K
; unless otherwise specified)
= specifications referred to T
J
from 0 to 125
C.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DYNAMIC CHARACTERISTICS
Input Voltage Range (*)
V
O
= V
REF
to 40V; I
O
= 3.5A
8
55
V
Output Voltage
L4973V5.1
I
O
= 1A
5.05
5.1
5.15
V
I
O
= 0.5A to 3.5A
5.00
5.1
5.20
V
V
CC
= 8V to 55V
4.95
5.1
5.25
V
Output Voltage
L4973V3.3
I
O
= 1A
3.326
3.36
3.393
V
I
O
= 0.5A to 3.5A
3.292
3.36
3.427
V
V
CC
= 8V to 40V
3.26
3.36
3.46
V
R
DSON
V
CC
= 10.5V
0.15
0.22
I
O
= 3.5A
0.35
Maximum Limiting Current
V
CC
= 8V to 55V
4
4.5
5.5
A
Efficiency
V
O
= 5.1V; I
O
= 3.5A
90
%
V
O
= 3.3V; I
O
= 3.5A
85
%
Switching Frequency
90
100
110
KHz
Supply Voltage Ripple
Rejection
V
i
= V
CC
+2V
RMS
V
O
= V
ref
; I
O
= 1A; f
ripple
= 100Hz
60
dB
f
sw
Switching Frequency Stability
vs, Supply Voltage
V
CC
= 8V to 55V
2
5
%
REFERENCE SECTION
Reference Voltage
5.025
5.1
5.175
V
I
ref
= 0 to 20mA;
V
CC
= 8 to 55V
4.950
5.1
5.250
V
Line Regulation
I
ref
= 0mA;
V
CC
= 8 to 55V
5
10
mV
Load Regulation
V
ref
= 0 to 5mA;
V
CC
= 0 to 20mA
2
6
10
25
mV
mV
Short Circuit Current
30
65
100
mA
SOFT START
Soft Start Charge Current
30
45
60
A
Soft Start Discharge Current
15
22
30
A
INHIBIT
High Level Voltage
3.0
V
Low Level Voltage
0.8
V
I
source
High Level
V
INH
= 3V
10
16
50
A
I
source
Low Level
V
INH
= 0.8V
10
15
50
A
DC CHARACTERISTICS
Total Operating Quiescent
Current
Duty Cycle = 50%
4
6
mA
Quiescent Current
Duty Cycle = 0
2.7
4
mA
Total stand-by quiescent
current
V
CC
= 24V; V
INH
= 5V
100
200
A
V
CC
= 55V; V
INH
= 5V
150
300
A
ERROR AMPLIFIER
High Level Output Voltage
11.0
V
Low Level Output Voltage
0.65
V
Source Bias Current
1
2
3
A
Source Output Current
200
300
600
A
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
4/16
Sink Output Current
200
300
A
Supply Voltage Ripple
Rejection
V
COMP
= VFB
C
REF
=4.7
F 1-5mA load
current
60
80
dB
DC Open Loop Gain
R
L
=
50
60
dB
Transconductance
I
comp
= -0.1 to 0.1mA;
V
comp
= 6V
2.5
mS
OSCILLATOR SECTION
Ramp valley
0.78
0.85
0.92
V
Ramp peak
V
CC
= 8V
1.9
2.1
2.3
V
V
CC
= 55V
9
9.6
10.2
V
Maximum Duty Cycle
95
97
%
Maximum Frequency
Duty Cycle = 0%; R
OSC
=
13K
; C
OSC
= 820pF;
500
KHz
SYNC FUNCTION
High Input Voltage
V
CC
= 8V to 55V
3.5
V
Low Input Voltage
V
CC
= 8V to 55V
0.9
V
Slave Sink Current
0.15
0.25
0.45
mA
Master Output Amplitude
I
source
= 3mA
4
4.5
V
Output Pulse Width
no load, V
sync
= 4.5V
0.20
0.35
s
(*) Pulse testing with a low duty cycle.
(**) The maximum power dissipation of the package must be observed.
ELECTRICAL CHARACTERISTICS (continued)
L4973
V
CC
C1
C2
R2
C7
C3
C4
C5
C6
R1
D1
L1
3 x
C0
C12
R3
R4
V
O
C8
4,5,6
13,14,15
7,8
9
1
17
16
11
2,3
12
D97IN515B
(DIP18)
10
C1=1000
F/63V
C2=220nF/63V
C3=470nF
C4=1
F/50V
C5=220pF
C6=22nF
C7=2.7nF
C8=220nF/63V
C0=100
F/40V(C9,C10,C11)
C12=Optional (220nF)
L1=150
H K
OOL
77310 - 40 Turns - 0.9mm
R1=9.1K
R2=20K
D1=GI SB560
V
O
(V)
R3(K
)
R4(K
)
3.3
5.1
12
15
18
24
0
2.7
12
16
20
30
4.7
4.7
4.7
4.7
4.7
L4973 V3.3
V
O
(V)
R3(K
)
R4(K
)
5.1
12
15
18
24
0
6.2
9.1
12
18
4.7
4.7
4.7
4.7
L4973 V5.1
Figure 1. Evaluation Board Circuit
L4973V3 - L4973V5 - L4973D3 - L4973D5
5/16
Output Voltage
Output
Ripple
Efficiency
Line Regulator
I
o
= 3.5A V
CC
= 8 to 50V
Load Regulator
V
CC
=35V I
O
= 1 to 3.5A
3.3V
20mV
81.5 (%)
3mV
6mV
5.1V
20mV
86.7 (%)
3mV
6mV
12V
30mV
93.5 (%)
3mV (V
CC
=15 to 50V)
4mV
Typical Performance (Using Evaluation Board) fsw = 100kHz
Figure 1a: Evaluation Board (Components Side)
Figure 1b: Evaluation Board (Solder Side)
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
6/16
L4973V3.3
V
CC
C1
C2
R2
C7
C3
C4
C5
C6
R1
D1
L1
3 x
C0
C12
Vo
C8
4,5,6
13,14,15
7,8
10
18
9
1
17
16
INH
SYNC
11
2,3
12
D97IN664A
Figure 1d: Application Circuit (see fig. 1 part list)
L4973V5.1
V
CC
C1
C2
R2
C7
C3
C4
C5
C6
R1
D1
L1
3 x
C0
C12
Vo
C8
4,5,6
13,14,15
7,8
10
18
9
1
17
16
INH
SYNC
11
2,3
12
D97IN665A
Figure 1c: Application Circuit (see fig. 1 part list)
0
10
20
30
40
50
V
CC
(V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Ibias
(mA)
Tamb=25
C
0% DC
D97IN633A
100KHz-R2=20K
C7=2.7nF
200KHz-R2=22K
C7=1.2nF
0Hz
Figure 2: Quiescent Drain Current vs. Input
Voltage (0% Duty Cycle)
-50
0
50
100
Tj(
C)
2.5
3.0
3.5
4.0
Ibias
(mA)
D97IN634
100KHz-R2=20K
C7=2.7nF
200KHz-R2=22K
C7=1.2nF
0Hz
0% DC
V
CC
= 35V
Figure 3: Quiescent Drain Current vs. Junction
Temperature
L4973V3 - L4973V5 - L4973D3 - L4973D5
7/16
0
10
20
30
40
50
V
CC
(V)
50
100
150
Ibias
(
A)
D97IN635A
25
C
125
C
V
inh
= 5V
Figure 4: Stand by Drain Current vs. input
Voltage
-40
0
40
80
Tj(
C)
-20
20
60
100
5.0
5.05
5.1
5.15
V
REF
(V)
D97IN637
Vcc=35V
Pin 16
Figure 5: Reference Voltage vs. Junction
Temperature (Pin 16)
0
10
20
30
40
50
V
CC
(V)
5.0
5.05
5.1
5.15
V
REF
(V)
D97IN636A
Tj=25
C
Pin 16
Figure 6: Reference Voltage vs. Input Voltage
(Pin 16)
0
10
20
30
40
50 I
REF
(mA)
4.9
5.0
5.1
5.2
V
REF
(V)
D97IN638
Tj=25
C
Vcc=10V
Vcc=40V
Figure 7: Reference Voltage vs. Reference Input
Current
0
15
Vinh(V)
10
5
-50
0
50
100
Iinh
(
A)
D97IN651
Tj=0
C
Tj=25
C
Tj=125
C
Vcc=35V
Pin 10
Figure 8: Inhibit Current vs. Inhibit Voltage
(Pin 10)
0
10
20
30
40
50
V
CC
(V)
5.06
5.08
5.1
5.12
V
O
(V)
D97IN639A
Tj=25
C
Tj=125
C
I
O
= 1A
Figure 9: Line Regulation (see fig. 1)
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
8/16
0
1
2
3
I
O
(A)
5.0
5.05
5.1
5.15
V
O
(V)
D97IN640
Tj=25
C
Tj=125
C
V
CC
= 35V
Figure 10: Load Regulation (see fig. 1c)
0
10
20
30
40
50
V
CC
(V)
3.3
3.31
3.32
3.34
V
O
(V)
3.33
3.35
D97IN660A
Tj=25
C
Tj=125
C
I
O
= 1A
Figure 11: Line Regulation (see fig. 1d)
0
1
2
3
I
O
(A)
3.3
3.31
3.33
3.35
V
O
(V)
3.32
3.34
D97IN661
Tj=25
C
Tj=125
C
V
CC
= 35V
Figure 12: Load Regulation (see fig. 1d)
0
20
40
60
80
R2(K
)
5
10
20
50
100
200
500
fsw
(KHz)
D97IN630
0.82nF
1.2nF
2.2nF
3.3nF
4.7nF
5.6nF
Tamb=25
C
Figure 13: Switching Frequency vs.R2 and C7
(fig. 1)
0
10
20
30
40
50
V
CC
(V)
90
95
100
105
fsw
(KHz)
D97IN631
Tamb=25
C
Figure 14: Switching Frequency vs. Input Voltage
-50
0
50
100
Tj(
C)
90
95
100
105
fsw
(KHz)
D97IN632
Figure 15: Switching Frequency vs. Junction
temperature (see fig. 1)
L4973V3 - L4973V5 - L4973D3 - L4973D5
9/16
0
1
2
3
I
O
(A)
0
0.2
0.4
0.6
V
(V)
D97IN643
Tj=0
C
Tj=125
C
Tj=25
C
Figure 16: Dropout Voltage Between pin 7,8 and
2,3
0
10
20
30
V
O
(V)
40
86
88
90
92
(%)
94
96
98
D97IN641
200KHz
100KHz
I
O
= 3A
V
CC
= 50V
Figure 17: Efficiency vs. Output Voltage
(see fig.1)
0
10
15
20
V
O
(V)
30
5
25
86
88
90
92
(%)
94
96
98
D97IN642
200KHz
100KHz
I
O
= 3A
V
CC
= 35V
Figure 18: Efficiency vs. Output Voltage
(Diode STPS745D)
0
1
2
3
I
O
(A)
80
85
90
95
(%)
D97IN645
Vcc=12V
Vcc=24V
Vcc=48V
V
O
= 5.1V
f
sw
= 100KHz
Figure 19: Efficiency vs. Output Current
( see fig.1c)
0
1
2
3
I
O
(A)
75
80
85
90
(%)
D97IN646
Vcc=12V
Vcc=24V
Vcc=48V
V
O
= 5.1V
f
sw
= 200KHz
Figure 20: Efficiency vs. Output Current
(see fig.1c)
0
1
2
3
I
O
(A)
75
80
85
90
(%)
D97IN644
Vcc=12V
Vcc=24V
Vcc=48V
V
O
= 3.3V
f
sw
= 100KHz
Figure 21: Efficiency vs. Output Current
(see fig.1d)
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
10/16
0
1
2
3
I
O
(A)
0.5
1.5
2.5
3.5
70
75
85
(%)
80
90
D97IN662
Vcc=48V
Vcc=12V
Vcc=24V
V
O
= 3.3V
f
sw
= 200KHz
Figure 22: Efficiency vs. Output Current
(see fig.1d)
0
10
30
40
Vcc(V)
20
50
0
0.5
1.0
1.5
Pdiss
(W)
D97IN647A
I
O
=3.5A
I
O
=3A
I
O
=2A
I
O
=2.5A
V
O
= 5.1V
f
sw
= 100KHz
Figure 23: Power dissipation vs. Input Voltage
(Device only) (see fig.1c)
0
5
15
20
V
O
(V)
10
25
30
0
0.5
1.0
1.5
Pdiss
(W)
2.0
2.5
3.0
D97IN648
I
O
=3.5A
I
O
=3A
I
O
=1A
I
O
=2A
I
O
=2.5A
V
CC
= 35V
f
sw
= 100KHz
Figure 24: Power dissipation vs. Output Voltage
(Device only)
-40 -20
60 80
Tj(
C)
0
120
20 40
100
4.2
4.4
4.6
4.8
Ilim
(A)
5
5.2
D97IN652
Vcc=35
Figure 25: Pulse by Pulse Limiting Current vs.
Junction Temperature
1
2
I
O
(A)
3
2
1
V
O
(mV)
100
0
-100
D97IN649
T
T
200
s/DIV
V
CC
= 35V
f
sw
= 100KHz
Figure 26: Load Transient
2
1
D97IN650
V
CC
(V)
30
20
10
V
O
(mV)
100
0
-100
1ms/DIV
I
O
= 1A
f
sw
= 100KHz
Figure 27: Line Transient
L4973V3 - L4973V5 - L4973D3 - L4973D5
11/16
Figure 28: Source Current Rise and Fall Time,
pin 2, 3 (See fig1)
25
30
35
40
Vi(V)
50
45
0
50
100
150
Lomax
(
H)
200
250
300
D97IN653
Css=100nF
Css=220nF
Css=470nF
Css=680nF
Css=820nF
Css=1
F
f
sw
= 100KHz
Figure 29: Soft Start Capacitor Selection vs.
Inductor and V
CC
max (ref. AN938)
15
20
25
30
Vi(V)
40
35
45
50
0
50
100
150
Lomax
(
H)
D97IN654
Css=22nF
Css=33nF
Css=47nF
Css=56nF
Css=68nF
f
sw
= 200KHz
Figure 30:Soft Start Capacitor Selection vs. In-
ductor and V
CC
max (ref. AN938)
10
10
3
10
5
10
7
f(Hz)
10
2
10
4
10
6
10
8
-200
-150
-100
-50
GAIN
(dB)
0
50
Phase
0
45
90
135
D97IN663
GAIN
Phase
Figure 31: Open Loop Frequency and Phase of
Error amplifier
L4973V3.3
V
CC
C1
C2
R2
C7
C3
C4
C5
C6
R1
D1
L1
3 x
C0
Vo
C8
4,5,6
13,14,15
7,8
10
18
9
1
17
INH
SYNC
11
2,3
12
16
R3
D97IN666A
R5
V
P
R
5
R
3
1
3.6K
4.7K
1.5
2K
2K
2
4.7K
3.6K
2.5
7.5K
3.6K
3
5.1K
1K
V
O
=3.36-1.74
R
3
R
5
Figure 32: 3.5A at V
O
< 3.3V (see part list fig. 1)
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
12/16
L1
KoolMm 77120- 24 Turns- 0.9mm
D1
STPS1025
L4973V3.3
V
CC
12V
5%
C1
560uF-25V
HFQ
Panasonic
C2
220nF
R2
22k
C7
1.2nF
C3
33nF
C4
1uF
C5
220pF
C6
22nF
R1
9k1
D1
L1
C9
470uF-25V
HFQ
Panasonic
Vo=3.33V
Io=3.5A
C8
220nF
4,5,6
13,14,15
7,8
10
18
9
1
17
16
INH
SYNC
11
2,3
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Io(A)
80
82
84
86
88
90
92
(%)
D97IN668A
Figure 33: 12V to 3.3V High Performance Buck Converter (f
sw
= 200kHz)
L4973
L4973
18
18
V
CC2
D97IN669
1
7,8
V
CC1
1
7,8
4,5,6
13,14,15
4,5,6
13,14,15
L4973
L4973
18
18
V
CC
1
7,8
1
7,8
4,5,6
13,14,15
4,5,6
13,14,15
Figure 34: Synchronization Example
L4973
V
CC
C1
C2
R2
C7
C3
C4
C5
C6
R1
D1
L1
C9
C10
Vo1
C8
4,5,6
13,14,15
7,8
10
18
9
1
17
16
INH
SYNC
11
2,3
12
C11
Vo2
n1
n2
D2
D97IN667A
V
O2
= V
O1
n
1
+ n
2
n
1
P
O2
< 20% P
O1
Figure 35: Multioutput not Isolated (Pin out referred to DIP12+3+3)
L4973V3 - L4973V5 - L4973D3 - L4973D5
13/16
Powerdip 18
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.85
1.40
0.033
0.055
b
0.50
0.020
b1
0.38
0.50
0.015
0.020
D
24.80
0.976
E
8.80
0.346
e
2.54
0.100
e3
20.32
0.800
F
7.10
0.280
I
5.10
0.201
L
3.30
0.130
Z
2.54
0.100
OUTLINE AND
MECHANICAL DATA
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
14/16
1
1
0
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
SO20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0
(min.)8
(max.)
OUTLINE AND
MECHANICAL DATA
L4973V3 - L4973V5 - L4973D3 - L4973D5
15/16
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L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
16/16