ChipFind - документация

Электронный компонент: L5950

Скачать:  PDF   ZIP
5 REGULATORS
10V (350mA); 8.5V (175mA); 5V (350mA); 5V
(250mA); 8V/10V (1A)
ALL REGULATORS ARE LOW DROPOUT
OUPUTS
3 HIGH SIDE DRIVERS:
2A (HSD1), 0.45A (HSD2 & HSD3)
NO EXTERNAL CHARGE PUMP CAPACI-
TORS ARE REQUIRED
STAND BY MODE CONTROLLED BY 3 IN-
PUT PINS:
ENABLE FOR REG2 AND REG3,
I
2
C BUS FOR REG1, REG4, REG5, HSD1,
HSD2, HSD3
INDIVIDUAL THERMAL SHUTDOWN
INDEPENDENT CURRENT LIMITING
SHORT CIRCUIT PROTECTION
LOAD DUMP PROTECTION AND OVERVOL-
TAGE SHUTDOWN
ESD PROTECTED
DESCRIPTION
The ASPM (Audio System Power Module) is an
integration of three high side drivers and five
regulators developed to provide the power for an
audio system.
The outputs of the IC are controlled via the I
2
C
bus and the Enable input.
External protection must be provided for reverse
battery protection.
March 2001
VOLTAGE
REFERENCE
REG 1
10V 350mA
REG 2
8.5V 175mA
REG 3
5V 350mA
REG 4
8V/10V 1A
REG 5
5V 250mA
8.5 & 5V
ENABLE
PC OUTPUT
CONTROL
CURRENT
LIMIT
PROTECTION
LOGIC
INDIVIDUAL
THERMAL
SHUTDOWN
OVERVOLTAGE
PROTECTION
DRIVE 1
2A
DRIVE 2
450mA
DRIVE 3
450mA
REG1
REG2
REG3
REG4
REG5
HSD1
HSD2
HSD3
BAT
GND
VREF
ENABLE
SCL
SDA
D99AU1002
BLOCK DIAGRAM
Multiwatt15
L5950
MULTIPLE MULTIFUNCTION
VOLTAGE REGULATOR FOR CAR RADIO
1/8
THERMAL DATA
Symbol
Parameter
Value
Unit
Rth j-case
Thermal Resistance Junction-case
2
C/W
1
2
3
4
5
6
7
9
10
11
8
REG2
REG1
VREF
GND
SCL
Enable
SDA
HSD3
HSD2
BAT
HSD1
13
14
15
12
REG4
BAT
REG5
REG3
D99AU1006
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
DC Operating Supply Voltage
-0.6 to 26.5
V
V
S
Transient Supply Overvoltages, rise time = 10ms
delay time = 115ms
34
V
V
in
Input Voltages (EN, SDA, SCL)
-0.6 to 9
V
V
out
Output Control Voltage
-0.6 to 6.0
V
T
op
Operating Temperature Range
-40 to 85
C
T
stg
Storage Temperature Range
-40 to 150
C
L5950
2/8
ELECTRICAL CHARACTERISTICS (Refer to the application circuit, V
S
= 14.4V; T
amb
= 25C; unless
otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
I
q,ST-BY
Standby Quiescent Current
All Outputs Off, V
BAT
= 14V
2
A
I
q
Maximum Quiescent Current
V
BAT
= 14V, I
REG1
= 350mA,
I
REG2
= 175mA, I
REG3
= 350mA,
I
REG4
= 1A, I
REG5
= 250mA,
I
HSD1
= 2A, I
HSD2,3
= 450mA
150
mA
I
EN
Enable Input Current
V
BAT
= 14V,
Enable
2V
V
BAT
= 14V,
Enable
0.8V
-10
10
A
A
V
IL
, V
IH
Enable Threshold Voltage
V
BAT
= 14V, V
IL
V
BAT
= 14V, V
IH
2
0.8
V
V
10V/350mA REG 1 OUTPUT
V
REG1
Output Voltage
I
REG1
= 350mA
11V
V
CC
16V
9.50
10
10.5
V
V
line
Line Regulation
11V
V
CC
26V
(Measure
V
REG1
Across V
CC
Range)
55
mV
V
load
Load Regulation
5mA
I
REG1
350mA
55
mV
V
DROPOUT
Dropout Voltage (Measure
V
BAT
- V
REG1
when V
REG1
drops
0.1V)
(Measure V
BAT
- V
REG1
when
V
REG1
drops 0.1V)
I
REG1
= 350mA
I
REG1
= 5mA
900
300
mV
mV
I
lim1
Current Limit
0.51
1.1
A
SVR
Ripple Rejection
f
o
= 1kHz, V
BAT
= 14V
with 1Vpp AC
I
REG1
= 175mA
50
dB
8.5V/175mA REG 2 OUTPUT
V
REG2
Output Voltage
I
REG2
= 175mA
9.5V
V
BAT
16V
8.3
8.5
8.7
V
V
line
Line Regulation
9.5V
V
BAT
26V
(Measure
V
REG2
Across V
BAT
Range)
50
mV
V
load
Load Regulation
5mA
I
REG2
175mA
50
mV
V
DROPOUT
Dropout Voltage
(Measure VBAT- V
REG2
when
V
REG2
drops 0.1V)
I
REG2
= 175mA
I
REG2
= 5mA
900
300
mV
mV
I
lim2
Current Limit
280
525
mA
SVR
Ripple Rejection
f
o
= 1kHz, V
BAT
= 14V
with 1Vpp AC
I
REG2
= 100mA
50
dB
5V/350mA REG 3 OUTPUT
V
REG3
Voltage Offset from VREF
10
40
mV
V
line
Line Regulation
7V
V
BAT
26V
(Measure
V
REG3
Across V
BAT
Range)
40
mV
V
load
Load Regulation
5mA
I
REG3
350mA
100
mV
L5950
3/8
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
DROPOUT
Dropout Voltage (Measure
VBAT- V
REG3
when V
REG3
drops 0.1V)
(Measure VBAT- V
REG3
when
V
REG3
drops 0.1V)
I
REG3
= 175mA
I
REG3
= 5mA
950
600
mV
mV
I
lim3
Current Limit
0.5
1
A
SVR
Ripple Rejection
f
o
= 1kHz, V
BAT
= 14V
with 1Vpp AC
I
REG3
= 175mA
50
dB
8/10V/1A REG 4 OUTPUT
V
REG4
Output Voltage
I
REG4
= 1A
b5 = 0
b5 = 1
7.6
9.50
8
10
8.4
10.5
V
V
V
line
Line Regulation
11V
V
BAT
26V, b5 = 1
(Measure
V
REG2
Across V
BAT
Range)
50
mV
V
load
Load Regulation
5mA
I
REG4
1A
150
mV
V
DROPOUT
Dropout Voltage
(Measure VBAT- V
REG2
when
V
REG2
drops 0.1V)
I
REG4
= 1A
I
REG4
= 5mA
950
600
mV
mV
I
lim4
Current Limit
1.3
2.4
A
SVR
Ripple Rejection
f
o
= 1kHz, V
BAT
= 14V
with 1Vpp AC
I
REG4
= 500mA
50
dB
5V/250mA REG 5 OUTPUT
V
REG5
Output Voltage
I
REG5
= 250mA
4.75
5
5.25
V
V
line
Line Regulation
7V
V
BAT
26V
(Measure
V
REG5
Across V
BAT
Range)
40
mV
V
load
Load Regulation
5mA
I
REG5
250mA
100
mV
V
DROPOUT
Dropout Voltage
(Measure VBAT- V
REG5
when
V
REG5
drops 0.1V)
I
REG5
= 250A
I
REG5
= 5mA
1.6
1.2
V
V
I
lim5
Current Limit
320
700
mA
SVR
Ripple Rejection
f
o
= 1kHz, V
BAT
= 14V
with 1Vpp AC
I
REG5
= 125mA
50
dB
2A HSD1
V
sat
Output Saturation Voltage
IHSD1 = 1A
Continuous Time Operation
0.5
V
I
leak1
Output Leakage Current
All Driver Outputs are Off
-50
50
A
I
lim
Current Limiting
R
HSD1
= 0.5
2.4
4
A
0.45A HSD2 & HSD3
V
sat
Output Saturation Voltage
IHSD2,3 = 300mA
Continuous Time Operation
0.6
V
I
leak2,3
Output Leakage Current
All Driver Outputs are Off
-50
50
A
I
lim
Current Limiting
R
HSD2,3
= 0.5
0.56
1
A
ELECTRICAL CHARACTERISTICS (continued)
L5950
4/8
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
CHARACTERISTICS FOR I
2
C
V
IL
LOW Level Input Voltage
1.5
V
V
IH
HIGH Level Input Voltage
3
V
V
HYS
Input Hysteresis
0.2
V
V
OL1
V
OL2
LOW Level Output
Sink Current = 3mA
Sink Current = 6mA
0.4
0.6
V
V
I
I
Input Current
0.4V
V
I
0.9V
DDmax
-10
10
A
f
SCL
SCL Clock Frequency
400
kHz
ELECTRICAL CHARACTERISTICS (continued)
FUNCTIONAL DESCRIPTION
The three high side drivers are a 2.0A output
(HSD1), and two 450mA outputs (HSD2 & 3). The
five regulator outputs are a 10V at 350mA
(REG1), an 8.5V at 175mA (REG2), a 5V at
350mA (REG3), an 8V/10V at 1A (REG4), and 5V
at 250mA (REG5). The regulators are low drop-
out. The regulators will operate with output ca-
pacitors with ESR of 0.1
to 5
.
The 8.5V regulator output (REG2) is a tighter tol-
erance output than the other regulator outputs.
The 8.5V output is a
2.5% (5% total range) out-
put over temperature. This is required on the
regulator to improve performance and reduce
cost on the 8.5V driven IC's in the radio. The
tighter tolerance is possible by performing a trim
of the bandgap reference to the 8.5V output. The
other outputs are
5% variation over temperature.
REG3 is referenced from the VREF input not the
internal bandgap. This is done to minimize the
voltage offset between individual 5V supplies.
The REG2 and REG3 outputs are turned on and
off with the Enable input, a '1' turns the outputs on
and a '0' turns them off. When Enable is "1", the
other outputs can be independently controlled via
the I
2
C bus. When a given regulator is turned off it
must be guaranteed to be lower than 0.2V. The
output voltage of REG4 is selected via bit 5 of the
I
2
C data byte: 8V is the output voltage if bit5 = '0'
while 10V is the output voltage when bit5 = '1'.
When all outputs are turned off the total current
draw must be minimized. I
2
C will run at a clock
speed range of 100kHz to 400kHz. This device
should be capable of operating at any frequency
within this range.
Protection
The L5950 can survive under the following condi-
tions: shorting the outputs to BAT and GND, loss
of BAT, loss of IC GND, double battery(+26.5V),
4000V ESD, 34V load dump. L5950 will not han-
dle a reverse battery condition. External compo-
nents must be implemented for reverse battery
protection.
Thermal Shutdown: REG1, REG2, REG3, REG4,
REG5 outputs shutdown at 160C and return to
normal operation at 130C. The HSD2 and HSD3
shutdown at 160C and return to normal opera-
tion at 130C. The HSD1 with go into thermal
shutdown at 170C and returns to operation at
120C.
Current Limiting: each voltage regulator will con-
tain its own current protection.
Short Circuit: If the outputs are short circuited, the
IC will go into current limiting and eventually the
thermal shutdown will kick in. Current limiting will
not disable the outputs.
Overvoltage: The IC will not operate if the BAT
voltage reaches 27V typ. or above.
t
BUP
P
S
P
SDA
SCL
Sr
t
LOW
t
R
t
F
t
HD;DAT
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
SU;STO
D99AU1007
t
SP
t
HIGH
Figure 1. Definition of Timing on the I
2
C Bus.
L5950
5/8
FBATT
VREF
C14
10
F
C12
10
F
C10
10
F
C8
10
F
C6
10
F
1000
F
0.1
F
EN
REG5
REG4
REG3
REG2
REG1
REG5
HSD1
ENABLE
BAT
VREF
SCL
SDA
GND
REG4
REG3
HSD2
HSD3
HSD1
HSD2
HSD3
D99AU1010A
REG2
REG1
Figure 2. Typical Application Circuit.
WRITE MODE:
CHIP ADDRESS
DATA BYTE
S
0
A
A
..
..
P
MSB
LSB
MSB
LSB
S = START condition - SDA goes from high to low while SCL is high
A = Acknowledge - the device being written to, pulls down on data line (SDA) during the acknowledge
clock pulse.
P = STOP condition - SDA goes from low to high while SCL is high.
CHIP ADDRESS BYTE:
CHIP ADDRESS
READ/WRITE
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
0
0
0
0
DATA BYTE:
DATA BYTE
REG1
R4 10V
REG4
REG5
HSD1
HSD2
HSD3
b7
b6
b5
b4
b3
b2
b1
b0
X
Default mode is 0000 0000 which corresponds to all outputs being off, low power mode.
Bit 5 Controls the output voltage of REG4. A '0' corresponds to 8V and a '1' corresponds to 10V.
(*) ESR of output capacitors should be between 0.1
and 5.0
.
L5950
6/8
Multiwatt15 V
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
5
0.197
B
2.65
0.104
C
1.6
0.063
D
1
0.039
E
0.49
0.55
0.019
0.022
F
0.66
0.75
0.026
0.030
G
1.02
1.27
1.52
0.040
0.050
0.060
G1
17.53
17.78
18.03
0.690
0.700
0.710
H1
19.6
0.772
H2
20.2
0.795
L
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.870
0.886
L2
17.65
18.1
0.695
0.713
L3
17.25
17.5
17.75
0.679
0.689
0.699
L4
10.3
10.7
10.9
0.406
0.421
0.429
L7
2.65
2.9
0.104
0.114
M
4.25
4.55
4.85
0.167
0.179
0.191
M1
4.63
5.08
5.53
0.182
0.200
0.218
S
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
OUTLINE AND
MECHANICAL DATA
L5950
7/8
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics Printed in Italy All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
L5950
8/8