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L5953

September 2003

This is preliminary information on a new product now in development. Details are subject to change without notice.

PWM: ADJUSTABLE 2.5/10V - 1A
SWITCHING VOLTAGE REGULATOR

EXTERNAL POWER MOS ABILITY FOR
OUTPUT CURRENT ENHANCEMENT

SYNCHRONIZATION FUNCTION

REG1- LINEAR LOW DROP 3.3/5V - 250mA
STBY VOLTAGE REGULATOR (LOW
CURRENT CONSUMPTION) with RESET

REG2- LINEAR VOLTAGE REGULATOR 1.5V
to 3.3V EXTERNALLY ADJUSTABLE - 300mA
MAXIMUM CURRENT

HSD1 : 500mA HIGH SIDE DRIVER

HSD2 : 200mA HIGH SIDE DRIVER

SPI INTERFACE

SPI DIAGNOSTICS HSD1, HSD2

DOUBLE SWITCHING FREQUENCY SPI
SELECTABLE

DOUBLE INPUT LVW

SPI FUNCTIONS

INPUT CONTROLS

Turn-on/off PWM
Turn-on/off REG2
Turn-on/off HSD1
Turn-on/off HSD2
Switching frequency selection f1- f2

OUTPUT FUNCTIONS:

HSD1 & HSD2 short to gnd, open load and

short to battery (Test mode)

Thermal warning

PROTECTIONS

OVERVOLTAGE PROTECTION

INTERNAL CURRENT LIMITING

THERMAL SHUTDOWN

ESD

DESCRIPTION
The L5953 is the integration of one switching regula-
tor, two linear voltage regulators, two low voltage
warnings and two high side drivers. It has a stand-by
operation mode (low current consumption) where
only the stand-by voltage regulator plus the low volt-
age warnings are active. The other regulators and
high side drivers are controlled by the SPI interface.

PowerSO36

ORDERING NUMBER: L5953

PRODUCT PREVIEW

MULTIPLE SWITCHING VOLTAGE REGULATOR

BLOCK DIAGRAM

VOLTAGE WARNING

SPI INTERFACE

REC2

LINEAR VOLTAGE

REGULATOR

1.5-3.3V/300mA

HSD1

HSD2

COMP

GATEOUT

GATEIN

VSW

DRAINOUT

STRAP

ADJ

VSTBY

GND

SWGND

VDD-LIN

REC1

ST-BY LINEAR VOLTAGE

REGULATOR

3.3-5V/250mA

PWM

STEP DOWN
REGULATOR

2.5-10V/1A

OSCILLATOR &

SYNC

STCAP

RES

VDD-SW

IRQ

VLR

FBLR

VIN

SYNC

VSPI

DGND

FGND

D01AU1330A

L5953

2/24

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

PIN CONNECTION

Symbol

Parameter

Value

Unit

DC Operating Supply Voltage

-0.6 to 30

Transient Supply Overvoltage (250ms)

SPI

Supply Voltage for SPI I/O

-0.6 to 6

Voltage Regulator Output Current

Internally limited

inlog

Input Voltage (C,D,Q,

,SYNC)

0 to 6

RESR

Output Capacitor Series Eq. Resistance (Linear reg.)(Allowed
range)

From 0.2 to 10

Operating Temperature Range

-40 to 85

°C

stg

Storage Temperature Ranges

-55 to 150

°C

Operative Junction Temperature

-40 to 150

°C

Symbol

Parameter

Value

Unit

thj-case

Thermal Resistance Junction to Case

1.7

°C/W

FGND

IRQ

VDD-LIN

HSD2

N.C.

HSD1

DRAINOUT

N.C.

GND

GATEIN

VSW

STCAP

VSPI

VSTBY

ADJ

SWGND

VDD-SW

D02AU1345A

DGND

GATEOUT

SYNC

STRAP

VLR

VIN

FBLR

RES

COMP

3/24

L5953

PIN FUNCTION

Pin Number

Pin Name

Function

FGND

Analog Ground

Input Voltage for LVW2

Input Voltage for LVW1

LVW2 Output

LVW1 Output

RES

Reset

Timing capacitor

SPI Serial Input

SPI Clock

SPI Serial Output

SPI Chip Select

DGND

SPI Ground

IRQ

Interrupt

HSD2

HSD2 Output

VDD-LIN

Battery

N.C.

Not Connected

HSD1

HSD1 Output

SWGND

Switching Ground

VDD-SW

PWM Battery

DRAINOUT

Drain of the exrternal MOS

N.C.

Not Connected

GND

Ground

VSW

Source of the external MOS

GATEIN

Gate of the internal MOS

GATEOUT

Switching Output for power mos gate

STRAP

Bootstrap

SYNC

Synchronization

VLR

REG2 Linear Voltage Regulator Output

VIN

REG2 Linear Voltage Regulator Input

FBLR

REG2 Linear Voltage Regulator Feedback

COMP

PWM Compensation

PWM Feedback

STCAP

ST-CAP

VSPI

Supply Voltage for SPI I/O

VSTBY

REG1 Stand-by Linear Voltage Regulator Output

ADJ

3.3V/5V REG1 Voltage Select

L5953

4/24

ELECTRICAL CHARACTERISTCS
( T

amb

= 25°C, V

= 14.4V)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Q,STBY

Quiescent current with regulators
and High-side drivers off

W1, W2, RES, IRQ, not active;
REG2, HSD1, HSD2, PWM off;
S, C, D fixed at high/low logic
level

100

Thermal Shutdown Junction
Temperature

150

°C

SMPS.PWM

amb

= 25°C, V

= 14.4V, V

= 5V; unless otherwise specified.)

o,min

Minimum Output Voltage

= 200mA

2.4

2.5

2.6

o,max

Maximum Output Voltage

= 200mA

9.6

10.4

Vref,PWM

Voltage Reference

1.275

Input Voltage Range

= 5V; I

= 0.5A

Line Regulation

= 0.5A

100

Load Regulation

= 5V; I

= 0.2A to 0.5A

Dropout Voltage between Pin 19
and Pin 23

= 0.5A, V

= 5V

0.5

= 1A, V

= 5V

Lim

Current Limit

1.5

Efficiency

f = 260kHz; I

= 0.5A

f = 400kHz; I

= 0.5A

90
86

%
%

SVR

Supply Voltage Ripple Rejection

= 1Vrms;

ripple

= 300Hz; I

= 0.4A

OSCILLATOR

Swiching frequency

249

260

271

kHz

Swiching frequency

384

400

416

kHz

Voltage Stability of Switching
Frequency

= 8 to 18V

Tbd

Temperature Stability of Switching
Frequency

= -40°C to 85°C

Tbd

SYNC

Low Input Voltage

0.8

High Input Voltage

Low Output Voltage

0.4

High Output Voltage

SOURCE

=1.5mA

---------

5/24

L5953

SLAVE

Slave Sink Current

100

Output Pulse Width

300

REG1 - 3.3V/5V STBY LINEAR VOLTAGE REGULATOR

STBY

Output Voltage

no load; ADJ pin = open
no load; ADJ pin = VSTBY pin

4.9

3.20

3.3

5.1
3.4

V
V

line

Line Regulation

no load; 7 < Vdd < 26V

load

Load Regulation

5mA < I

< 250mA

dropout

STCAP

- V

STBY

= 100mA, V

= 5V

= 100mA, V

= 3.3V

0.36
0.47

0.5

0.65

lim

Current Limit

Out short to GND

300

SVR

Supply Voltage Rejection

= 1Vrms: f = 300Hz

= 250mA

REG2 - LINEAR VOLTAGE REGULATOR 1.5V to 3.3V

Linear Regulator Output Voltage

no load; 4.75

16V;

1+ (R5/R6) = 2.588

3.2

3.3

3.4

no load; 3.135

16V;

1+ (R5/R6) = 1.176

1.45

1.5

1.55

Input Voltage

= 150mA

1.5V

3.135

= 300mA

1.5V

3.3V

4.75

load

Load Regulation

5mA

300mA

4.75V

16V; 1.5V

3.3V

line

Line Regulation

no load;
4.75V

16V; 1.5V

3.3V

ref,REG2

Voltage Reference

1.275

Lim

Current Limit

Out Short to ground

400

SVR

Supply Voltage Rejection

= 5Vdc, 0.5Vacpp, 300Hz

= 300mA; 1.5V

3.3V

= 3.3Vdc, 0.5Vacpp, 300Hz

= 150mA; 1.5V

HSD1

sat, peak

Saturation Voltage

= 0.5A

250

lim

Current Limit

600

load

Load Inductance

100

ELECTRICAL CHARACTERISTCS (continued)
( T

amb

= 25°C, V

= 14.4V)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L5953

6/24

DIAGNOSTIC PARAMETERS

HSD2

sat, peak

Saturation Voltage

= 0.2A

250

lim

Current Limit

300

load

Load Inductance

100

VOLTAGE WARNING

Sense Low Threshold

1.245

1.275

1.305

sth

Sense Threshold Hysteresis

Sense Output Low Voltage

= 1mA

0.4

Sense Output Leakage

= 5V; V

1.5V

Sense Input Current

=5V

RESET

Reset Threshold Voltage

0.95 x
V

STBY

RTH

Reset Threhold Hysteresis

0.02 x
V

STBY

Reset Output Voltage

= 1mA

0.4

Reset Output Leakage

= V

STBY

CTth

Delay Comparator Threshold

0.5 x

STBY

CThy

Delay Comparator Threshold
Hysteresys

180

CT1

Timing Capacitor Output Source
Current

7.5

CT2

Timing Capacitor Output Pull-
Down equivalent Resistor

150

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

HSD1W1 High Side Driver 1 Overcurrent

Warning activation

0.95

HSD1W2 High Side Driver 1 Open Load

Warning activation

HSD1 output voltage in test mode

HSD1W2

TEST

High Side Driver 1 V

Short

Warning activation in test mode

HSD1 in test mode
Measure V

VDD-LIN

-V

HSD1

1.5

HSD2W1 High Side Driver 2 Overcurrent

Warning activation

0.7

ELECTRICAL CHARACTERISTCS (continued)
( T

amb

= 25°C, V

= 14.4V)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

7/24

L5953

SPI INTERFACE

HSD2W2 High Side Driver 2 Open Load

Warning activation

HSD2 output voltage in test mode

HSD2W3 High Side Driver 2 V

Short

Warning activation in test mode

HSD2 in test mode
Measure V

VDD-LIN

-V

HSD1

1.5

THW

Thermal warning activation

145

°C

IRQ - Interrupt Request Pin

IRQ-L

IRQ Low voltage

= 1mA

0.4

IRQ-H

IRQ Leakage

irq

= 5V

Symbol

Alt

Parameter

Test Conditions

Min.

Max.

Unit

Recommended DC Operating Voltage

SPI

Supply Voltage for SPI I/O

5.5

Input Parameters (Tamb = 25°C, f = 1MHz)

Input Capacitance (D)

Input Capacitance (others pins)

LPF

Input Signal Pulse Width

DC Characteristics (T

amb

= -40 to 85°C, V

SPI

= 3V to 5.5V)

Input Leakage Current

Output Leakage Current

±2

Input Low Voltage

-0.3

0.3V

SPI

Input High Voltage

0.7V

SPI

Output Low Voltage

= 2mA

0.2V

SPI

Output High Voltage

= -2mA

0.8V

SPI

AC Characteristics (Tamb = -40 to 85°C, V

SPI

= 3V to 5.5V

SCLH

S Setup Time

CLSH

S Hold Time

Clock High Time

200

Clock Low Time

300

CLCH

Clock Rise Time

CHCL

Clock Fall Time

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

DLDH

Data In Rise Time

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L5953

8/24

Figure 1. AC Testing Input Output WaveformsI

Figure 2. SPI Clocking Scheme

DHDL

Data in Fall Time

SHSL

S Deselect Time

4.5V < V

SPI

< 5.5V

3V < V

SPI

< 4.5V

200
250

ns
ns

SHQZ

DIS

Output Disable Time

150

QVCL

Clock Low to Output Valid

250

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

Symbol

Alt

Parameter

Test Conditions

Min.

Max.

Unit

0.8V

SPY

0.2V

SPY

0.7V

SPY

0.3V

SPY

D03AU1479

(MODE 0: CPOL=0,CPHA=0)

(MODE 3: CPOL=1,CPHA=1)

MSB

D
Q

9/24

L5953

Figure 3. Output Timing

Figure 4. Serial Input Timing

FUNCTIONAL DESCRIPTION

REG1 Stand-by Regulator (Figure 5)

The stand-by regulator output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin:

- leaving the ADJ pin open, the output voltage is 5V;

- connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V.

This regulator is supplied by STCAP pin and provide the reset information.

It has a current protection which limits the maximum allowable output current.

Reset (Figure 6)

The RES pin is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in
regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time

AI01070B

MSB OUT

MSB-1 OUT

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

(CPOL=0, CPHA=0)

tQHQL

tCLQX

tQVCL

AI01071

MSB IN

tDVCH

HIGH IMPEDANCE

LSB IN

tSLCH

tCHDX

tDLDH
tDHDL

tCHCL

tCLCH

tCLSH

tSHSL

(CPOL=0, CPHA=0)

L5953

10/24

set up by the external capacitor CT.

When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero
only the REG1 and low Voltage Warnings are active.

Low Voltage Warning(Figure 7)

This circuit is able to sense two different voltages through external resistors to increase the overall flexibility.

If S1 pin voltage is higher than Vst, the output mos M1 is off: W1 is floating and can be pulled up by an external
resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to
zero. The same thing happens for S2 - W2.

The outputs W1 and W2 can be connected together to get a single output.

REG2 Linear Voltage Regulator (Figure 5)

REG2 is a linear voltage regulator with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V)
is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum
allowable output current.

High Side Drivers (Figure 8)

Two high-side driver with charge pump controlled by SPI are available inside L5953. They are protected against
short to ground: the short circuit potection limits the maximum output current.

A diagnostic procedure is available to detect open load, short to battery and overcurrent.

Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal
operationof the device. (see OPERATION -page 13

PWM Step Down Voltage Regulator (Figure 9)

The switching regulator inside the L5953 is a voltage control mode (also known as "direct duty cycle") Buck reg-
ulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the
power switch.

The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooh has a
fixed frequency and an amplitude variable with the battery voltage.

Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the
free-wheeling diode.

Error amplifier and compensation network

The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V
bandgap voltage) and whose inverting input and output are externally available for feedback and frequency
compensation.

13/24

L5953

SPI INTERFACE

Signals Description (Figure 10)

The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3.

Serial Output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the
falling edge of the serial clock.

Serial Input (D). The input pin is used to transfer data serially into the device. It receives instructions, address-
es, and data to be written. Input is latched on the rising edge of the serial clock.

Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data
present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after
the falling edge of the clock input.

Chip Select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the
S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is dese-
lected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After
power up, the chip is at the deselect state.

SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by
regulator VSTBY. The SPI is resetted by an internal signal whose buffered version is RES .

OPERATIONS

All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on
the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction
code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been
previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid in-
struction (one not contained in table 1) leaves the chip as previously selected.

Write Enable (WREN and Write Disable (WRDI)

The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN
instruction will set the latch and the WRDI istruction will reset the latch. The latch is reset under all the following
conditions:

Power on

WRDI instruction executed

As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and
enters a wait mode until it is deselected.

Table 1. Instruction Set.

Instruction

Description

Instruction Format

WREN

Set Write Enable Latch

00000110

WRDI

Reset Write Enable Latch

00000100

WSTA

Write Status Register

00000010

RDIA

Read Diagnostic Register

00000101

RSTA

Read Status Register

00000011

L5953

14/24

Table 2. Status Register.

Table 3. Status Register Description

Table 4. Diagnostic Register.

s15

s14

s13

s12

s11

s10

REG2 HSD1

HSD2

TBD

PWM
Freq.

PWM

TBD

Test

Mode

START

DIAG

s15

REG2 Linear Voltage
Regulator 1.5 to 3.3V

Regulator off

Regulator on

s14

High Side Driver 1

HSD1 off

HSD1 on

s13

High Side Driver 2

HSD2 off

HSD2 on

s12

TBD

s11

TBD

s10

PWM switching frequency

260kHz

400kHz

PWM Voltage Regulator

PWM1 off

PWM1 on

TBD

Test Mode

Test Mode off

Test Mode on
NOTE: in this case the bits s15 - s2 are internally
set to 0 (regulators and high side drivers are in off
condition)

Diagnostic

Diagnostic off

Starts the diagnostic procedure:
- in Test Mode if s1=1;
- during normal operation if s1=0
If s1=0 and s0=1, must be s14 = 1 (HSD1 ON)
and s13=1 (HSD2 ON)

Test mode

HSD1W1

HSD1W2

HSD1W3

HSD2W1

HSD2W2

HSD2W3

THW

15/24

L5953

Table 5. Diagnostic Register Description.

SUMMARY OF THE MAIN OPERATIONS

Operation A

Test Mode Diagnostic Procedure Start

1) WREN instruction (Fig.11)

2) WSTA instruction (Fig.12)

Operation B

Read the Diagnostic Register
Case1: after a Test Mode Diagnostic Procedure Start
1) RDIA instruction (Fig.13)
2) Diagnostic Register output (Fig.13)

NOTE: an operation B must follow an operation A. The delay between the end of the operations A to
the start of the operations B must be longer than 100

Operation C

Write the Status Register

Test mode

The Diagnostic Register is
referred to a test performed
during the normal working
of the L5953

The Diagnostic Register is
referred to a test performed
in Test mode

HSD1W1

If d7=0: HSD1 in normal
condition;
If d7=1: bit value
meaningless

If d7=0: HSD1 is in
overcurrent
If d7=1: bit value
meaningless

HSD1W2

If d7=0: bit value
meaningless;
If d7=1: HSD1 in normal
condition

If d7=0: bit value
meaningless
If d7=1: an open load is
present on HSD1

HSD1W3

If d7=0: bit value
meaningless;
If d7=1: HSD1 in normal
condition

If d7=0: bit value
meaningless
If d7=1: HSD1 is shorted to
the supply voltage VDD

HSD2W1

If d7=0: HSD1 in normal
condition;
If d7=1: bit value
meaningless

If d7=0: HSD2 is in
overcurrent;
If d7=1: bit value
meaningless

HSD2W2

If d7=0: bit value
meaningless
If d7=1: HSD2 in normal
condition

If d7=0: bit value
meaningless
If d7=1: an open load is
present on HSD2

HSD1W3

If d7=0: bit value
meaningless
If d7=1: HSD2 in normal
condition;

If d7=0: bit value
meaningless
If d7=1: HSD1 is shorted to
the supply voltage VDD

Thermal Warning

Normal condition

Overtemperature protection
activated(Tj>150°C)

L5953

16/24

1) WREN instruction (Fig.11)
2) WSTA instruction (Fig.16)

Operation D

Read the Status Register
1) RSTA instruction (Fig.17)
2) Status Register output (Fig.17)

Operation E

Diagnostic Procedure Start
1) WREN instruction (Fig.11)
2) WSTA instruction (Fig.14)

Operation F

Read the Diagnostic Register
Case 2: after a Diagnostic Procedure Start
1) RDIA instruction (Fig.15)
2) Diagnostic Register output (Fig.15)
An operation F must follow an operation E if the pin IRQ is not activated.
The delay between the Operation E and an Operation F must be longer than 100

To be recognized, the fault must be present without interruptions during all the delay above mentionned .
After an Operation F, the bit s0 of the Status Register is resettled (0)

Operation G

Write operation disabled
1) WRDI instruction (Table 1)

Operation H

Read the Diagnostic Register case 3: after an IRQ pin activation
1) RDIA instruction (Fig. 15)
2) Diagnostic Register Output (Fig. 15)
The delay between the IRQ activation and an Operation F must be longer than 100

Figure 11. Write Enable Latch Sequence

HIGH IMPEDANCE

CPOL=0

CPHA=0

D03AU1483

17/24

L5953

Figure 12. Test Mode Diagnostic Procedure Start (after a Write Enable Latch Sequence, Fig.11)

Figure 13. Read the Diagnostic registerCase1: after a Test Mode diagnostic procedure start (Fig.
12)

Figure 14. Diagnostic Procedure Start (after a Write Enable Latch Sequence, operation A)

Figure 15. Read the Diagnostic RegisterCase2: during the normal working of the L5953 (after a

Diagnostic Procedure Start, Fig.14)

HIGH IMPEDANCE

INSTRUCTION

STATUS REGISTER

s15

s14

s13

s12

s11

s10

D03AU1484

CPOL=0, CPHA=0

HIGH IMPEDANCE

INSTRUCTION

DIAGNOSTIC REGISTER OUT

D03AU1485

CPOL=0, CPHA=0

HIGH IMPEDANCE

INSTRUCTION

STATUS REGISTER

s15

s14

s13

s12

s11

s10

D03AU1486

CPOL=0, CPHA=0

HIGH IMPEDANCE

INSTRUCTION

DIAGNOSTIC REGISTER OUT

D03AU1487

CPOL=0, CPHA=0

L5953

18/24

Figure 16. Write the Status Register (after a Write Enable Latch Sequence, operation A)

Figure 17. Read the Status Register

IRQ - Interrupt Request Pin

It is an open drain pin activated (low) every time a variation occurs in the Diagnostic Register.

Purpose: to alert the

P that one or more warning bit of the Diagnostic Register has changed from 0 to

1 or from 1 to 0.

An activation of this pin puts the bit s0 of the Status Register to 1 (START DIAGNOSTIC) like an
Operation E (Diagnostic Procedure Start). Then an Operation F has to be executed without an
Operation E before.

After an Operation F, the IRQ pin is disactivated, and goes to 1 if connected to a pull-up resistor.

L5953 - Application Note

HIGH IMPEDANCE

INSTRUCTION

STATUS REGISTER

s15

s14

s13

s12

s11

s10

D03AU1488

CPOL=0, CPHA=0

HIGH IMPEDANCE

INSTRUCTION

STATUS REGISTER OUT

D03AU1489

s15

s14

s13

s12

s11

s10

CPOL=0, CPHA=0

19/24

L5953

Figure 18. Block and Application Diagram

Figure 19. Block Diagram And Application With External Power MOS

VOLTAGE WARNING

SPI INTERFACE

REG2

LINEAR VOLTAGE

REGULATOR

1.5-3.3V/300mA

HSD1

HSD2

COMP

GATEOUT

GATEIN

VSW

DRAINOUT

STRAP

ADJ

VSTBY

GND

SWGND

VDD

VDD-LIN

REG1

ST-BY LINEAR VOLTAGE

REGULATOR

3.3-5V/250mA

PWM

STEP DOWN
REGULATOR

2.5-10V/1A

OSCILLATOR &

SYNC

STCAP

RES

VDD-SW

IRQ

VLR

FBLR

VIN

SYNC

DGND

FGND

D01AU1331B

C11

C10

VSPI

VOLTAGE WARNING

SPI INTERFACE

REG2

LINEAR VOLTAGE

REGULATOR

1.5-3.3V/300mA

HSD1

HSD2

COMP

GATEOUT

GATEIN

VSW

DRAINOUT

STRAP

ADJ

VSTBY

GND

SWGND

VDD

VDD-LIN

REG1

ST-BY LINEAR VOLTAGE

REGULATOR

3.3-5V/250mA

PWM

STEP DOWN
REGULATOR

2.5-10V/1A

OSCILLATOR &

SYNC

STCAP

RES

VDD-SW

IRQ

VLR

FBLR

VIN

SYNC

DGND

FGND

D01AU1332B

C10

VSPI

L5953

20/24

PART LIST on Evaluation Board

REG1 OUTPUT VOLTAGE
V

STBY

= 5V if pin ADJ left floating

STBY

= 3.3V if pin ADJ is conneted to the pin V

STBY

Timing Capacitor
The value for this capacitor has to be chosen according the wanted power-on delay T

where I

CT1

is the source current used to charge the timing capacitor and V

STBY

is the REG1 output voltage.

Feedback resistors for REG2

where VLR is the required output voltage for REG2.

External components for PWM regulator

Bootstrap capacitor
The suggested value for the bootstrap capacitor is C6 = 100nF

Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output
filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck
regulator working in Continuos mode. Continuous mode operation is recommended in order to reduce the stress
of the output capacitor and of the free-wheeling diode.

Inductor Selection
The minimum value of the inductor L7 has to be so that the maximum inductor current ripple

L,max

is 20% to

30% of the maximum load current load I

o,max

.The maximum ripple is present when the switching frequency is

minimum ( f

sw,min

) and the input voltage is maximum ( V

in,max

) so the minimum value for the inductor L

min

is :

Output Capacitor Selection
The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple
on the output voltage is due to a capacitive contribute, often negligible, equal to

C1 = 470

C2 = 220 nF

C3 = 470

C4 = 10

C5 = 1

C6 = 100 nF

C7 = 470

ESR=65 m

C8 = 56nF

C9 = 2.7 nF

C10 = 10

C11 = 4.7 nF

R1 = 2.2 k

R2 = 2 x 1.5 k

in parallel

R3 = 10 k

R4 = 220 k

R5 = 3.3 k

R6 = 1 k

L1 = 180

D1 = 1N4007 or

MBR160

D2 = MBR360

C11

CT 1

0.5 V

S TB Y

(

)

C TL Ry

--------------------------------------------------------------

r ef R EG 2

--------------------------

m in

L m ax

--------------------

i m ax

-----------------

s w m in

------------------

21/24

L5953

and a resistive contribute given by the ESR of the capacitor and which is equal to

VC fixes the value for C7 while

VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that

the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If V

ripple

is the maximum

allowed voltage ripple on Vo then it should result:

More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behav-
iour of the output voltage in case of large load variations.

Free-wheeling diode
The diode must withstand an average current Id equal to Id = I

lim

( 1- D

min

)

where I

lim

is the current of intervention of the short circuit protection and D

min

is the minimum duty cycle. As D

min

is vey low, the current Id can be assumed equal to I

lim

Compensation Network
In continuous mode, the voltage controlled buck converter showes two poles due to the output LC filter and one
zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and
two poles:

the zeros compensate the double poles of the LC filter
one pole compensates the zero due to ESR of the output capacitor
the second pole is nominally located in the origin which means an infinite gain at frequency null. In

the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open
loop gain and the pole is located at very low frequency.

The values for the components of the compensation network can be fixed when the inductor L1 and the output
capacitor C7 are chosen.

The necessary steps are following:

1.fix the cross-over frequency f

of the overall loop gain.

Usually

where f

sw,min

is the minimum switching frequency

2.Calculate the high frequency error amplifier gain

3.Chose R3 and calculate

The value for R3 has not to be very high (for example 10K

) so to limit the error due to an error amplifier input

offset current.

L m ax

8 C7 f

s w m in

---------------------------------------

ESR

L m a x

ri ppl e

ES R

0.1 f

s w,min

0.25 f

ESR

-------------

L1 C7

-----------------------

23/24

L5953

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

3.60

0.141

0.10

0.30

0.004

0.012

3.30

0.130

0.10

0.004

0.22

0.38

0.008

0.015

0.23

0.32

0.009

0.012

D (1)

15.80

16.00

0.622

0.630

9.40

9.80

0.370

0.385

13.90

14.50

0.547

0.570

0.65

0.0256

11.05

0.435

E1 (1)

10.90

11.10

0.429

0.437

2.90

0.114

5.80

6.20

0.228

0.244

2.90

3.20

0.114

0.126

0.10

0.004

15.50

15.90

0.610

0.626

1.10

0.043

0.80

1.10

0.031

0.043

(max.)

(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".

PowerSO36

PSO36MEC

DETAIL A

h x 45°

DETAIL A

lead

slug

Gage Plane

0.35

DETAIL B

(COPLANARITY)

- C -

SEATING PLANE

0.12

A B

BOTTOM VIEW

OUTLINE AND

MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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24/24

L5953

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L5953

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