DYNAMIC DAC DETECTION ON CHIP
PROGRAMMABLE OUTPUT FROM 0.925V

TO 2.0V WITH 0.05V AND 0.025V BINARY
STEPS

ULTRA HIGH EFFICIENCY
SEPARATE 5V BIAS SUPPLY AVAILABLE

FOR HIGH EFFICIENCY PERFORMANCE

EXCELLENT

OUTPUT

ACCURACY

OVER LINE, LOAD AND TEMPERATURE
VARIATIONS

HIGH PRECISION INTERNAL REFERENCE

DIGITALLY TRIMMED

OPERATING SUPPLY

VOLTAGE FROM

4.75V TO 25V

VERY FAST LOAD TRANSIENT
REMOTE SENSING INPUTS
INTERNAL

LINEAR

REGULATOR

2.5V

/150mA,

2% PRECISION

POWER MANAGEMENT

- PROGRAMMABLE POWER-UP TIME
- POWER GOOD OUTPUT, SKIP MODE
- OUTPUT OVERVOLTAGE PROTECTION
- OUTPUT UNDERVOLTAGE LOCKOUT

OPERATING FREQUENCY UP TO 1MHz
MEETS INTEL MOBILE PENTIU

III

Application

ADVANCED MICROPROCESSOR SUPPLIES
POWER SUPPLYFOR PENTIUM

III INTEL MO-

BILE

DESCRIPTION

The L5996 is a power supply controller that offers
a complete power management for

notebook

CPUs of the next generation especially for mobile
Pentium III. A high precise 5 bit digital to analog
converter (DAC) allows to adjust the output volt-
age from 0.925V to 2.0V. Dynamic DAC code
changes are detected on chip in order to switch
the output voltage between 1.3V and 1.45V in
less tahn 100

s.The high precision internal refer-

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

July 1999

FREQ SETTING

SYNC

POWER

MANAGEMENT

& SYSTEM

SUPERVISOR

4.75V

25V

POWER

SECTION

L5996

POWER GOOD

PWM SECTIONS

DAC

NOSKIP

ENABLE

CPU CORE

2.5V LIN. REG.

3.3V

2.5V

CPU CLK

0.925V to 2.0V

Pentium

III

Mobile

D98IN997A

TYPICAL APPLICATION CIRCUIT

TQFP32

(7mm x 7mm)

L5996

5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU

PRELIMINARY DATA

1/9

ence, digitally trimmed, assures the selected out-
put voltage to within +/-1% over temperature and
battery voltage variations.
Thanks to the remote sensing inputs and to the
window comparator system, embedded in the er-
ror summing structure, the device provides excel-
lent load transient performance. The high peak
current gate drive affords to have fast switching
to the external power mos, performing an high ef-
ficiency. A complete power management include
on board a programmable power-up sequencing,
power good signal, skip mode operation and un-
dervoltege detection. The L5996 assures a fast
protection against load overvoltage and load
overcurrent. Linear regulator on-board is avail-
able with an output voltage of 2.5V (+/-2%) and a
current capability of

150mA, useful for CPU

CLOCK BUS.

11 12 13 14 15 16

29 28 27 26 25

SSTART

DISPROT

V5SW

VIN

ENABLE

REG5

LRSNS

HRSNS

VFB

VPROG

COMP

SNSGND

IN2.5

O2.5

VBG

VSS

POWERGOOD

RGATE

PWRGND

RSTRAP

HSTRAP

HGATE

HSRC

NOSKIP

ICURLIM

OSC

FREQ

VID4

VID3

VID2

VID0

VID1

D98IN998

PIN CONNECTION

LRSNS

HRSNS

COMP

HSTRAP

HGATE

HSRC

Cboot

Rsense

VIN

RGATE

PWRGND

Load

Hside

Lside

CONTROL

LOGIC

OVER CURRENT

COMPARATOR

ZERO CROSSING

COMPARATOR

PULSE SKIPPING

COMPARATOR

SOFT

START

HRSNS

LRSNS

CSOFT

SSTART

O2.5

IN2.5

VBG

VPROG

DISPROT

ENABLE

OSC

FREQ

OSCILLATOR

and

SYNC

OVER/UNDER VOLTAGE

COMPARATOR

PWGOOD

NOSKIP

LINEAR

REGULATOR

POWER

MANAGEMENT

D98IN999

RSTRAP

SNSGND

VFB

VSS

PROGRAMMABLE

BANDGAP &

REFERENCE

VID0

VID1

VID2

VID3

INTERNAL SUPPLY

REG5

V5SW

2.5V

LIN.

REG.

ICURLIM

VPROG

VIN

Vdc

5.5V to 25V

REG5

SLOPE

ERROR

SUMMING

VPROG

WINDOW

COMP

IN3.3V

VCPUCLK

VID4

BLOCK DIAGRAM

DESCRIPTION (Continued)

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

VIN to PWRGND

-0.5 to 27

PWRGND to VSS

0.5

VREFS to PWRGND

HSTRAP, HGATE to PWRGND

-0.5V to VIN+14V

RSTRAP, RGATE to PWRGND

-0.5V to 14V

EABLE, FREQ, OSC, COMP, VFB, HRSNS, LRSNS

VID0-3, NOSKIP

Junction Temperature Range

-40 to 150

stg

Storage Temperature Range

-55 to 150

L5996

2/9

ELECTRICAL CHARACTERISTICS ( V

= 12V; T

= 25

C, OSC = GND, unless otherwise specified)

= specifications referred to T

from 0 to 70

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DC CHARACTERISTICS

Input Supply Voltage

4.75

Operating Quiescent Current

RGATE = HGATE = OPEN
ENABLE = REG5

0.9

1.1

Stand-By Current

ENABLE = GND
VIN = 12V
V

= 25V

100

150
180

INTERNAL REGULATOR (VREG5)

REG5

Output Voltage

= 7.5V to 25V

LOAD

= 0 to 5mA,

REG5

= 4.7

4.9

5.0

5.1

REG5

Total Current Capability

CREG5 = 4.7

= 5.5V

mA
mA

Switch-Over Threshold Voltage

4.3

4.5

4.7

Current Capability
(internal switch on)

5SW

= 4.5 to 5.5V

REG5

4.4V

2.5V REFERENCE VOLTAGE

O 2.5

Regulated Voltage

IN 2.5

= 3.3V

VO 2.5

= 47

O 2.5

= 10mA

2.45

2.5

2.55

Regulation over Line and Load 6V < V

< 25V

IN 2.5

= 3.3V

O 2.5

= 0-150mA

2.425

2.5

2.575

VO 2.5 MAX

Current Limit

IN 2.5

= 3.3V

500

PROGRAMMABLE REFERENCE VOLTAGE AND VBG

PROG

Accuracy

ID0

, V

ID1

, V

ID2

, V

ID3

, V

ID4

see Table 1.

-0.5%

PROG

+0.5%

Ouput Voltage Accuracy

Line and Load Regulation
included, V

ID0

, V

ID1

, V

ID2

, V

ID3

ID4

, see Table 1.

-1%

PROG

+1%

Band Gap reference

VBG

= 220nF

1.240

1.246

1.252

POWER MANAGEMENT

Enable Voltage

HIGH LEVEL

2.4

Disable Voltage

LOW LEVEL

0.8

Power Good Saturation
Voltage

sink

= 400

0.4

NOSKIP Mode (Active high)

High Level
Low Level

2.4

0.8

V
V

Output UVLO Threshold

OVP = GND

Output UVLO Lockout Time

Depending on C

value

775

ms/

THERMAL DATA

Symbol

Parameter

Value

Unit

Th j-amb

Thermal Resistance Junction to Ambient

C/W

L5996

3/9

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

PROTECTION FUNCTIONS

-V

Over-Current Threshold
Voltage

SSTART

= 3.1V

Pulse Skipping Mode
Threshold Voltage

NOSKIP = HIGH

Zero Crossing Threshold

-4

Under-Voltage Threshold

Vprog

-13%

Vprog

-10%

Vprog

-7%

Upper Over-Voltage Threshold

Vprog

+7%

Vprog

+10%

Vprog
+13%

Lower Over-Voltage Threshold

Vprog

-4.5%

Over-Voltage Propagation
Time

1.5

Under-Voltage Propagation
Time

1.5

SOFT START

Soft start source current

3.2

4.8

Soft start clamp voltage

3.1

OSCILLATOR AND SYNC

osc

Fixed frequency

OSC =0V; FREQ = REG5

225

250

275

KHz

OSC = REG5 FREQ = REG5

180

200

220

KHz

SINK MIN

Minimum Synchronizzable
external frequency

FREQ = REG5
OSC = EXTERNAL SIGNAL

120

KHz

Sync pulse width

Rising edge mode

200

Sync pulse amplitude

5.5

fosc

Operating switching frequency Rext connected between

FREQ and GND, OSC
connect to REG5 or GND
Rext = 680k

Rext = 40k

100

kHz

MHz

HIGH AND LOW SIDE GATE DRIVERS

OH5

Output high source peak
current

HSTRAP = RSTRAP = REG5

550

Output high sink impedance

test

= 100mA,

HSTRAP = RSTRAP = REG5

3.5

OH12

Output high source peak
current

HSTRAP = RSTRAP = 12V

H12

Output high sink impedance

test

= 100mA,

HSTRAP - RSTRAP = 12V

OL5

Output low peak current

HSTRAP = RSTRAP = 5V

500

Output low impedance

Itest = 100mA,
HSTRAP = RSTRAP = 5V

OL12

Output low peak current

HSTRAP = RSTRAP = 12V

L12

Output low Impedance

test

= 100mA,

HSTRAP = RSTRAP = 12V

Dead Time

GATE low to high

ELECTRICAL CHARACTERISTICS (continued)

L5996

4/9

FUNCTIONAL PIN DESCRIPTION

ENABLE(pin1): Enable input. A

high level

(>2.4V) enables the device, a low level (<0.8V)
shuts it down. As ENABLE drops below 0.8V, the
drivers are turned off and all internal functions are
disabled except REG5. In this condition the stand
by current is less than 80

A at VIN = 12V.

VIN(pin2): Device supply voltage. Input voltage
range at this pin is 4.75V to 25V and the operat-
ing current requirement at 12V is 650

REG5(pin3): 5V Regulator supply. Used also to
supply the bootstrap capacitor. A minimum 2.2

ceramic capacitor connected to PWRGND is re-
quired.

V5SW(pin4): 5V supply line. Connecting to 5V
bus(4.75V to 5.5V) the device is no longer pow-
ered by VIN but by this pin and the internal linear
regulator is disconnected increasing the effi-
ciency.

DISPROT (pin5) Disable Protection Functions. A
high level (3.3V CMOS LOGIC) on this pin dis-
ables the undervoltage and the overvoltage pro-
tection. Tie this pin to V

for normal operation.

SSTART(pin6): Soft Start. The soft-start time is
programmed by an external capacitor connected
between this pin and SGND. The internal current
generator forces 4

A through the capacitor imple-

menting the soft start function.

HRSNS(pin7): Error summing current sense non
inverting input.

LRSNS(pin8): Error summing current sense in-
verting input.

VFB(pin9): Regulator voltage feedback input.
Connect close to the CPU input supply pin realise
an accurate voltage regulation. VFB internally is
connected to the window comparator that is used
to increase the performance during the load tran-
sient.

COMP(pin10): Regulator stability compensation
pin. The compensation is realised internally and
normally it is not necessary to connect any exter-
nal components to this pin.

VPROG(pin11): Reference voltage test pin. This
pin provides the DAC output and should be de-
coupled to ground using a 0.22

F ceramic ca-

pacitor. No load has to be connected.

SNSGND(pin12): Remote ground sense. This
pin is internally connected to the low power cir-
cuitry and for a precise output voltage regulation
can be connected to the output capacitor nega-
tive terminal.

IN2.5

(pin13): 2.5V linear supply voltage. Is avail-

able on-chip a linear regulator useful for the 2.5V
bus. A max input voltage of 3.3V is recom-
mended at Iomax (150mA).

O2.5

(pin14): 2.5V linear regulator output. The

linear regulator is realised with an internal NPN
transistor

with +/-2% output accuracy. A mini-

mum

capacitor connected versus

PWRGND is required.

VBG(pin15): Band-gap reference voltage. A min
220nF ceramic capacitor is required to assure the
band gap stability and noise immunity.

VSS(pin16): Signal ground. This pin could be
connected to the PWRGND pin.

FREQ(pin17): Connecting an external resistor
versus ground is possible to select the switching
frequency between 100kHz and 1MHz. Using an
Rext=680k the fsw is 100kHz, using an Rext =
40k the fsw is 1MHz. In this condition is recom-
mended to connect the OSC pin to REG5 or to
VSS.

OSC(pin18): Connecting to REG5 is able to set
the switching frequency at 200kHz, connecting to
VSS is able to set the switching frequency at
250kHz. An external pulsed signal, with an ampli-
tude higher than 2.4V, could synchronise the de-
vice. In all these conditions pin FREQ has to be
connected to REG5.

OVP/CURLIM(pin19): Over voltage protection
and reduced current limit window. If the output
voltage reaches the 10% above the programmed
voltage (VPROG) this pin is driven low the high
side driver is turned off and the low, side driver is
turned on. All the internal blocks are active. The
device uses OVP function to discharge the output
during HIGH_TO_LOW core voltage transition.
The pin is driven low also during LOW_TO_HIGH
core voltage transition. The pin will stay low as

L5996

5/9

long as the current limit value is reduced with re-
spect to the normal operating value. This is done
to limit voltage overshoots during core voltage
changes. Making this signal externally available
simplifies system debugging.

VID0-4(pin20-24): Voltage Identification code in-
put. These open collector compatible inputs are
used to program the output voltage as specified
in Table 1. Every pin has an internal pull up. If all
four pins are high or floating, the output voltage
and the 2.5V regulator are suspended and the
POWERGOOD is low.

NOSKIP(pin25): Pulse skipping mode control. A
high level (>2.4V) disables pulse skipping in low
load condition, a low level (>0.8V) enables it.

HSRC(pin26):

High

side

N-Channel

switch

source connection. This pin provides the return
path for the high side driver.

HGATE(pin27): Gate driver output, high side N-
Channel switch. The driver internal impedance is
about 4

at VIN=12V.

HSTRAP(pin28):Bootstrap capacitor pin. This pin

provide to supply the high side driver sinking the
current by the bootstrap capacitor.

RSTRAP(pin29):

Synchronous rectifier

gate

driver supply voltage. This pin could be con-
nected to REG5 to reduce the switching losses
due to the external Mosfets gate capacitance.
This is useful to maintain an high efficiency at
light load.

RGATE(pin30): Gate driver output, low side N-
Channel switch. The driver internal impedance is
about 3

at VIN=12V.

PWRGND(pin31): Power ground. This pin has to
be connected closely

to the low side mosfet

source in order to reduce the noise injected into
the IC.

POWER GOOD(pin32): Open drain power good
output. This pin is pulled low if the output voltage
is not within

10% and the 2.5V output is lower

than 2.175V (-13%). The pin is pulled low also if
REG5, VPROG and VBG have not reached the
expected values. This test could be useful in an
assembling fault condition.

Table 1. VID [4:0] AND corresponding +VCC_CPU_CORE ranges

VID[4:0]

+VCC_CPU_CORE

VID[4:0]

+VCC_CPU_CORE

00000

2.00V

10000

1.275V

00001

1.95V

10001

1.250V

00010

1.90V

10010

1.225V

00011

1.85V

10011

1.200V

00100

1.80V

10100

1.175V

00101

1.75V

10101

1.150V

00110

1.70V

10110

1.125V

00111

1.65V

10111

1.100V

01000

1.60V

11000

1.075V

01001

1.55V

11001

1.050V

01010

1.50V

11010

1.025V

01011

1.45V

11011

1.000V

01100

1.40V

11100

0.975V

01101

1.35V

11101

0.950V

01110

1.30V

11110

0.925V

01111

No CPU

11111

No CPU

L5996

6/9

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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L5996

9/9

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