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Электронный компонент: L6206

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1/23
L6206
September 2003
s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
s
5.6A OUTPUT PEAK CURRENT (2.8A DC)
s
R
DS(ON)
0.3
TYP. VALUE @ T
j
= 25 C
s
OPERATING FREQUENCY UP TO 100KHz
s
PROGRAMMABLE HIGH SIDE OVERCURRENT
DETECTION AND PROTECTION
s
DIAGNOSTIC OUTPUT
s
PARALLELED OPERATION
s
CROSS CONDUCTION PROTECTION
s
THERMAL SHUTDOWN
s
UNDER VOLTAGE LOCKOUT
s
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
s
BIPOLAR STEPPER MOTOR
s
DUAL OR QUAD DC MOTOR
DESCRIPTION
The L6206 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L6206 features thermal shutdown and a non-dissipa-
tive overcurrent detection on the high side Power
MOSFETs plus a diagnostic output that can be easily
used to implement the overcurrent protection.
BLOCK DIAGRAM
D99IN1088A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V
10V
BRIDGE A
BRIDGE B
SENSE
B
PROGCL
B
OCD
B
OCD
A
PROGCL
A
OCD
A
OCD
B
ORDERING NUMBERS:
L6206N (PowerDIP24)
L6206PD (PowerSO36)
L6206D (SO24)
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
DMOS DUAL FULL BRIDGE DRIVER
L6206
2/23
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Test conditions
Value
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
60
V
V
OD
Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
= 60V;
V
SENSEA
= V
SENSEB
= GND
60
V
OCD
A
,OCD
B
OCD pins Voltage Range
-0.3 to +10
V
PROGCL
A
,
PROGCL
B
PROGCL pins Voltage Range
-0.3 to +7
V
V
BOOT
Bootstrap Peak Voltage
V
SA
= V
SB
= V
S
V
S
+ 10
V
V
IN
,V
EN
Input and Enable Voltage Range
-0.3 to +7
V
V
SENSEA,
V
SENSEB
Voltage Range at pins SENSE
A
and SENSE
B
-1 to +4
V
I
S(peak)
Pulsed Supply Current (for each
V
S
pin), internally limited by the
overcurrent protection
V
SA
= V
SB
= V
S
;
t
PULSE
< 1ms
7.1
A
I
S
RMS Supply Current (for each
V
S
pin)
V
SA
= V
SB
= V
S
2.8
A
T
stg
, T
OP
Storage and Operating
Temperature Range
-40 to 150
C
Symbol
Parameter
Test Conditions
MIN
MAX
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
8
52
V
V
OD
Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
52
V
V
SENSEA,
V
SENSEB
Voltage Range at pins SENSE
A
and SENSE
B
(pulsed t
W
< t
rr
)
(DC)
-6
-1
6
1
V
V
I
OUT
RMS Output Current
2.8
A
T
j
Operating Junction Temperature
-25
+125
C
f
sw
Switching Frequency
100
KHz
3/23
L6206
THERMAL DATA
PIN CONNECTIONS (Top View)
(5) The slug is internally connected to pins 1,18,19 and 36 (GND pins).
Symbol
Description
PowerDIP24
SO24
PowerSO36
Unit
R
th-j-pins
MaximumThermal Resistance Junction-Pins
18
14
-
C/W
R
th-j-case
Maximum Thermal Resistance Junction-Case
-
-
1
C/W
R
th-j-amb1
MaximumThermal Resistance Junction-Ambient
1
(1)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm
2
(with a thickness of 35 m).
43
51
-
C/W
R
th-j-amb1
Maximum Thermal Resistance Junction-Ambient
2
(2)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 m).
-
-
35
C/W
R
th-j-amb1
MaximumThermal Resistance Junction-Ambient
3
(3)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 m), 16 via holes
and a ground layer.
-
-
15
C/W
R
th-j-amb2
Maximum Thermal Resistance Junction-Ambient
4
(4)
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
58
77
62
C/W
PowerDIP24/SO24
PowerSO36
(5)
GND
GND
OUT1
B
OCD
B
SENSE
B
IN2
B
IN1
B
1
3
2
4
5
6
7
8
9
PROGCL
B
VBOOT
EN
B
OUT2
B
VS
B
GND
GND
19
18
17
16
15
13
14
D99IN1089A
10
11
12
24
23
22
21
20
IN1
A
IN2
A
SENSE
A
OCD
A
OUT1
A
VS
A
OUT2
A
VCP
EN
A
PROGCL
A
GND
N.C.
N.C.
VS
A
OCD
A
OUT1
A
N.C.
N.C.
N.C.
N.C.
N.C.
OUT1
B
OCD
B
N.C.
VS
B
N.C.
N.C.
GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
GND
GND
D99IN1090A
IN1
A
SENSE
A
IN2
A
SENSE
B
IN2
B
IN1
B
9
8
7
28
29
30
PROGCL
A
PROGCL
B
10
27
OUT2
A
EN
A
VCP
EN
B
OUT2
B
VBOOT
14
12
11
23
25
26
N.C.
N.C.
13
24
L6206
4/23
PIN DESCRIPTION
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
1
10
IN1
A
Logic input
Bridge A Logic Input 1.
2
11
IN2
A
Logic input
Bridge A Logic Input 2.
3
12
SENSE
A
Power Supply
Bridge A Source Pin. This pin must be connected to Power
Ground directly or through a sensing power resistor.
4
13
OCD
A
Open Drain
Output
Bridge A Overcurrent Detection and thermal protection pin.
An internal open drain transistor pulls to GND when
overcurrent on bridge A is detected or in case of thermal
protection.
5
15
OUT1
A
Power Output
Bridge A Output 1.
6, 7,
18, 19
1, 18,
19, 36
GND
GND
Signal Ground terminals. In Power DIP and SO packages,
these pins are also used for heat dissipation toward the
PCB.
8
22
OUT1
B
Power Output
Bridge B Output 1.
9
24
OCD
B
Open Drain
Output
Bridge B Overcurrent Detection and thermal protection pin.
An internal open drain transistor pulls to GND when
overcurrent on bridge B is detected or in case of thermal
protection.
10
25
SENSE
B
Power Supply
Bridge B Source Pin. This pin must be connected to Power
Ground directly or through a sensing power resistor.
11
26
IN1
B
Logic Input
Bridge B Input 1
12
27
IN2
B
Logic Input
Bridge B Input 2
13
28
PROGCL
B
R Pin
Bridge B Overcurrent Level Programming. A resistor
connected between this pin and Ground sets the
programmable current limiting value for the bridge B. By
connecting this pin to Ground the maximum current is set.
This pin cannot be left non-connected.
14
29
EN
B
Logic Input
Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B.
If not used, it has to be connected to +5V.
15
30
VBOOT
Supply
Voltage
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16
32
OUT2
B
Power Output
Bridge B Output 2.
17
33
VS
B
Power Supply
Bridge B Power Supply Voltage. It must be connected to
the supply voltage together with pin VS
A
.
20
4
VS
A
Power Supply
Bridge A Power Supply Voltage. It must be connected to
the supply voltage together with pin VS
B
.
21
5
OUT2
A
Power Output
Bridge A Output 2.
5/23
L6206
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
22
7
VCP
Output
Charge Pump Oscillator Output.
23
8
EN
A
Logic Input
Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A.
If not used, it has to be connected to +5V.
24
9
PROGCL
A
R Pin
Bridge A Overcurrent Level Programming. A resistor
connected between this pin and Ground sets the
programmable current limiting value for the bridge A. By
connecting this pin to Ground the maximum current is set.
This pin cannot be left non-connected.
ELECTRICAL CHARACTERISTICS
(T
amb
= 25 C, V
s
= 48V, unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
V
Sth(ON)
Turn-on Threshold
6.6
7
7.4
V
V
Sth(OFF)
Turn-off Threshold
5.6
6
6.4
V
I
S
Quiescent Supply Current
All Bridges OFF;
T
j
= -25C to 125C
(6)
5
10
mA
T
j(OFF)
Thermal Shutdown Temperature
165
C
Output DMOS Transistors
R
DS(ON)
High-Side Switch ON Resistance T
j
= 25
C
0.34
0.4
T
j
=125
C
(6)
0.53
0.59
Low-Side Switch ON Resistance
T
j
= 25
C
0.28
0.34
T
j
=125
C
(6)
0.47
0.53
I
DSS
Leakage Current
EN = Low; OUT = V
S
2
mA
EN = Low; OUT = GND
-0.15
mA
Source Drain Diodes
V
SD
Forward ON Voltage
I
SD
= 2.8A, EN = LOW
1.15
1.3
V
t
rr
Reverse Recovery Time
I
f
= 2.8A
300
ns
t
fr
Forward Recovery Time
200
ns
Logic Input
V
IL
Low level logic input voltage
-0.3
0.8
V
V
IH
High level logic input voltage
2
7
V
I
IL
Low Level Logic Input Current
GND Logic Input Voltage
-10
A
PIN DESCRIPTION (continued)
L6206
6/23
(6)
Tested at 25C in a restricted range and guaranteed by characterization.
(7)
See Fig. 1.
(8)
See Fig. 2.
I
IH
High Level Logic Input Current
7V Logic Input Voltage
10
A
V
th(ON)
Turn-on Input Threshold
1.8
2.0
V
V
th(OFF)
Turn-off Input Threshold
0.8
1.3
V
V
th(HYS)
Input Threshold Hysteresis
0.25
0.5
V
Switching Characteristics
t
D(on)EN
Enable to out turn ON delay time
(7)
I
LOAD
=2.8A, Resistive Load
100
250
400
ns
t
D(on)IN
Input to out turn ON delay time
I
LOAD
=2.8A, Resistive Load
(dead time included)
1.6
s
t
RISE
Output rise time
(7)
I
LOAD
=2.8A, Resistive Load
40
250
ns
t
D(off)EN
Enable to out turn OFF delay time
(7)
I
LOAD
=2.8A, Resistive Load
300
550
800
ns
t
D(off)IN
Input to out turn OFF delay time
I
LOAD
=2.8A, Resistive Load
600
ns
t
FALL
Output Fall Time
(7)
I
LOAD
=2.8A, Resistive Load
40
250
ns
t
dt
Dead Time Protection
0.5
1
s
f
CP
Charge pump frequency
-25C<T
j
<125C
0.6
1
MHz
Over Current Detection
I
s over
Input Supply Over Current
DetectionThreshold
-25C<T
j
<125
C; RCL= 39 k
-25C<T
j
<125
C; RCL= 5 k
-25C<T
j
<125
C; RCL= GND
-10%
-10%
-30%
0.57
4.42
5.6
+10%
+10%
+30%
A
A
A
R
OPDR
Open Drain ON Resistance
I = 4mA
40
60
t
OCD(ON)
OCD Turn-on Delay Time (8)
I = 4mA; C
EN
< 100pF
200
ns
t
OCD(OFF)
OCD Turn-off Delay Time (8)
I = 4mA; C
EN
< 100pF
100
ns
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25 C, V
s
= 48V, unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
7/23
L6206
Figure 1. Switching Characteristic Definition
Figure 2. Overcurrent Detection Timing Definition
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
OCD
Threshold
90%
10%
I
OUT
V
OCD
t
t
t
OCD(OFF)
t
OCD(ON)
D01IN1222
L6206
8/23
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6206 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.3ohm (typical value @ 25C), with intrinsic
fast freewheeling diode. Cross conduction protection
is achieved using a dead time (td = 1
s typical) be-
tween the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figure 3. Charge Pump Circuit
LOGIC INPUTS
Pins IN1
A
, IN2
A
, IN1
B
, IN2
B
, EN
A
and EN
B
are TTL/
CMOS and uC compatible logic inputs. The internal
structure is shown in Fig. 4. Typical value for turn-on
and turn-off thresholds are respectively Vthon=1.8V
and Vthoff = 1.3V.
Pins EN
A
and EN
B
are commonly used to implement
Overcurrent and Thermal protection by connecting
them respectively to the outputs OCD
A
and OCD
B
,
which are open-drain outputs. If that type of connec-
tion is chosen, some care needs to be taken in driving
these pins. Two configurations are shown in Fig. 5
and Fig. 6. If driven by an open drain (collector) struc-
ture, a pull-up resistor R
EN
and a capacitor C
EN
are
connected as shown in Fig. 5. If the driver is a stan-
dard Push-Pull structure the resistor R
EN
and the ca-
pacitor C
EN
are connected as shown in Fig. 6. The
resistor R
EN
should be chosen in the range from
2.2k
to 180K
. Recommended values for R
EN
and
C
EN
are respectively 100K
and 5.6nF. More infor-
mation on selecting the values is found in the Over-
current Protection section.
Figure 4. Logic Inputs Internal Structure
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
TRUTH TABLE
X
= Don't care
High Z = High Impedance Output
C
BOOT
220nF
C
P
10nF
R
P
100
D1
1N4148
D2
1N4148
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP
VBOOT
VS
B
D01IN1328
INPUTS
OUTPUTS
EN
IN1
IN2
OUT1
OUT2
L
X
X
High Z
High Z
H
L
L
GND
GND
H
H
L
Vs
GND
H
L
H
GND
Vs
H
H
H
Vs
Vs
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
A
or EN
B
OCD
A
or OCD
B
D02IN1355
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
D02IN1356
OCD
A
or OCD
B
9/23
L6206
NON-DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION
In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated. This circuit can be
used to provides protection against a short circuit to ground or between two phases of the bridge as well as a
roughly regulation of the load current. With this internal over current detection, the external current sense resis-
tor normally used and its associated power dissipation are eliminated. Fig. 7 shows a simplified schematic of
the overcurrent detection circuit for the Bridge A. Bridge B is provided of an analogous circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current reaches the detection threshold Isover the OCD comparator signals a fault
condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA
connected to OCD pin is turned on. Fig. 8 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to EN pin and adding
an external R-C as shown in Fig.7. The off time before recovering normal operation can be easily programmed
by means of the accurate thresholds of the logic inputs.
I
REF
and, therefore, the output current detection threshold are selectable by R
CL
value, following the equations:
Isover = 5.6A 30% at -25C < T
j
< 125C if R
CL
= 0
(PROGCL connected to GND)
Isover =
10% at -25C < T
j
< 125C if 5K
<
R
CL
< 40k
Fig. 9 shows the output current protection threshold versus R
CL
value in the range 5k
to 40k
.
The Disable Time t
DISABLE
before recovering normal operation can be easily programmed by means of the accu-
rate thresholds of the logic inputs. It is affected whether by C
EN
and R
EN
values and its magnitude is reported in
Figure 10. The Delay Time t
DELAY
before turning off the bridge when an overcurrent has been detected depends
only by C
EN
value. Its magnitude is reported in Figure 11.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should
be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should be chosen
according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
to 180K
. Recommended values for R
EN
and C
EN
are respectively 100K
and 5.6nF that allow obtaining 200
s Disable Time.
22100
R
C L
----------------
L6206
10/23
Figure 7. Overcurrent Protection Simplified Schematic
Figure 8. Overcurrent Protection Waveforms
+
OVER
TEMPERATURE
I
REF
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40
TYP.
C
ENA
R
ENA
R
CLA
.
EN
A
OCD
A
PROGCL
A,
+5V
1.2V
-
+
C or LOGIC
D02IN1354
I
SOVER
I
OUT
V
th(ON)
V
th(OFF)
V
EN(LOW)
V
DD
t
OCD(ON)
t
D(ON)EN
t
EN(FALL)
t
EN(RISE)
t
DISABLE
t
DELAY
t
OCD(OFF)
t
D(OFF)EN
V
EN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
11/23
L6206
Figure 9. Output Current Protection Threshold versus R
CL
Value
Figure 10. t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5V).
5k 10k 15k 20k 25k 30k 35k 40k
0
0.5
1
1.5
2
2.5
3
3.5
5
R
C L
[
]
4
4.5
I
SO VER
[A]
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[ n F ]
t
DIS
AB
L
E
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[ n F ]
t
DIS
AB
L
E
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
L6206
12/23
Figure 11. t
DELAY
versus C
EN
(V
DD
= 5V).
THERMAL PROTECTION
In addition to the Ovecurrent Detection, the L6206 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165C (typ. value)
with 15C hysteresis (typ. value).
1
10
100
0.1
1
10
Cen [nF]
t
del
ay
[
s]
13/23
L6206
APPLICATION INFORMATION
A typical application using L6206 is shown in Fig. 12. Typical component values for the application are shown
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VS
A
and VS
B
) and ground near the L6206 to improve the high frequency filtering on the power supply and
reduce high frequency transients generated by the switching. The capacitors connected from the EN
A
/OCD
A
and EN
B
/OCD
B
nodes to ground set the shut down time for the Brgidge A and Bridge B respectively when an
over current is detected (see Overcurrent Protection). The two current sources (SENSE
A
and SENSE
B
) should
be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immu-
nity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin descrip-
tion). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
Figure 12. Typical Application
C
1
100uF
D
1
1N4148
C
2
100nF
D
2
1N4148
C
BOOT
220nF
R
CLA
5K
C
P
10nF
R
CLB
5K
C
ENA
5.6nF
R
ENA
100k
C
ENB
5.6nF
R
ENB
100k
C
REF
68nF
R
P
100
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
A
LOAD
B
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN1
A
IN2
A
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
ENB
R
ENB
R
ENA
EN
A
EN
B
23
IN2
B
12
IN1
B
IN2
B
IN1
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
C
ENA
PROGCL
B
13
R
CLB
D02IN1344
L6206
14/23
PARALLELED OPERATION
The outputs of the L6206 can be paralleled to increase the output current capability or reduce the power dissi-
pation in the device at a given current level. It must be noted, however, that the internal wire bond connections
from the die to the power or sense pins of the package must carry current in both of the associated half bridges.
When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on the power supply
or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detec-
tion threshold.
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 13. The current in the two devices
connected in parallel will share very well since the R
DS(ON)
of the devices on the same die is well matched.
When connected in this configuration the over current detection circuit, which senses the current in each bridge
(A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with
the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in
either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current
equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors
R
CLA
or R
CLB
in figure 13. It is recommended to use R
CLA
= R
CLB
.
In this configuration the resulting Bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.15
Typ. Value @ T
J
= 25C
- 5.6A max RMS Load Current
- 11.2A max OCD Threshold
Figure 13. Parallel connection for higher current
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN2
IN1
A
IN2
B
12
6
7
9
EN
A
EN
B
R
EN
EN
23
IN1
B
11
IN2
A
IN1
2
14
24
17
3
15
22
SENSE
B
R
CLA
10
C
EN
PROGCL
B
13
R
CLB
D02IN1364
15/23
L6206
To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge
2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 14. In
this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense
pins so the dissipation in the device will be reduced, but the peak current rating is not increased.
When connected in this configuration the over current detection circuit, senses the sum of the current in upper
devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges.
Since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold
set the resistor R
CLA
or R
CLB
in figure 14. R
CLA
sets the threshold when outputs OUT1
A
and OUT2
A
are high
and resistor R
CLB
sets the threshold when outputs OUT1
B
and OUT2
B
are high.
It is recommended to use R
CLA
= R
CLB
.
In this configuration, the resulting bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.15
Typ. Value @ T
J
= 25C
- 2.8A max RMS Load Current
- 5.6A max OCD Threshold
Figure 14. Parallel connection with lower Overcurrent Threshold
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
A
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
IN
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13
R
CLB
D02IN1361
L6206
16/23
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 15. In this
configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors R
CLA
or R
CLB
in Figure 15. It is recommended to use R
CLA
= R
CLB
.
The resulting half bridge has the following characteristics.
- Equivalent Device: HALF BRIDGE
- R
DS(ON)
0.075
Typ. Value @ T
J
= 25C
- 5.6A max RMS Load Current
- 11.2A max OCD Threshold
Figure 15. Paralleling the four Half Bridges
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13
R
CLB
D02IN1365
17/23
L6206
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fig. 16 and Fig. 17 are shown the approximate relation between the output current and the IC power dissipa-
tion using PWM current control driving two loads, for two different driving types:
One Full Bridge ON at a time (Fig.16) in which only one load at a time is energized.
Two Full Bridges ON at the same time (Fig.17) in which two loads at the same time are energized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125C maximum).
Figure 16. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.
Figure 17. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be de-
liver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the
available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can
be achieved using copper on the PCB with proper area and thickness. Figures 19, 20 and 21 show the Junction-to-
Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board
with 6cm
2
dissipating footprint (copper thickness of 35m), the R
th j-amb
is about 35C/W. Fig. 18 shows mount-
ing methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be
reduced down to 15C/W.
No PWM
f
SW
= 30kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
I
A
I
B
I
OUT
I
OUT
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W]
I
OUT
[A]
ONE FULL BRIDGE ON AT A TIME
No PWM
f
SW
= 30kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
I
A
I
B
I
OUT
I
OUT
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W ]
I
OUT
[A ]
TWO FULL BRIDGES ON AT THE SAME TIME
L6206
18/23
Figure 18. Mounting the PowerSO package.
Figure 19. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
Figure 20. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 21. SO24 Junction-Ambient thermal resistance versus on-board copper area.
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
13
18
23
28
33
38
43
1
2
3
4
5
6
7
8
9
10
1 1
1 2
13
W ith o ut G ro u nd La yer
W ith Gr o un d La yer
W ith Gr o un d La yer + 16 via
H o le s
s q . c m
C / W
On-Board Copper Area
39
40
41
42
43
44
45
46
47
48
49
1
2
3
4
5
6
7
8
9
10
11
12
C o p pe r Are a is o n Bo tto m
S id e
C o p pe r Are a is o n To p S i de
s q . cm
C / W
On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
1
2
3
4
5
6
7
8
9
10
11
12
C o pp er A re a is o n T op S id e
s q. cm
C / W
On-Board Copper Area
19/23
L6206
Figure 22. Typical Quiescent Current vs.
Supply Voltage
Figure 23. Normalized Typical Quiescent
Current vs. Switching Frequency
Figure 24. Typical Low-Side R
DS(ON)
vs.
Supply Voltage
Figure 25. Typical High-Side RDS(ON) vs.
Supply Voltage
Figure 26. Normalized R
DS(ON)
vs.Junction
Temperature (typical value)
Figure 27. Typical Drain-Source Diode
Forward ON Characteristic
4 .6
4 .8
5 .0
5 .2
5 .4
5 .6
0
10
2 0
3 0
40
5 0
6 0
Iq [m A ]
V
S
[V ]
f
sw
= 1kHz
T
j
= 25C
T
j
= 85C
T
j
= 125C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0
20
40
60
80
100
Iq / (Iq @ 1 kHz)
f
SW
[kHz]
0.276
0.280
0.284
0.288
0.292
0.296
0.300
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.336
0.340
0.344
0.348
0.352
0.356
0.360
0.364
0.368
0.372
0.376
0.380
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.8
1.0
1.2
1.4
1.6
1.8
0
20
40
60
80
100
120
140
R
DS(ON)
/ (R
DS(ON)
@ 25 C )
Tj [C]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
700
800
900
1000
1100
1200
1300
I
SD
[A]
V
SD
[mV]
T
j
= 25C
L6206
20/23
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.60
0.141
a1
0.10
0.30
0.004
0.012
a2
3.30
0.130
a3
0
0.10
0
0.004
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D (1)
15.80
16.00
0.622
0.630
D1
9.40
9.80
0.370
0.385
E
13.90
14.50
0.547
0.570
e
0.65
0.0256
e3
11.05
0.435
E1 (1)
10.90
11.10
0.429
0.437
E2
2.90
0.114
E3
5.80
6.20
0.228
0.244
E4
2.90
3.20
0.114
0.126
G
0
0.10
0
0.004
H
15.50
15.90
0.610
0.626
h
1.10
0.043
L
0.80
1.10
0.031
0.043
N
10
(max.)
S
8
(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
21/23
L6206
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.320
0.170
A1
0.380
0.015
A2
3.300
0.130
B
0.410
0.460
0.510
0.016
0.018
0.020
B1
1.400
1.520
1.650
0.055
0.060
0.065
c
0.200
0.250
0.300
0.008
0.010
0.012
D
31.62
31.75
31.88
1.245
1.250
1.255
E
7.620
8.260
0.300
0.325
e
2.54
0.100
E1
6.350
6.600
6.860
0.250
0.260
0.270
e1
7.620
0.300
L
3.180
3.430
0.125
0.135
M
0 min, 15 max.
Powerdip 24
A1
B
e
B1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DATA
L6206
22/23
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D
(1)
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0;75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
(1) "D" dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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23/23
L6206