ChipFind - документация

Электронный компонент: L6208D

Скачать:  PDF   ZIP
1/27
L6208
September 2003
s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
s
5.6A OUTPUT PEAK CURRENT (2.8A RMS)
s
R
DS(ON)
0.3
TYP. VALUE @ T
j
= 25C
s
OPERATING FREQUENCY UP TO 100KHz
s
NON DISSIPATIVE OVERCURRENT
PROTECTION
s
DUAL INDEPENDENT CONSTANT t
OFF
PWM
CURRENT CONTROLLERS
s
FAST/SLOW DECAY MODE SELECTION
s
FAST DECAY QUASI-SYNCHRONOUS
RECTIFICATION
s
DECODING LOGIC FOR STEPPER MOTOR
FULL AND HALF STEP DRIVE
s
CROSS CONDUCTION PROTECTION
s
THERMAL SHUTDOWN
s
UNDER VOLTAGE LOCKOUT
s
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
s
BIPOLAR STEPPER MOTOR
DESCRIPTION
The L6208 is a DMOS Fully Integrated Stepper Motor
Driver with non-dissipative Overcurrent Protection,
realized in MultiPower-BCD technology, which com-
bines isolated DMOS Power Transistors with CMOS
and bipolar circuits on the same chip. The device in-
cludes all the circuitry needed to drive a two-phase
bipolar stepper motor including: a dual DMOS Full
Bridge, the constant off time PWM Current Controller
that performs the chopping regulation and the Phase
Sequence Generator, that generates the stepping
sequence. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L6208 features a non-dissipative overcurrent protec-
tion on the high side Power MOSFETs and thermal
shutdown.
BLOCK DIAGRAM
GATE
LOGIC
STEPPING
SEQUENCE
GENERATION
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
CONTROL
CW/CCW
VREF
A
V
BOOT
5V
10V
VS
A
VS
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
ONE SHOT
MONOSTABLE
MASKING
TIME
THERMAL
PROTECTION
V
BOOT
V
BOOT
OCD
B
OCD
A
10V
10V
BRIDGE A
SENSE
COMPARATOR
BRIDGE B
D01IN1225
RC
A
+
-
SENSE
B
VREF
B
RC
B
HALF/FULL
CLOCK
RESET
PWM
ORDERING NUMBERS:
L6208N (PowerDIP24)
L6208PD (PowerSO36)
L6208D (SO24)
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
DMOS DRIVER FOR BIPOLAR STEPPER MOTOR
L6208
2/27
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Test conditions
Value
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
60
V
V
OD
Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
= 60V;
V
SENSEA
= V
SENSEB
= GND
60
V
V
BOOT
Bootstrap Peak Voltage
V
SA
= V
SB
= V
S
V
S
+ 10
V
V
IN
,V
EN
Input and Enable Voltage Range
-0.3 to +7
V
V
REFA
,
V
REFB
Voltage Range at pins V
REFA
and V
REFB
-0.3 to +7
V
V
RCA,
V
RCB
Voltage Range at pins RC
A
and
RC
B
-0.3 to +7
V
V
SENSEA,
V
SENSEB
Voltage Range at pins SENSE
A
and SENSE
B
-1 to +4
V
I
S(peak)
Pulsed Supply Current (for each
V
S
pin), internally limited by the
overcurrent protection
V
SA
= V
SB
= V
S
;
t
PULSE
< 1ms
7.1
A
I
S
RMS Supply Current (for each
V
S
pin)
V
SA
= V
SB
= V
S
2.8
A
T
stg
, T
OP
Storage and Operating
Temperature Range
-40 to 150
C
Symbol
Parameter
Test Conditions
MIN
MAX
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
8
52
V
V
OD
Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
52
V
V
REFA
,
V
REFB
Voltage Range at pins V
REFA
and V
REFB
-0.1
5
V
V
SENSEA,
V
SENSEB
Voltage Range at pins SENSE
A
and SENSE
B
(pulsed t
W
< t
rr
)
(DC)
-6
-1
6
1
V
V
I
OUT
RMS Output Current
2.8
A
T
j
Operating Junction Temperature
-25
+125
C
f
sw
Switching Frequency
100
KHz
3/27
L6208
THERMAL DATA
PIN CONNECTIONS (Top View)
(5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
Symbol
Description
PowerDIP24
SO24
PowerSO36
Unit
R
th-j-pins
Maximum Thermal Resistance Junction-Pins
18
14
-
C/W
R
th-j-case
Maximum Thermal Resistance Junction-Case
-
-
1
C/W
R
th-j-amb1
Maximum Thermal Resistance Junction-Ambient
(1)
(1)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm
2
(with a thickness of 35m).
43
51
-
C/W
R
th-j-amb1
Maximum Thermal Resistance Junction-Ambient
(2)
(2)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm
2
(with a thickness of 35m).
-
-
35
C/W
R
th-j-amb1
Maximum Thermal Resistance Junction-Ambient
(3)
(3)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm
2
(with a thickness of 35m), 16 via holes
and a ground layer.
-
-
15
C/W
R
th-j-amb2
Maximum Thermal Resistance Junction-Ambient
(4)
(4)
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
58
77
62
C/W
GND
GND
OUT1
B
RC
B
SENSE
B
HALF/FULL
VREF
B
1
3
2
4
5
6
7
8
9
CONTROL
VBOOT
EN
OUT2
B
VS
B
GND
GND
19
18
17
16
15
13
14
D99IN1083
10
11
12
24
23
22
21
20
CLOCK
CW/CCW
SENSE
A
RC
A
OUT1
A
VS
A
OUT2
A
VCP
RESET
VREF
A
GND
N.C.
N.C.
VS
A
RC
A
OUT1
A
N.C.
N.C.
N.C.
N.C.
N.C.
OUT1
B
RC
B
N.C.
VS
B
N.C.
N.C.
GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
GND
GND
D99IN1084
CLOCK
SENSE
A
CW/CCW
SENSE
B
HALF/FULL
VREF
B
9
8
7
28
29
30
VREF
A
CONTROL
10
27
OUT2
A
RESET
VCP
EN
OUT2
B
VBOOT
14
12
11
23
25
26
N.C.
N.C.
13
24
PowerDIP24/SO24
PowerSO36
(5)
L6208
4/27
PIN DESCRIPTION
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
1
10
CLOCK
Logic Input
Step Clock input. The state machine makes one step on
each rising edge.
2
11
CW/CCW
Logic Input
Selects the direction of the rotation. HIGH logic level sets
clockwise direction, whereas LOW logic level sets
counterclockwise direction.
If not used, it has to be connected to GND or +5V.
3
12
SENSE
A
Power Supply
Bridge A Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
4
13
RC
A
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
5
15
OUT1
A
Power Output
Bridge A Output 1.
6, 7,
18, 19
1, 18,
19, 36
GND
GND
Ground terminals. In PowerDIP24 and SO24 packages,
these pins are also used for heat dissipation toward the
PCB. On PowerSO36 package the slug is connected to
these pins.
8
22
OUT1
B
Power Output
Bridge B Output 1.
9
24
RC
B
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
10
25
SENSE
B
Power Supply
Bridge B Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
11
26
VREF
B
Analog Input
Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
12
27
HALF/FULL
Logic Input
Step Mode Selector. HIGH logic level sets HALF STEP
Mode, LOW logic level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5V.
13
28
CONTROL
Logic Input
Decay Mode Selector. HIGH logic level sets SLOW DECAY
Mode. LOW logic level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5V.
14
29
EN
Logic Input
(6)
Chip Enable. LOW logic level switches OFF all Power
MOSFETs of both Bridge A and Bridge B. This pin is also
connected to the collector of the Overcurrent and Thermal
Protection to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
15
30
VBOOT
Supply
Voltage
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16
32
OUT2
B
Power Output
Bridge B Output 2.
17
33
VS
B
Power Supply
Bridge B Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VS
A
20
4
VS
A
Power Supply
Bridge A Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VS
B
5/27
L6208
(6)
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series
a resistor with a value in the range of 2.2K
- 180K
, recommended 100K
.
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
21
5
OUT2
A
Power Output
Bridge A Output 2.
22
7
VCP
Output
Charge Pump Oscillator Output.
23
8
RESET
Logic Input
Reset Pin. LOW logic level restores the
Home
State
(State 1) on the Phase Sequence Generator State
Machine.
If not used, it has to be connected to +5V.
24
9
VREF
A
Analog Input
Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
ELECTRICAL CHARACTERISTICS
(T
amb
= 25C, V
s
= 48V, unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
V
Sth(ON)
Turn-on Threshold
6.6
7
7.4
V
V
Sth(OFF)
Turn-off Threshold
5.6
6
6.4
V
I
S
Quiescent Supply Current
All Bridges OFF;
T
j
= -25C to 125C
(7)
5
10
mA
T
j(OFF)
Thermal Shutdown Temperature
165
C
Output DMOS Transistors
R
DS(ON)
High-Side Switch ON Resistance T
j
= 25
C
0.34
0.4
T
j
=125
C
(7)
0.53
0.59
Low-Side Switch ON Resistance
T
j
= 25
C
0.28
0.34
T
j
=125
C
(7)
0.47
0.53
I
DSS
Leakage Current
EN = Low; OUT = V
S
2
mA
EN = Low; OUT = GND
-0.15
mA
Source Drain Diodes
V
SD
Forward ON Voltage
I
SD
= 2.8A, EN = LOW
1.15
1.3
V
t
rr
Reverse Recovery Time
I
f
= 2.8A
300
ns
t
fr
Forward Recovery Time
200
ns
Logic Inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
V
IL
Low level logic input voltage
-0.3
0.8
V
V
IH
High level logic input voltage
2
7
V
PIN DESCRIPTION (continued)
L6208
6/27
I
IL
Low Level Logic Input Current
GND Logic Input Voltage
-10
A
I
IH
High Level Logic Input Current
7V Logic Input Voltage
10
A
V
th(ON)
Turn-on Input Threshold
1.8
2.0
V
V
th(OFF)
Turn-off Input Threshold
0.8
1.3
V
V
th(HYS)
Input Threshold Hysteresis
0.25
0.5
V
Switching Characteristics
t
D(ON)EN
Enable to Output Turn-on Delay
Time
(8)
I
LOAD
=2.8A, Resistive Load
100
250
400
ns
t
D(OFF)EN
Enable to Output Turn-off Delay
Time
(8)
I
LOAD
=2.8A, Resistive Load
300
550
800
ns
t
RISE
Output Rise Time
(8)
I
LOAD
=2.8A, Resistive Load
40
250
ns
t
FALL
Output Fall Time
(8)
I
LOAD
=2.8A, Resistive Load
40
250
ns
t
DCLK
Clock to Output Delay Time
(9)
I
LOAD
=2.8A, Resistive Load
2
s
t
CLK(min)L
Minimum Clock Time
(10)
1
s
t
CLK(min)
H
Minimum Clock Time
(10)
1
s
f
CLK
Clock Frequency
100
KHz
t
S(MIN)
Minimum Set-up Time
(11)
1
s
t
H(MIN)
Minimum Hold Time
(11)
1
s
t
R(MIN)
Minimum Reset Time
(11)
1
s
t
RCLK(MIN
)
Minimum Reset to Clock Delay
Time
(11)
1
s
t
DT
Dead Time Protection
0.5
1
s
f
CP
Charge Pump Frequency
T
j
= -25C to 125C
(7)
0.6
1
MHz
PWM Comparator and Monostable
I
RCA,
I
RCB
Source Current at pins RC
A
and
RC
B
V
RCA
= V
RCB
= 2.5V
3.5
5.5
mA
V
offset
Offset Voltage on Sense
Comparator
V
REFA,
V
REFB
= 0.5V
5
mV
t
PROP
Turn OFF Propagation Delay
(12)
500
ns
t
BLANK
Internal Blanking Time on
SENSE pins
1
s
t
ON(MIN)
Minimum On Time
1.5
2
s
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25C, V
s
= 48V, unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
7/27
L6208
(7)
Tested at 25C in a restricted range and guaranteed by characterization.
(8)
See Fig. 1.
(9)
See Fig. 2.
(10)
See Fig. 3.
(11) See
Fig.
4.
(12)
Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(13)
See Fig. 5.
Figure 1. Switching Characteristic Definition
t
OFF
PWM Recirculation Time
R
OFF
= 20K
;
C
OFF
= 1nF
13
s
R
OFF
= 100K
;
C
OFF
= 1nF
61
s
I
BIAS
Input Bias Current at pins VREF
A
and VREF
B
10
A
Over Current Protection
I
SOVER
Input Supply Overcurrent
Protection Threshold
T
j
= -25C to 125C
(7)
4
5.6
7.1
A
R
OPDR
Open Drain ON Resistance
I = 4mA
40
60
t
OCD(ON)
OCD Turn-on Delay Time (13)
I = 4mA; C
EN
< 100pF
200
ns
t
OCD(OFF)
OCD Turn-off Delay Time (13)
I = 4mA; C
EN
< 100pF
100
ns
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25C, V
s
= 48V, unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
L6208
8/27
Figure 2. Clock to Output Delay Time
Figure 3. Minimum Timing Definition; Clock Input
Figure 4. Minimum Timing Definition; Logic Inputs
CLOCK
I
OUT
t
t
t
DCLK
V
th(ON)
D01IN1317
CLOCK
t
CLK(MIN)H
t
CLK(MIN)L
V
th(OFF)
V
th(ON)
D01IN1318
V
th(OFF)
CLOCK
RESET
t
S(MIN)
t
H(MIN)
t
R(MIN)
t
RCLK(MIN)
LOGIC INPUTS
D01IN1319
V
th(OFF)
V
th(ON)
V
th(ON)
9/27
L6208
Figure 5. Overcurrent Detection Timing Definition
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6208 integrates two independent Power MOS Full Bridges. Each Power MOS has an R
DS(ON)
= 0.3
(typ-
ical value @ 25C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current
Controller and the Phase Sequence Generator (see below). Cross conduction protection is achieved using a
dead time (t
DT
= 1
s typical value) between the switch off and switch on of two Power MOSFETSs in one leg of
a bridge.
Pins VS
A
and VS
B
MUST be connected together to the supply voltage V
S
. The device operates with a supply
voltage in the range from 8V to 52V. It has to be noticed that the R
DS(ON)
increases of some percents when the
supply voltage is in the range from 8V to 12V (see Fig. 34 and 35).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The bootstrapped supply voltage V
BOOT
is obtained through an internal Oscillator and few
external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (VCP) is a
square wave at 600KHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 1.
Table 1. Charge Pump External Components Values
C
BOOT
220nF
C
P
10nF
R
P
100
D1
1N4148
D2
1N4148
I
SOVER
90%
10%
I
OUT
V
EN
t
OCD(OFF)
t
OCD(ON)
D02IN1399
ON
OFF
BRIDGE
L6208
10/27
Figure 6. Charge Pump Circuit
LOGIC INPUTS
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC compatible logic inputs.
The internal structure is shown in Fig. 7. Typical value for turn-on and turn-off thresholds are respectively
V
th(ON)
= 1.8V and V
th(OFF)
= 1.3V.
Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal
protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving
this pin. The EN input may be driven in one of two configurations as shown in Fig. 8 or 9. If driven by an open
drain (collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in Fig. 8. If the
driver is a standard Push-Pull structure the resistor R
EN
and the capacitor C
EN
are connected as shown in Fig.
9. The resistor R
EN
should be chosen in the range from 2.2K
to 180K
. Recommended values for R
EN
and
C
EN
are respectively 100K
and 5.6nF. More information on selecting the values is found in the Overcurrent
Protection section.
Figure 7. Logic Inputs Internal Structure
Figure 8. EN Pin Open Collector Driving
Figure 9. EN Pin Push-Pull Driving
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP
VBOOT
VS
B
D01IN1328
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
D01IN1330
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
D01IN1331
ESD
PROTECTION
11/27
L6208
PWM CURRENT CONTROL
The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 10. As the current in
the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREF
A
or VREF
B
) the sense
comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates as defined by the selected decay mode, described in the next
section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to pre-
vent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the
monostable time plus the dead time.
Figure 10. PWM Current Controller Simplified Schematic
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the
reverse recovery of the freewheeling diodes. The L6208 provides a 1
s Blanking Time t
BLANK
that inhibits the
comparator output so that this current spike cannot prematurely re-trigger the monostable.
DRIVERS
+
DEAD TIME
S
Q
R
DRIVERS
+
DEAD TIME
2H
1H
2L
1L
OUT2A(or B)
SENSEA(or B)
RSENSE
D01IN1332
RCA(or B)
R
OFF
C
OFF
VREFA(or B)
IOUT
OUT1A(or B)
+
+
-
-
1
s
5mA
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
MONOSTABLE
SET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
2 PHASE
STEPPER MOTOR
BLANKING TIME
MONOSTABLE
VS
A
(or
B
)
TO GATE LOGIC
(0)
(1)
L6208
12/27
Figure 11. Output Current Regulation Waveforms
Figure 12 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately
calculated from the equations:
t
RCFALL
= 0.6 R
OFF
C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 R
OFF
C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
R
OFF
100K
0.47nF
C
OFF
100nF
t
DT
= 1s (typical value)
Therefore:
t
OFF(MIN)
= 6.6s
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Rise Time t
RCRISE
of the voltage at the pin RCOFF. The
Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
ON
, which depends by motors and supply parameters, has to
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
OFF
B
C
D
D
A
t
ON
t
OFF
t
OFF
B
C
ON
2.5V
0
Fast Deca
y
Fast Deca
y
Slow Decay
Slow Decay
1
s t
BLANK
t
RCRISE
1
s t
DT
1
s t
DT
t
RCRISE
t
RCFALL
t
RCFALL
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
1
s t
BLANK
5V
V
RC
V
SENSE
V
REF
I
OUT
V
REF
R
SENSE
D01IN1334
13/27
L6208
t
RCRISE
= 600 C
OFF
Figure 13 shows the lower limit for the on time t
ON
for having a good PWM current regulation capacity. It has to
be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be smaller
than t
RCRISE
- t
DT
. In this last case the device continues to work but the off time t
OFF
is not more constant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the circuit
performance.
Figure 12. t
OFF
versus C
OFF
and R
OFF
Figure 13. Area where t
ON
can vary maintaining the PWM regulation.
t
O N
t
O N MIN
(
)
>
1.5
s (typ. value)
=
t
O N
t
R C R IS E
t
D T
>
0.1
1
10
100
1
10
100
1 .10
3
1 .10
4
Coff [nF]
to
ff
[
s]
R
off
= 100k
R
off
= 47k
R
off
= 20k
0.1
1
10
100
1
10
100
Coff [nF]
t
on(
mi
n)
[
s]
1.5
s (typ. value)
L6208
14/27
DECAY MODES
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin
is low, the Fast Decay mode is selected and both transistors in the bridge are switched off during the off time.
When the CONTROL pin is high, the Slow Decay mode is selected and only the low side transistor of the bridge
is switched off during the off time.
Figure 14 shows the operation of the bridge in the Fast Decay mode. At the start of the off time, both of the
power MOS are switched off and the current recirculates through the two opposite free wheeling diodes. The
current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After
the dead time, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectifica-
tion mode. In applications where the motor current is low it is possible that the current can decay completely to
zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification
mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower
power MOS is operated in synchronous rectification mode. This operation is called Quasi-Synchronous Recti-
fication Mode. When the monostable times out, the power MOS are turned on again after some delay set by the
dead time to prevent cross conduction.
Figure 15 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 14. Fast Decay Mode Output Stage Configurations
Figure 15. Slow Decay Mode Output Stage Configurations
STEPPING SEQUENCE GENERATION
The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges
to drive a stepper motor in either full step or half step. Two full step modes are possible, the Normal Drive Mode
where both phases are energized each step and the Wave Drive Mode where only one phase is energized at a
A) ON TIME
B) 1
s DEAD TIME
C) QUASI-SYNCHRONOUS
RECTIFICATION
D) 1
s SLOW DECAY
D01IN1335
A) ON TIME
B) 1
s DEAD TIME
C) SYNCHRONOUS
RECTIFICATION
D) 1
s DEAD TIME
D01IN1336
15/27
L6208
time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction
of rotation is set by the CW/CCW input. The RESET input resets the state machine to state.
HALF STEP MODE
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 16 shows the motor current wave-
forms and the state diagram for the Phase Sequencer Generator. At Start-Up or after a RESET the Phase Se-
quencer is at state 1. After each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,... if CW/
CCW is high (Clockwise movement) or 1,8,7,6,5,4,3,2,... if CW/CCW is low (Counterclockwise movement).
NORMAL DRIVE MODE (Full-step two-phase-on)
A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is applied when the state
machine is at an ODD numbered state the Normal Drive Mode is selected. Figure Fig. 17 shows the motor cur-
rent waveform state diagram for the state machine of the Phase Sequencer Generator. The Normal Drive Mode
can easily be selected by holding the HALF/FULL input low and applying a RESET. AT start -up or after a RE-
SET the State Machine is in state1. While the HALF/FULL input is kept low, state changes following the se-
quence 1,3,5,7,... if CW/CCW is high (Clockwise movement) or 1,7,5,3,... if CW/CCW is low (Counterclockwise
movement).
WAVE DRIVE MODE (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is applied when the
state machine is at an EVEN numbered state the Wave Drive Mode is selected. Figure 18 shows the motor cur-
rent waveform and the state diagram for the state machine of the Phase Sequence Generator. To enter the
Wave Drive Mode the state machine must be in an EVEN numbered state. The most direct method to select the
Wave Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to
the clock input then take the HALF/FULL input low. This sequence first forces the state machine to sate 1. The
clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 de-
pending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the
state machine following the sequence 2,4,6,8,... if CW/CCW is high (Clockwise movement) or 8,6,4,2,... if CW/
CCW is low (Counterclockwise movement).
Figure 16. Half Step Mode
Figure 17. Normal Drive Mode
3
2
4
5
1
D01IN1320
2
3
4
5
6
7
8
6
1
8
7
I
OUTA
I
OUTB
CLOCK
Start Up or Reset
2
4
1
D01IN1322
3
5
7
1
3
5
7
6
8
I
OUTA
I
OUTB
CLOCK
3
5
1
7
Start Up or Reset
L6208
16/27
Figure 18. Wave Drive Mode
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6208 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external cur-
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a sim-
plified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current reaches the detection threshold (typically 5.6A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typ-
ical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin,
the off time before recovering normal operation can be easily programmed by means of the accurate thresholds
of the logic inputs.
Figure 19. Overcurrent Protection Simplified Schematic
2
4
2
D01IN1321
4
6
8
2
4
6
8
6
8
I
OUTA
I
OUTB
CLOCK
3
5
1
7
Start Up or Reset
+
OVER TEMPERATURE
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
FROM THE
BRIDGE B
OCD
COMPARATOR
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40
TYP.
C
EN
.
R
EN
.
EN
V
DD
C or LOGIC
D01IN1337
17/27
L6208
Figure 20 shows the Overcurrent Detection operation. The Disable Time t
DISABLE
before recovering normal oper-
ation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
EN
and R
EN
values and its magnitude is reported in Figure 21. The Delay Time t
DELAY
before turning off the
bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in Figure 22.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should
be chosen according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
to 180K
. Recommended values for R
EN
and C
EN
are respectively 100K
and 5.6nF that allow obtaining 200
s Disable Time.
Figure 20. Overcurrent Protection Waveforms
I
SOVER
I
OUT
V
th(ON)
V
th(OFF)
V
EN(LOW)
V
DD
t
OCD(ON)
t
D(ON)EN
t
EN(FALL)
t
EN(RISE)
t
DISABLE
t
DELAY
t
OCD(OFF)
t
D(OFF)EN
V
EN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
L6208
18/27
Figure 21. t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5V).
Figure 22. t
DELAY
versus C
EN
(V
DD
= 5V).
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6208 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165C (typ. value)
with 15C hysteresis (typ. value).
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[n F ]
t
DIS
AB
L
E
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[n F ]
t
DIS
AB
L
E
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
1
10
100
0.1
1
10
Cen [nF]
t
d
el
ay
[
s]
19/27
L6208
APPLICATION INFORMATION
A typical Bipolar Stepper Motor Driver application using L6208 is shown in Fig. 23. Typical component values
for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should
be placed between the power pins (VS
A
and VS
B
) and ground near the L6208 to improve the high frequency
filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is detected (see Overcur-
rent Protection). The two current sensing inputs (SENSE
A
and SENSE
B
) should be connected to the sensing
resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive re-
sistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recom-
mended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
Figure 23. Typical Application
C
1
100F
D
1
1N4148
C
2
100nF
D
2
1N4148
C
A
1nF
R
A
39K
C
B
1nF
R
B
39K
C
BOOT
220nF
R
EN
100K
C
P
10nF
R
P
100
C
EN
5.6nF
R
SENSEA
0.3
C
REF
68nF
R
SENSEB
0.3
M
OUT1
A
VREF
A
VREF
B
CLOCK
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
RC
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
V
S
8-52V
DC
24
VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
R
SENSEA
20
CW/CCW
CLOCK
CW/CCW
2
6
7
11
RESET
EN
C
EN
R
EN
RESET
ENABLE
V
REF
= 0-1V
23
HALF/FULL
HALF/FULL
12
CONTROL
FAST/SLOW DECAY
13
14
4
17
3
15
22
SENSE
B
R
SENSEB
C
A
R
A
10
C
REF
RC
B
9
C
B
R
B
D01IN1341
L6208
20/27
Output Current Capability and IC Power Dissipation
In Fig. 24, 25, 26 and 27 are shown the approximate relation between the output current and the IC power dis-
sipation using PWM current control driving a two-phase stepper motor, for different driving sequences:
HALF STEP mode (Fig. 24) in which alternately one phase / two phases are energized.
NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Fig. 25) in which two phases are energized
during each step.
WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Fig. 26) in which only one phase is energized at
each step.
MICROSTEPPING mode (Fig. 27), in which the current follows a sine-wave profile, provided through
the V
ref
pins.
For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125C maximum).
Figure 24. IC Power Dissipation versus Output Current in HALF STEP Mode.
Figure 25. IC Power Dissipation versus Output Current in NORMAL Mode (full step two phase on).
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
I
A
I
B
I
OUT
I
OUT
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W]
I
OUT
[A ]
HALF STEP
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Volt age = 24 V
I
A
I
B
I
OUT
I
OUT
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W ]
I
OUT
[A ]
NORM AL DRIVE
21/27
L6208
Figure 26. IC Power Dissipation versus Output Current in WAVE Mode (full step one phase on).
Figure 27. IC Power Dissipation versus Output Current in MICROSTEPPING Mode.
Thermal Management
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully.
Besides the available space on the PCB, the right package should be chosen considering the power dissipation.
Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 28, 29 and 30
show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packag-
es.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6cm
2
dissipating footprint (copper thickness of 35m), the R
th(j-amb)
is about 35C/W. Fig. 31 shows mount-
ing methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be
reduced down to 15C/W.
No PW M
f
SW
= 3 0 kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
I
A
I
B
I
OUT
I
OUT
WAVE DRIVE
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W]
I
OUT
[A]
f
SW
= 50 k
Hz (slow decay)
f
SW
= 30 k
Hz (slow decay)
I
A
I
B
I
OUT
I
OUT
MICROSTEPPING
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
D
[W]
I
OUT
[A]
Test Conditions:
Supply Voltage = 24V
L6208
22/27
Figure 28. PowerSO36 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
Figure 29. PowerDIP24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
Figure 30. SO24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
Figure 31. Mounting the PowerSO Package.
13
18
23
28
33
38
43
1
2
3
4
5
6
7
8
9
10
1 1
1 2
13
W ith o ut G ro u nd La yer
W ith Gr o un d La yer
W ith Gr o un d La yer + 16 via
H o le s
s q . c m
C / W
On-Board Copper Area
39
40
41
42
43
44
45
46
47
48
49
1
2
3
4
5
6
7
8
9
10
11
12
C o p pe r Are a is o n Bo tto m
S id e
C o p pe r Are a is o n To p S i de
s q . cm
C / W
On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
1
2
3
4
5
6
7
8
9
10
11
12
C o pp er A re a is o n T op S id e
s q. cm
C / W
On-Board Copper Area
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
23/27
L6208
Figure 32. Typical Quiescent Current vs.
Supply Voltage
Figure 33. Normalized Typical Quiescent
Current vs. Switching Frequency
Figure 34. Typical Low-Side R
DS(ON)
vs. Supply
Voltage
Figure 35. Typical High-Side RDS(ON) vs.
Supply Voltage
Figure 36. Normalized R
DS(ON)
vs.Junction
Temperature (typical value)
Figure 37. Typical Drain-Source Diode Forward
ON Characteristic
4 .6
4 .8
5 .0
5 .2
5 .4
5 .6
0
10
2 0
3 0
40
5 0
6 0
Iq [m A ]
V
S
[V ]
f
sw
= 1kHz
T
j
= 25C
T
j
= 85C
T
j
= 125C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0
20
40
60
80
100
Iq / (Iq @ 1 kHz)
f
SW
[kHz]
0.276
0.280
0.284
0.288
0.292
0.296
0.300
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.336
0.340
0.344
0.348
0.352
0.356
0.360
0.364
0.368
0.372
0.376
0.380
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.8
1.0
1.2
1.4
1.6
1.8
0
20
40
60
80
100
120
140
R
DS(ON)
/ (R
DS(ON)
@ 25 C)
T j [C ]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
700
800
900
1000
1100
1200
1300
I
SD
[A]
V
SD
[mV]
T
j
= 25C
L6208
24/27
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.60
0.141
a1
0.10
0.30
0.004
0.012
a2
3.30
0.130
a3
0
0.10
0
0.004
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D (1)
15.80
16.00
0.622
0.630
D1
9.40
9.80
0.370
0.385
E
13.90
14.50
0.547
0.570
e
0.65
0.0256
e3
11.05
0.435
E1 (1)
10.90
11.10
0.429
0.437
E2
2.90
0.114
E3
5.80
6.20
0.228
0.244
E4
2.90
3.20
0.114
0.126
G
0
0.10
0
0.004
H
15.50
15.90
0.610
0.626
h
1.10
0.043
L
0.80
1.10
0.031
0.043
N
10
(max.)
S
8
(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
25/27
L6208
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.320
0.170
A1
0.380
0.015
A2
3.300
0.130
B
0.410
0.460
0.510
0.016
0.018
0.020
B1
1.400
1.520
1.650
0.055
0.060
0.065
c
0.200
0.250
0.300
0.008
0.010
0.012
D
31.62
31.75
31.88
1.245
1.250
1.255
E
7.620
8.260
0.300
0.325
e
2.54
0.100
E1
6.350
6.600
6.860
0.250
0.260
0.270
e1
7.620
0.300
L
3.180
3.430
0.125
0.135
M
0 min, 15 max.
Powerdip 24
A1
B
e
B1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
26/27
L6208
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D
(1)
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0;75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
(1) "D" dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
27/27
L6208