L6213
SOLENOID DRIVER + SWITCH MODE POWER SUPPLY
ADVANCE DATA
OPERATING SUPPLY VOLTAGE UP TO 46V
1A POWER SUPPLY (5V)
5A SOLENOID DRIVER
PRECISE ON CHIP REFERENCE VOLTAGE
DISCONTINUOUS
MODE -
FREQUENCY
VARIABLE
VERY HIGH EFFICIENCY
1
OUTPUT DMOS (SMPS)
INTERNAL CURRENT LIMIT (SMPS SEC-
TION)
EXTERNALLY PROGRAMMABLE SOLENOID
CURRENT RISING SLOPE
EXTERNALLY
PROGRAMMABLE
FIXED
HYSTERESIS CONTROL
OPTIMIZED DMOS R
DS ON
FOR HIGH SIDE
CHOPPING
DESCRIPTION
The L6213 is an IC containing a S.M.P.S. deliver-
ing 1A at a voltage of 5V and a section designed
to drive a solenoid with a current up to 5A.
The device is realized in BCD mixed technology,
which combines isolated DMOS power transistor
with CMOS and Bipolar circuits on the same chip.
The SMPS section can deliver 1A DC with an out-
put voltage of 5V, including current limiting, reset
and power fail for microprocessor and thermal
protection.
The solenoid driver section is designed for high
current applications like hammer driver in elec-
tronic typewriter.
The solenoid output section contains a high side and
a low side DMOS, which R
DS ON
are optimized for
high side chopping. The current rising slope is exter-
nally programmable through an external capacitor.
The level of hysteresis of the current can be
changed through an external resistor.
The device is supplied in Powerdip 16+2+2, and
use the four center pins to conduct heat to the
printed circuit.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
November 1991
APPLICATION CIRCUIT
Powerdip 16+2+2
MULTIPOWER BCD TECHNOLOGY
1/9
BLOCK DIAGRAM
L6213
2/9
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Supply Voltage
52
V
V
D
; V
OUT-UP
Output Negative Voltage DC
-1.3
V
V
D
Output Negative Voltage peak at t = 0.1
s f = 100KHz
-5V
V
V
OUT-DOWN
Output Positive Voltage DC
V
S
+ 1.3
V
Output Positive Voltage peak at t = 0.1
s f = 25KHz
V
S
+ 5
V
V
OUT-UP
Output Negative Voltage peak at t = 0.1
s f = 25KHz
-5
V
PFP
Input Voltage
25
V
V
O
, Enable
PIM
Input Voltage
7
V
Reset, PF
Output Voltage
20
V
CD, ISTP
Input Voltage
5.5
V
Out-Up
Out-Down
Output Current DC = 10% T
ON
= 3.5ms
5.5
A
T
stg
Storage Temperature
-50 to 150
C
THERMAL DATA
Symbol
Description
Value
Unit
R
th j-pins
R
th j-amb
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient
Max.
Max.
14
60
C/W
C/W
PIN CONNECTION (Top view)
L6213
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PIN DESCRIPTION
Nr.
Name
Description
1
Out-Up
Solenoid section upper DMOS output.
2
BSE
Solenoid section upper DMOS bootstrap. A capacitor connected between pin 2 and pin 1
ensures the efficient driving of the solenoid section upper DMOS.
3
ENABLE
Solenoid control input - TTL compatible.
4
+V
S1
Unregulated voltage input - Solenoid section.
5, 6
GND
Ground.
7
PF
Power fail output, the saturation of PF is guaranteed if VPS exceed 3V. PF is at logic 1 a
time T
1
after RESET reached the high level. PF came back to logic 0 when VPS goes
down under 18V. (see fig. 1)
8
PFP
Power fail programming. A resistor divider connected to VPS changes the Power fail
threshold levels.
9
CD
Capacitor delay. A capacitor connected to this pin determines the Reset signal delay time
t
d
.
10
V
S2
Unregulated voltage input - SMPS sections.
11
VD
Regulator output and diode voltage control.
12
BSA
SMPS section DMOS bootstrap. A capacitor connected between pin 12 and pin 11
ensures efficient driving of SMPS DMOS.
13
RESET
Reset output. The saturation of Reset is guaranteed if VPS exceeds 3V. The Reset output
reaches the logic level 1 a time delay (set by capacitor CD) after VPS has reached a
rising threshold voltage. Reset reaches 0 level when VPS goes down below folling
threshold.
14
V
out
Feed back input of the regulation loop.
15, 16
GND
Ground.
17
R
sense
Connection for solenoid sensing resistor.
18
PIM
Programming of solenoid current rising edge. An RC network connected to this pin
determines the slope of the solenoid current rising edge.
19
ISTP
Programming of solenoid current histeresys.
20
Out-Down
Solenoid section lower DMOS output.
ELECTRICAL CHARACTERISTICS (Refer to the application circuit, T
J
=25
C, I
out
Power Supply =
50mA, VPS from 12V to 46V; unless otherwise specified.
Pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
STEP-DOWN SECTION
10, 4
V
i
Supply Voltage
14
46
V
14
V
o
Output Voltage
I
O
= 0.05 to 1A
4.85
5.2
V
R
DS on
On State Drain Resistance
T
J
= 25
C; VPS = 15 to 46V
0.56
0.7
10
t
h on
Turn-on Threshold
VPS Rising Fig. 1
10
12
V
10
t
h off
Turn-off Threshold
VPS Falling Fig. 1
10
12
V
10
I
B
Input Bias Current
15
mA
11
I
lim
Static Current Limiting
2.2
3.4
A
2, 10
I
i
Total Input Current
ENABLE = 1, VPS = 46V,
I
load
= 0
13
mA
2, 10
I
i
Total Input Current
ENABLE = 1, VPS = 15V,
I
load
= 0
18
mA
11
t
dp
Protection Current Maximum
Delay Time
1
s
t
off
Minimum Power off State
VPS = 46V I
O
= 50mA
4.2
7.8
s
L6213
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ELECTRICAL CHARACTERISTICS (continued)
Pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
POWER FAIL
10
V
thR
Rising Threshold Voltage
PFP open
Fig. 1
19.5
20
23
V
10
V
th F
Falling Threshold Voltage
PFP open
Fig. 1
16.6
18.1
19.5
V
10
V
th
Threshold Hysteresis
PFP open
Fig. 1
0.5
V
8
I
PFI
Divided Internal Current
130
A
8
V
th-PFP
Rising Threshold Voltage
VPS = 24V
1.1
1.21
1.29
V
8
V
th-PFP
Falling Threshold Voltage
VPS = 24V
0.98
1.06
1.13
V
8
V
th -PFP
Threshold Hysteresis
VPS = 24V
30
mV
7
V
sat
Output PF Saturation
PF current = 2.5mA
VPS = 3 to 46V
0.4
V
7
I
leak
Output Leakage Current
VPS = 46V VPF = 20V
50
A
7
t1
Delay to Reset
RESET High to PF high
Delay Time (fig. 1)
0
1
s
7
t2
Noise Immunity
When VPS drops to 8V for a
time from 0 to t2, PF must be
at 1 logic level (fig. 2)
0
1
s
7
t3
Noise Immunity
When VPS drops to 17V for
a time greater than t3, PF
must be at 0 logic level (fig. 2)
4
s
RESET
9
I
d
Delay Source Current
V
D
= 0 to 4.1V
70
140
A
9
I
d
Delay Sink Current
VD = 4.3 to 2V
10
mA
13
V
sat
Output RESET Saturation
RESET Current = 2.5mA
VPS = 3 to 46V
0.4
V
13
I
leak
Output Leakage Current
VPS = 46V RD = 4 to 5V
V
RESET
= 20V
50
A
13
t4
Noise Immunity
When VPS drops to 10V for a
time greater than t4 RESET
must be at 0 logic level (fig. 1)
4
s
SOLENOID CONTROL SECTION
18
Vsat
Saturation Voltage
ENABLE = 1 I PIM = 5mA
0.2
V
18
I
leak
Leakage Current
PIM = 0.2 to 2.5V ENABLE = 0
+100
A
18
V
clamp
Clamp Voltage
1.9
2
2.1
V
17
Minimum Offset Threshold
PIM = GND V
sens
= 10mV
ENABLE = 0
lower MOS must be in conduction
17
MAximum Offset Voltage
PIM = GND V
se ns
= 50mV
ENABLE = 0
lower MOS must be open
17
V
sense
Static Voltage Limiting
Threshold
V
sens
going from 0 to 0.6V
PIM = 3V, the EMH DMOS
goes to high resistance state
when V
sens
is within: (see
Block Diagram)
0.475
0.5
0.525
V
17
Maximum Delay Time
1
s
t
p
Protection Time
2
4
s
EMH R
on
OnStateDrain toSource Resistance
T
j
= 25
C, VPS 15 to 46V
0.35
0.45
EML R
on
OnStateDrain to SourceResistance
Tj = 25
C, VPS 15 to 46V
0.28
0.4
17
V
sense
Vsense Hysteresis
IST = Open
IST = 0.75V
IST = 3V
35
15
80
50
25
100
65
35
120
mV
mV
mV
L6213
5/9
Figure 1: Power Fail and Reset Static Operation. (PFP open)
L6213
6/9
Figure 2: Power Fail and Reset Noise Immunity and Dynamic Operation.
L6213
7/9
POWERDIP20 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.85
1.40
0.033
0.055
b
0.50
0.020
b1
0.38
0.50
0.015
0.020
D
24.80
0.976
E
8.80
0.346
e
2.54
0.100
e3
22.86
0.900
F
7.10
0.280
I
5.10
0.201
L
3.30
0.130
Z
1.27
0.050
L6213
8/9
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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L6213
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