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Электронный компонент: L6221A

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L6221A L6221AD
L6221N
July 1998
QUAD DARLINGTON SWITCH
.
FOUR NON INVERTING INPUTS WITH
ENABLE
.
OUTPUT VOLTAGE UP TO 50 V
.
OUTPUT CURRENT UP TO 1.8 A
.
VERY LOW SATURATION VOLTAGE
.
TTL COMPATIBLE INPUTS
.
INTEGRAL FAST RECIRCULATION DIODES
DESCRIPTION
The L6221 monolithic quad darlington switch is de-
signed for high current, high voltage switching appli-
cations. Each of the four switches is controlled by a
logic input and all four are controlled by a common
enableinput.All inputsareTTL-compatiblefor direct
connection to logic circuits.
Eachswitch consists of an open-collectordarlington
transistor plus a fast diodefor switchingapplications
with inductive device loads. The emitters of the four
switches are commoned. Any number of inputsand
outputs of the same device may be paralleled.
Multiwatt 15
Powerdip 12 + 2 + 2
SO16+2+2
ORDERING NUMBERS:
L6221A (Powerdip)
L6221N (Multiwatt15)
L6221AD (SO16+2+2)
BLOCK DIAGRAM
1/15
PIN CONNECTIONS (top views)
L6221A (Powerdip)
L6221N (Multiwatt-15)
OUT4
CLAMPB
N.C.
OUT3
GND
OUT2
GND
N.C.
CLAMPA
IN2
N.C.
V
S
GND
GND
ENABLE
N.C.
IN3
IN4
1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
OUT1
IN1
D95IN231
L6221AD (SO16+2+2)
THERMAL DATA
Symbol
Parameter
SO20
Powerdip
Multiwatt15
Unit
R
th j-pins
R
th j-case
R
th j-amb
Thermal Resistance Junction-pins
Max.
Thermal Resistance Junction-case
Max.
Thermal Resistance Junction-ambient
Max.
17
80
14
80

3
35
C/W
C/W
C/W
L6221A - L6221AD - L6221N
2/15
PIN FUNCTIONS (see block diagram)
Name
Function
IN 1
Input to Driver 1
IN 2
Input to Driver 2
OUT 1
Output of Driver 1
OUT 2
Output of Driver 2
CLAMP A
Diode Clamp to Driver 1 and Driver 2
IN 3
Input to Driver 3
IN 4
Input to Driver 4
OUT 3
Output of Driver 3
OUT 4
Output of Driver 4
CLAMP B
Diode Clamp to Driver 3 and Driver 4
ENABLE
Enable Input to All Drivers
V
S
Logic Supply Voltage
GND
Common Ground
For each input : H = High level
L = Low level
TRUTH TABLE
Enable
Input
Power Out
H
H
L
H
L
X
ON
OFF
OFF
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
o
Output Voltage
50
V
V
s
Logic Supply Voltage
7
V
V
IN
, V
EN
Input Voltage, Enable Voltage
V
s
I
C
Continuous Collector Current (for each channel)
1.8
A
I
C
Collector Peak Current (repetitive, duty cycle = 10 % t
on
= 5 ms)
2.5
A
I
C
Collector Peak Current (non repetitive, t = 10
s)
3.2
A
T
op
Operating Temperature Range (junction)
40 to + 150
C
T
stg
Storage Temperature Range
55 to + 150
C
I
sub
Output Substrate Current
350
mA
P
tot
Total Power Dissipation
at T
pins
= 90
C
(powerdip)
at T
case
= 90
C
(multiwatt)
at T
case
= 90
C
(SO20)
at T
amb
= 70
C
(powerdip)
at T
amb
= 70
C
(multiwatt)
at T
amb
= 70
C
(SO20)
4.3
20
3.5
1
2.3
1
W
W
W
W
W
W
L6221A - L6221AD - L6221N
3/15
ELECTRICAL CHARACTERISTICS
Refer to the test circuit to Fig. 1 to Fig. 9 (V
S
= 5V, T
amb
= 25
o
C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min .
Typ . Max .
Unit
V
S
Logic Supply Voltage
4.5
5.5
V
I
s
Logic Supply Current
All Outputs ON, I
C
= 0.7A
All Outputs OFF
20
20
mA
mA
V
CE(sus)
Output Sustaining Voltage
V
IN
= V
IN
L, V
EN
= V
EN
H
I
C
= 100 mA
46
V
I
CEX
Output Leakage Current
V
CE
= 50V
V
IN
= V
IN
L, V
EN
= V
EN
H
1
mA
V
CE(sat)
Collector Emitter Saturation Voltage
(one input on ; all others inputs off.)
V
s
= 4.5V
V
IN
= V
IN
H, V
EN
= V
EN
H
I
C
= 0.6A
I
C
= 1A
I
C
= 1.8A
1
1.2
1.6
V
V
IN
L, V
EN
L
Input Low Voltage
0.8
V
I
IN
L, I
EN
L
Input Low Current
V
IN
= V
IN
L, V
EN
= V
EN
L
100
A
V
IN
L, V
EN
H
Input High Voltage
2.0
V
I
IN
H , I
EN
H
Input High Current
V
IN
= V
IN
H, V
EN
= V
EN
H
10
A
I
R
Clamp Diode Leakage Current
V
R
= 50 V, V
EN
= V
EN
H
V
IN
= V
IN
L
100
A
V
F
Clamp Diode Forward Voltage
I
F
= 1A
I
F
= 1.8A
1.6
2.0
V
V
t
d (on)
Turn on Delay Time
V
p
= 5V, R
L
= 10
2
s
t
d (off)
Turn off Delay Time
V
p
= 5V, R
L
= 10
5
s
I
s
Logic Supply Current Variation
V
IN
= 5V, V
EN
= 5V
I
out
= 300 mA for Each Channel
120
m A
L6221A - L6221AD - L6221N
4/15
TEST CIRCUITS
(X) = Referred to Multiwatt package
X = Referred to Powerdip package
Figure 1 : Logic supply current.
S
et
V
IN
= 4.5V, V
EN
= 0.8V, or V
IN
= 0.8V, V
EN
= 4.5V, for I
S
(all outputs off)
S
et
V
IN
= 2V, V
EN
= 2V, for I
S
(all outputs on)
Figure 2 : Output Sustaining Voltage.
Figure 3 : Output Leakage Current.
L6221A - L6221AD - L6221N
5/15
Figure 4 :
Collector-emitter Saturation
Voltage
Figure 5 :
Logic Input Characteristics
S
et
S
1
, S
2
open, V
IN
, V
EN
= 0.8V for I
IN
L, I
EN
L
S
et
S
1
, S
2
open, V
IN
, V
EN
= 2V for I
IN
H, I
EN
H
S
et
S
1
, S
2
close, V
IN
, V
EN
= 0.8V for V
IN
L, V
EN
L
S
et
S
1
, S
2
close, V
IN
, V
EN
= 2V for V
IN
H, V
EN
H
Figure 6 : Clamp Diode Leakage Current.
Figure 7 : Clamp Diode Forward Voltage.
L6221A - L6221AD - L6221N
6/15
Figure 8 : Switching Times Test Circuit.
Figure 9 : Switching TImes Waveforms.
Figure 10 : Allowed Peak Collector Current ver-
sus Duty Cycle for 1, 2, 3 or 4 Con-
temporary Working Outputs (L6221A)
Figure 11 : Allowed Peak Collector Current ver-
sus Duty Cycle for 1, 2, 3 or 4 Con-
temporary Working Outputs
(L6221N)
L6221A - L6221AD - L6221N
7/15
Figure 14 : Collector Saturation Voltage versus
Junction Temperature at IC = 1A
Figure 15 : Free-wheeling Diode Forward Voltage
versus Junction Temperature
at IF = 1A
Figure 16 : Saturation Voltage vs. Junc-
Figure 17 : Free-wheeling Diode Forward
Figure 12 : Collector Saturation Voltage versus
Collector Current
Figure 13 : Free-wheeling Diode Forward Voltage
versus Diode Current
L6221A - L6221AD - L6221N
8/15
Figure 19 : Driver for Solenoids up to 3A.
Some care must be taken to ensure that the collec-
tors are placed close together to avoid different cur-
rent partitioning at turn-off.
We suggest to put in parallel channel 1 and 4 and
channel 2 and 3 as shown in figure 19 for the similar
electrical characteristics of the logic section (turn-on
and turn-off delay time) and the power stages (col-
lector saturation voltage, free-wheeling diode for-
ward voltage).
APPLICATION INFORMATION
When inductive loads are driven by L6221A/N, a
zener diode in series with the integral free-wheeling
diodes increases the voltage across which energy
stored in the load is discharged and therefore
speeds the current decay (fig. 18).
For reliability it is suggestedthat the zener is chosen
so that V
p
+ V
z
< 35 V.
The reasons for this are two fold :
1) The zener voltage changes in temperature and
current.
2) The instantaneouspower must be limited to avoid
the reverse second breakdown.
Figure 18.
L6221A - L6221AD - L6221N
9/15
Figure 22 : Peak Collector Current versus Duty
Cycle for 1 or 2 Paralleled Outputs
Driven (L6221N)
Figure 21 : Peak Collector Current versus Duty
Cycle for 1 or 2 Paralleled Outputs
Driven (L6221A)
Figure 20 : Saturation Voltage versus Collector
Current
L6221A - L6221AD - L6221N
10/15
Figure 25 : Maximum Dissipable Power and Junc-
tion to Ambient Thermal Resistance
versus Side "
"
Figure 26 : Maximum Allowable Power Dissipa-
tion versus Ambient Temperature
Figure 24 : External Heatsink Mounting Example
Figure 23 : Example of P.C. Board Copper Area
Which is Used as Heatsink
MOUNTING INSTRUCTION
The R
th j-amb
of the L6221A can be reduced by sol-
deringthe GND pins to a suitablecopper area of the
printed circuit board (Fig. 23) or to an external
heatsink (Fig. 24).
The diagram of figure 25 shows the maximum dis-
sipable power P
tot
and the R
th j-amb
as a function of
the side "
" of two equal square copper areas hav-
ing a thickness of 35
(1.4 mils). During soldering
the pins temperature must not exceed 260
C and
the soldering time must not be longer than 12 sec-
onds.
The external heatsink or printed circuit copper area
must be connected to electrical ground.
L6221A - L6221AD - L6221N
11/15
POWERDIP 16 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.85
1.40
0.033
0.055
b
0.50
0.020
b1
0.38
0.50
0.015
0.020
D
20.0
0.787
E
8.80
0.346
e
2.54
0.100
e3
17.78
0.700
F
7.10
0.280
I
5.10
0.201
L
3.30
0.130
Z
1.27
0.050
L6221A - L6221AD - L6221N
12/15
MULTIWATT 15 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
5
0.197
B
2.65
0.104
C
1.6
0.063
D
1
0.039
E
0.49
0.55
0.019
0.022
F
0.66
0.75
0.026
0.030
G
1.02
1.27
1.52
0.040
0.050
0.060
G1
17.53
17.78
18.03
0.690
0.700
0.710
H1
19.6
0.772
H2
20.2
0.795
L
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.870
0.886
L2
17.65
18.1
0.695
0.713
L3
17.25
17.5
17.75
0.679
0.689
0.699
L4
10.3
10.7
10.9
0.406
0.421
0.429
L7
2.65
2.9
0.104
0.114
M
4.25
4.55
4.85
0.167
0.179
0.191
M1
4.63
5.08
5.53
0.182
0.200
0.218
S
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
L6221A - L6221AD - L6221N
13/15
1
10
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
SO20 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0 (min.)8 (max.)
L6221A - L6221AD - L6221N
14/15
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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L6221A - L6221AD - L6221N
15/15