1/24
L6258E
September 2004
1
FEATURES
ABLE TO DRIVE BOTH WINDINGS OF A
BIPOLAR STEPPER MOTOR OR TWO DC
MOTORS
OUTPUT CURRENT UP TO 1.2A EACH
WINDING
WIDE VOLTAGE RANGE: 12V TO 40V
FOUR QUADRANT CURRENT CONTROL,
IDEAL FOR MICROSTEPPING AND DC
MOTOR CONTROL
PRECISION PWM CONTROL
NO NEED FOR RECIRCULATION DIODES
TTL/CMOS COMPATIBLE INPUTS
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOW
2
DESCRIPTION
L6258E is a dual full bridge for motor control applica-
tions realized in BCD technology, with the capability
of driving both windings of a bipolar stepper motor or
bidirectionally control two DC motors.
L6258E and a few external components form a com-
plete control and drive circuit. It has high efficiency
phase shift chopping that allows a very low current
ripple at the lowest current control levels, and makes
this device ideal for steppers as well as for DC mo-
tors.The power stage is a dual DMOS full bridge ca-
pable of sustaining up to 40V, and includes the
diodes for current recirculation.The output current ca-
pability is 1.2A per winding in continuous mode, with
peak start-up current up to 1.5A. A thermal protection
circuitry disables the outputs if the chip temperature
exceeds the safe limits.
NOT FOR NEW DESIGN
PWM CONTROLLED - HIGH CURRENT
DMOS UNIVERSAL MOTOR DRIVER
Figure 2. Block Diagram
DAC
CHARGE
PUMP
V
R
(V
DD
/2)
VCP1
PH_1
I0_1
I1_1
I2_1
VREF1
TRIANGLE
GENERATOR
TRI_CAP
ERROR
AMP
+
-
V
R
+
-
+
-
C
C
POWER
BRIDGE
1
TRI_0
TRI_180
TRI_180
TRI_0
DAC
PH_2
I0_2
I1_2
I2_2
VREF1
ERROR
AMP
+
-
V
R
+
-
+
-
C
C
POWER
BRIDGE
2
TRI_0
TRI_180
THERMAL
PROT.
OUT1A
OUT1B
R
s
SENSE1A
VBOOT
DISABLE
VS
OUT2A
OUT2B
SENSE2A
R
s
VS
EA_IN2
EA_OUT2
GND
EA_IN1
EA_OUT1
VCP2
V
DD
(5V)
D96IN430D
VR GEN
INPUT
&
SENSE
AMP
C
P
C
FREF
C
BOOT
INPUT
&
SENSE
AMP
I3_1
I3_2
SENSE1B
SENSE2B
R
C1
R
1
1M
R
2
1M
R
C2
C
C2
C
C1
Rev. 7
Figure 1. Package
Table 1. Order Codes
Part Number
Package
L6258E
(Replaced by L6258EX)
PowerSO36
PowerSO36
L6258E
2/24
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection (Top view)
Symbol
Parameter
Value
Unit
V
s
Supply Voltage
45
V
V
DD
Logic Supply Voltage
7
V
V
ref1
/V
ref2
Reference Voltage
2.5
V
I
O
Output Current (peak)
1.5
A
I
O
Output Current (continuous)
1.2
A
V
in
Logic Input Voltage Range
-0.3 to 7
V
V
boot
Bootstrap Supply
60
V
V
boot
- V
s
Maximum Vgate applicable
15
V
T
j
Junction Temperature
150
C
T
stg
Storage Temperature Range
-55 to 150
C
PWR_GND
PH_2
EA_IN2
EA_OUT2
DISABLE
EA_OUT1
OUT1A
EA_IN1
PH_1
SENSE1
OUT1B
I3_1
VS
I2_1
I3_2
OUT2B
SENSE2
PWR_GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
PWR_GND
PWR_GND
D96IN432E
GND
TRI_CAP
V
DD
I0_1
VREF1
I1_1
9
8
7
28
29
30
VCP1
SIG_GND
10
27
OUT2A
VCP2
VBOOT
VREF2
I2_2
I0_2
14
12
11
23
25
26
VS
I1_2
13
24
3/24
L6258E
Table 3. Pins Function
Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.
Pin #
Name
Description
1, 36
PWR_GND
Ground connection (1). They also conduct heat from die to printed circuit copper.
2, 17
PH_1, PH_2
These TTL compatible logic inputs set the direction of current flow through the load. A
high level causes current to flow from OUTPUT A to OUTPUT B.
3
I
1_1
Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the
Vref voltage applied according to the thruth table of page 7
4
I
0_1
See pin 3
5
OUT1A
Bridge output connection (1)
6
DISABLE
Disables the bridges for additional safety during switching. When not connected the
bridges are enabled
7
TRI_cap
Triangular wave generation circuit capacitor. The value of this capacitor defines the output
switching frequency
8
V
DD
(5V)
Supply Voltage Input for logic circuitry
9
GND
Power Ground connection of the internal charge pump circuit
10
V
CP1
Charge pump oscillator output
11
V
CP2
Input for external charge pump capacitor
12
V
BOOT
Overvoltage input for driving of the upper DMOS
13, 31
V
S
Supply voltage input for output stage. They are shorted internally
14
OUT2A
Bridge output connection (2)
15
I
0_2
Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the
VRef voltage applied according to the truth table of page 7
16
I
1_2
See pin 15
18, 19
PWR_GND
Ground connection. They also conduct heat from die to printed circuit copper
20, 35
SENSE2,
SENSE1
Negative input of the transconductance input amplifier (2, 1)
21
OUT2B
Bridge output connection and positive input of the tranconductance (2)
22
I
3_2
See pin 15
23
I
2_2
See pin 15
24
EA_OUT_2
Error amplifier output (2)
25
EA_IN_2
Negative input of error amplifier (2)
26, 28
V
REF2
, V
REF1
Reference voltages for the internal DACs, determining the output current value. Output
current also depends on the logic inputs of the DAC and on the sensing resistor value
27
SIG_GND
Signal ground connection
29
EA_IN_1
Negative input of error amplifier (1)
30
EA_OUT_1
Error amplifier output (1)
32
I
2_1
See pin 3
33
I
3_1
See pin 3
34
OUT1B
Bridge output connection and positive input of the tranconductance (1)
L6258E
4/24
Figure 4. Thermal Characteristics
Conditions
Power Dissipated
(W)
T Ambient
(C)
Thermal J-A resistance
(C/W)
5.3
70
15
4.0
70
20
2.3
70
35
pad layout + ground layers + 16 via hol
PCB ref.: 4 LAYER cm 12 x 12
pad layout + ground layers
PCB ref.: 4 LAYER cm 12 x 12
pad layout + 6cm2 on board heat sink
PCB ref.: 2 LAYER cm 12 x 12
D02IN1370
0
0
2
4
6
8
15C/W
20C/W
35C/W
10
12
20
40
60
80
100
120
140
160
Ambient Temperature (C)
Power Dissipated (W)
D02IN1371
5/24
L6258E
Table 4. Electrical Characteristics (V
S
= 40V; V
DD
= 5V; T
j
= 25; unless otherwise specified.)
Note 1: This is true for all the logic inputs except the disable input.
(*) Chopping frequency is twice fosc value.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
12
40
V
V
DD
Logic Supply Voltage
4.75
5.25
V
V
BOOT
Storage Voltage
V
S
= 12 to 40V
V
S
+6
V
S
+12
V
V
Sense
Max Drop Across Sense Resistor
1.25
V
V
S(off)
Power off Reset
Off Threshold
6
7.2
V
V
DD(off)
Power off Reset
Off Threshold
3.3
4.1
V
I
S(on)
VS Quiescent Current
Both bridges ON, No Load
15
mA
I
S(off)
VS Quiescent Current
Both bridges OFF
7
mA
I
DD
VDD Operative Current
15
mA
T
SD-H
Shut Down Hysteresis
25
C
T
SD
Thermal shutdown
150
C
f
osc
Triangular Oscillator Frequency
(*)
C
FREF
= 1nF
12.5
15
18.5
KHz
TRANSISTORS
I
DSS
Leakage Current
OFF State
500
A
R
ds(on)
On Resistance
ON State
0.6
0.75
V
f
Flywheel diode Voltage
If =1.0A
1
1.4
V
CONTROL LOGIC
V
in(H)
lnput Voltage
All Inputs
2
V
DD
V
V
in(L)
Input Voltage
All Inputs
0
0.8
V
I
in
Input Current (Note 1)
0 < V
in
< 5V
-150
+10
A
I
dis
Disable Pin Input Current
-10
+150
A
V
ref1
/
ref2
Reference Voltage
operating
0
2.5
V
I
ref
V
ref
Terminal Input Current
V
ref
= 1.25
-2
5
A
FI =
V
ref
/V
sense
PWM Loop Transfer Ratio
2
V
FS
DAC Full Scale Precision
V
ref
= 2.5V I
0
/I
1
/I
2
/I
3
= L
1.23
1.34
V
V
offset
Current Loop Offset
V
ref
= 2.5V I
0
/I
1
/I
2
/I
3
= H
-30
+30
mV
DAC Factor Ratio
Normalized @ Full scale Value
-2
+2
%
SENSE AMPLIFIER
V
cm
lnput Common Mode Voltage
Range
-0.7
V
S
+0.7
V
I
inp
Input Bias
sense1/sense2
-200
0
A
ERROR AMPLIFIER
G
V
Open Loop Voltage Gain
70
dB
SR
Output Slew Rate
Open Loop
0.2
V/
s
GBW
Gain Bandwidth Product
400
kHz
L6258E
6/24
3
FUNCTIONAL DESCRIPTION
The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.
The current control is generated through a switch mode regulation.
With this system the direction and the amplitude of the load current are depending on the relation of phase and
duty cycle between the two outputs of the current control loop.
The L6258E power stage is composed by power DMOS in bridge configuration as it is shown in figure 5, where
the bridge outputs OUT_A and OUT_B are driven to V
s
with an high level at the inputs IN_A and IN_B while are
driven to ground with a low level at the same inputs .
The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same
phase and 50% of duty cycle.
In this case the outputs of the two half bridges are continuously switched between power supply (V
s
) and
ground, but keeping the differential voltage across the load equal to zero.
In figure 5A is shown the timing diagram of the two outputs and the load current for this working condition.
Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while
we consider negative the current flowing into load with a direction from OUT_B to OUT_A.
Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive pos-
itive current into the load.
In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge
formed by T1 and T4 when the output OUT_A is driven to V
s
and the output OUT_B is driven to ground, while
there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs
are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs
are connected to ground.
Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is high-
er than the current charging time constant during the period in which the current flows into the load through the
diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude
depending on the difference in duty cycle of the two driving signals.
In figure 5B is shown the timing diagram in the case of positive load current
On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the
IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two
outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is
driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions
of the previous case when both the outputs are driven to Vs or to ground.
So, in this case the load current will be negative with an average amplitude always depending by the difference
in duty cycle of the two driving signals.
In figure 5C is shown the timing diagram in the case of negative load current .
Figure 6 shows the device block diagram of the complete current control loop.
3.1 Reference Voltage
The voltage applied to VREF pin is the reference for the internal DAC and, together with the sense resistor val-
ue, defines the maximum current into the motor winding according to the following relation:
where R
s
= sense resistor value
I
MAX
0.5 V
REF
R
S
---------------------------
1
FI
-----
V
RE F
R
S
--------------
=
=
7/24
L6258E
Figure 5. Power Bridge Configuration
LOAD
OUT_A
OUT_B
T1
T3
T2
T4
IN_A
IN_B
V
S
0
OUTA
OUTB
Iload
0
OUTA
OUTB
Iload
0
OUTA
OUTB
Iload
Fig. 1A
Fig. 1B
Fig. 1C
D97IN624
L6258E
8/24
Figure 6. Current Control Loop Block Diagram
3.2 Input Logic (I
0
- I
1
- I
2
- I
3
)
The current level in the motor winding is selected according to this table:
Table 5.
I3
I2
I1
I0
Current level
% of IMAX
H
H
H
H
No Current
H
H
H
L
9.5
H
H
L
H
19.1
H
H
L
L
28.6
H
L
H
H
38.1
H
L
H
L
47.6
H
L
L
H
55.6
H
L
L
L
63.5
L
H
H
H
71.4
L
H
H
L
77.8
L
H
L
H
82.5
L
H
L
L
88.9
L
L
H
H
92.1
L
L
H
L
95.2
L
L
L
H
98.4
L
L
L
L
100
DAC
+
-
+
-
VDAC
ia
ic
Rc
Cc
V
R
+
-
ib
+
-
+
-
ERROR AMPL.
INPUT TRANSCONDUCTANCE
AMPL.
VS
VS
R
L
L
L
R
S
LOAD
OUTA
OUTB
VREF
I0
I1
I2
I3
PH
Gin=1/Ra
VSENSE
Gs=1/Rb
Tri_180
POWER AMPL.
SENSE TRANSCONDUCTANCE
AMPL.
D97IN625
Tri_0
9/24
L6258E
3.3 Phase Input ( PH )
The logic level applied to this input determines the direction of the current flowing in the winding of the motor.
High level on the phase input causes the motor current flowing from OUT_A to OUT_B through the load.
3.4 Triangular Generator
This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to generate the duty cycle
variation of the signals driving the output stage in bridge configuration.
The frequency of the triangular wave defines the switching frequency of the output, and can be adjusted by changing
the capacitor connected at TR1_CAP pin :
where : K = 1.5 x 10
-5
3.5 Charge Pump Circuit
To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on the Vboot pin. This
boostrap voltage is not needed for the low side power DMOS transistors because their sources terminals are
grounded. To produce this voltage a charge pump method is used. It is made by using two external capacitors;
one connected to the internal oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the
driving the gates of the high side DMOS. The value suggested for the capacitors are:
Table 6.
3.6 Current Control LOOP
The current control loop is a transconductance amplifier working in PWM mode.
The motor current is a function of the programmed DAC voltage.
To keep under control the output current, the current control modulates the duty cycle of the two outputs OUT_A
and OUT_B, and a sensing resistor Rs is connected in series with the motor winding in order to produce a volt-
age feedback compared with the programmed voltage of the DAC .
The duty cycle modulation of the two outputs is generated comparing the voltage at the outputs of the error am-
plifier, with the two triangular wave references .
In order to drive the output bridge with the duty cycle modulation explained before, the signals driving each out-
put ( OUTA & OUTB ) are generated by the use of the two comparators having as reference two triangular wave
signals Tri_0 and Tri_180 of the same amplitude, the same average value (in our case Vr), but with a 180 of
phase shift each other.
The two triangular wave references are respectively applied to the inverting input of the first comparator and to
the non inverting input of the second comparator .
The other two inputs of the comparators are connected together to the error amplifier output voltage resulting
by the difference between the programmed DAC. The reset of the comparison between the mentioned signals
is shown in fig. 7.
C
boot
Storage Capacitor
100
nF
C
P
PumpCapacitor
10
nF
F
ref
K
C
----
=
L6258E
10/24
Figure 7. Output comparator waveforms
In the case of V
DAC
equal to zero, the transconductance loop is balanced at the value of Vr, so the outputs of
the two comparators are signals having the same phase and 50% of duty cycle .
As we have already mentioned, in this situation, the two outputs OUT_A and OUT_B are simultaneously driven
from V
s
to ground ; and the differential voltage across the load in this case is zero and no current flows in the
motor winding.
With a positive differential voltage on V
DAC
(see Fig 6, the transconductance loop will be positively unbalanced
respected Vr.
In this case being the error amplifier output voltage greater than Vr, the output of the first comparator is a square
wave with a duty cycle higher than 50%, while the output of the second comparator is a square wave with a duty
cycle lower than 50%.
The variation in duty cycle obtained at the outputs of the two comparators is the same, but one is positive and
the other is negative with respect to the 50% level.
The two driving signals, generated in this case, drive the two outputs in such a way to have switched current
flowing from OUT_A through the motor winding to OUT_B.
With a negative differential voltage V
DAC
, the transconductance loop will be negatively unbalanced respected Vr.
In this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output
of the second comparator is a square wave with a duty cycle higher than 50%.
The variation in the duty cycle obtained at the outputs of the two comparators is always of the same.
The two driving signals, generated in this case, drive the the two outputs in order to have the switched current
flowing from OUT_B through the motor winding to OUT_A.
3.7 Current Control Loop Compensation
In order to have a flexible system able to drive motors with different electrical characteristics, the non inverting
input and the output of the error amplifier ( EA_OUT ) are available.
Connecting at these pins an external RC compensation network it is possible to adjust the gain and the band-
width of the current control loop.
Tri_0
Tri_180
Error Ampl.
Output
First Comp.
Output
Second Comp.
Output
11/24
L6258E
4
PWM CURRENT CONTROL LOOP
4.1 Open Loop Transfer Function Analysis
Block diagram : refer to Fig. 6.
Table 7. Application data:
these data refer to a typical application, and will be used as an example during the analysis of the stability of the
current control loop.
The block diagram shows the schematics of the L6258E internal current control loop working in PWM mode; the
current into the load is a function of the input control voltage V
DAC
, and the relation between the two variables
is given by the following formula:
I
load
R
S
G
S
= V
DAC
G
in
where:
V
DAC
is the control voltage defining the load current value
G
in
is the gain of the input transconductance amplifier ( 1/Ra )
G
s
is the gain of the sense transconductance amplifier ( 1/Rb )
R
s
is the resistor connected in series to the output to sense the load current
In this configuration the input voltage is compared with the feedback voltage coming from the sense resistor,
then the difference between this two signals is amplified by the error amplifier in order to have an error signal
controlling the duty cycle of the output stage keeping the load current under control.
It is clear that to have a good performance of the current control loop, the error amplifier must have an high DC
gain and a large bandwidth .
Gain and bandwidth must be chosen depending on many parameters of the application, like the characteristics
of the load, power supply etc..., and most important is the stability of the system that must always be guaran-
teed.
To have a very flexible system and to have the possibility to adapt the system to any application, the error am-
plifier must be compensated using an RC network connected between the output and the negative input of the
same.
For the evaluation of the stability of the system, we have to consider the open loop gain of the current control
loop:
V
S
= 24V
Gs transconductance gain = 1/Rb
L
L
= 12mH
Gin transconductance gain = 1/Ra
R
L
= 12
Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak)
R
S
= 0.33
R
a
= 40K
R
C
= to be calculated
R
b
= 20K
C
C
= to be calculated
V
r
= Internal reference equal to V
DD
/2 (Typ. 2.5V)
I
LOAD
R
S
1
R
b
-------
V
DAC
1
R
a
-------
=
I
LOAD
V
DAC
R
b
R
a
R
s
------------------
0.5
V
DAC
R
S
---------------
A
( )
=
=
L6258E
12/24
Aloop = ACerr ACpw ACload ACsense
where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus the attenuation of
the load block.
The same formula in dB can be written in this way:
Aloop
dB
= ACerr
dB
+ ACpw
dB
+ ACload
dB
+ ACsense
dB
So now we can start to analyse the dynamic characteristics of each single block, with particular attention to the
error amplifier.
4.2 Power Amplifier
The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output stage in full bridge
configuration.
The output duty cycle variation is given by the comparison between the voltage of the error amplifier and two
triangular wave references Tri_0 and Tri_180. Because all the current control loop is referred to the Vr refer-
ence, the result is that when the output voltage of the error amplifier is equal to the Vr voltage the two output
Out_A and Out_B have the same phase and duty cycle at 50%; increasing the output voltage of the error am-
plifier above the Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases
of the same percentage; on the contrary decreasing the voltage of the error amplifier below the Vr voltage, the
duty cycle of the Out_A decreases and the duty cycle of the Out_B increases of the same percentage.
The gain of this block is defined by the amplitude of the two triangular wave references; more precisely the gain
of the power amplifier block is a reversed proportion of the amplitude of the two references.
In fact a variation of the error amplifier output voltage produces a larger variation in duty cycle of the two outputs
Out_A and Out_B in case of low amplitude of the two triangular wave references.
The duty cycle has the max value of 100% when the input voltage is equal to the amplitude of the two triangular
references.
The transfer function of this block consist in the relation between the output duty cycle and the amplitude of the
triangular references.
Vout = 2 V
S
(0.5 - DutyCycle)
Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the transfer function of
this block is a linear constant gain without poles and zeros.
4.3 Load Attenuation
The load block is composed by the equivalent circuit of the motor winding (resistance and inductance) plus the
sense resistor.
We will considered the effect of the Bemf voltage of the motor in the next chapter.
The input of this block is the PWM voltage of the power amplifier and as output we have the voltage across the
sense resistor produced by the current flowing into the motor winding. The relation between the two variable is :
ACpw
dB
20
V
out
V
in
---------------
log
2 V
S
Triangular Amplitude
-------------------------------------------------------
=
=
ACpw
dB
10
2 24
1.6
--------------
log
29.5dB
=
=
V
sense
V
out
R
L
R
S
+
---------------------
R
S
=
13/24
L6258E
so the gain of this block is:
where:
R
L
= equivalent resistance of the motor winding
R
S
= sense resistor
Because of the inductance of the motor L
L
, the load has a pole at the frequency :
Before analysing the error amplifier block and the sense transconductance block, we have to do this consider-
ation :
Aloop
dB
= Ax
dB
+ Bx
dB
Ax|
dB
= ACpw|
dB
+ ACload|
dB
and
Bx|
dB
= ACerr|
dB
+ ACsense|
dB
this means that Ax|dB is the sum of the power amplifier and load blocks;
Ax|
dB
= (29,5) + (-31.4) = -1.9dB
The BODE analysis of the transfer function of Ax is:
Figure 8.
The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz.
It is clear now that (because of the negative gain of the Ax function), Bx function must have an high DC gain in
ACload
V
sense
v
out
------------------
R
S
R
L
R
S
+
---------------------
=
=
ACload
dB
20
R
S
R
L
R
S
+
---------------------
log
=
Aload
dB
20
0.33
12
0.33
+
------------------------
log
31.4dB
=
=
Fpole
1
2
L
L
R
L
R
S
+
---------------------
---------------------------------
=
Fpole
1
6.28
12 10
3
12
0.33
+
------------------------
-----------------------------------------
163Hz
=
=
L6258E
14/24
order to increment the total open loop gain increasing the bandwidth too.
4.4 Error Amplifier and Sense Amplifier
As explained before the gain of these two blocks is :
Bx
dB
= ACerr
dB
+ ACsense
dB
Being the voltage across the sense resistor the input of the Bx block and the error amplifier voltage the output
of the same, the voltage gain is given by :
Verr_out = -(ic Zc) so ic = -(Verr_out
)
because ib = icwe have:
Vsense
= -(Verr_out
)
In the case of no external RC network is used to compensate the error amplifier, the typical open loop transfer
function of the error plus the sense amplifier is something with a gain around 80dB and a unity gain bandwidth
at 400kHz. In this case the situation of the total transfer function Aloop, given by the sum of the Ax
dB
and Bx
dB
is :
Figure 9.
The BODE diagram shows together the error amplifier open loop transfer function, the Ax function and the re-
sultant total Aloop given by the following equation :
Aloop
dB
= AxdB + Bx
dB
The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem in this case is the
stability of the system; in fact the total Aloop cross the zero dB axis with a slope of -40dB/decade.
Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an high DC gain and
a large bandwidth. Aloop must have enough phase margin to guarantee the stability of the system.
A method to reach the stability of the system, using the RC network showed in the block diagram, is to cancel
the load pole with the zero given by the compensation of the error amplifier.
ib
Vsense Gs
Vsense
1
Rb
--------
=
=
1
Zc
-------
1
Rb
--------
1
Zc
-------
Bx
Verr_out
Vsense
------------------------
Zc
Rb
--------
=
=
15/24
L6258E
The transfer function of the Bx block with the compensation on the error amplifier is :
In this case the Bx block has a DC gain equal to the open loop and equal to zero at a frequency given by the
following formula:
In order to cancel the pole of the load, the zero of the Bx block must be located at the same frequency of 163Hz;
so now we have to find a compromise between the resistor and the capacitor of the compensation network.
Considering that the resistor value defines the gain of the Bx block at the zero frequency, it is clear that this
parameter will influence the total bandwidth of the system because, annulling the load pole with the error am-
plifier zero, the slope of the total transfer function is -20dB/decade.
So the resistor value must be chosen in order to have an error amplifier gain enough to guarantee a desired
total bandwidth .
In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the formula:
where: Rb = 20k
we have: Rc = 1.1M
Therefore we have the zero with a 163Hz the capacitor value :
Now we have to analyse how the new Aloop transfer function with a compensation network on the error amplifier
is.
The following bode diagram shows :
the Ax function showing the position of the load pole
the open loop transfer function of the Bx block
the transfer function of the Bx with the RC compensation network on the error amplifier
the total Aloop transfer function that is the sum of the Ax function plus the transfer function of the com-
pensated Bx block.
Bx
Zc
Rb
--------
Rc
j
1
2
f Cc
-------------------------
Rb
-----------------------------------------
=
=
Fzero
1
2
Rc Cc
-------------------------------
=
Bx_gain
@ zero freq.
20
Rc
Rb
--------
log
=
Cc
1
2
Fzero Rc
-----------------------------------------
1
6.28 163 1.1 10
6
-------------------------------------------------------
880pF
=
=
=
L6258E
16/24
Figure 10.
We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total Aloop cross a the
0dB axis with a slope of -20dB/decade, having in this way a stable system with an high gain at low frequency
and a bandwidth of around 8KHz.
To increase the bandwidth of the system, we should increase the gain of the Bx block, keeping the zero in the
same position. In this way the result is a shift of the total Aloop transfer function up to a greater value.
4.5 Effect of the Bemf of the stepper motor on the current control loop stability
In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to look at the load block :
Figure 11.
The schematic now shows the equivalent circuit of the stepper motor including a sine wave voltage generator
of the Bemf. The Bemf voltage of the motor is not constant, its value changes depending on the speed of the
motor.
Increasing the motor speed the Bemf voltage increases :
Bemf = Kt
where:
Kt is the motor constant
is the motor speed in radiant per second
OUT+
Bemf
R
L
L
L
OUT-
R
S
to Sense
Amplifier
17/24
L6258E
The formula defining the gain of the load considering the Bemf of the stepper motor becomes:
we can see that the Bemf influences only the gain of the load block and does not introduce any other additional
pole or zero, so from the stability point of view the effect of the Bemf of the motor is not critical because the
phase margin remains the same.
Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent variation of the
bandwidth of the system.
5
APPLICATION INFORMATION
A typical application circuit is shown in Fig.12.
Note: For avoid current spikes on falling edge of DISABLE a "DC feedback" would be added to the ERROR
Amplifier. (R1-R2 on Fig. 12).
5.1 Interference
Due to the fact that the circuit operates with switch mode current regulation, to reduce the effect of the wiring
inductance a good capacitor (100nF) can be placed on the board near the package, between the power supply
line (pin 13,31) and the power ground (pin 1,36,18,19) to absorb the small amount of inductive energy.
It should be noted that this capacitor is usually required in addition to an electrolytic capacitor, that has poor
performance at the high frequencies, always located near the package, between power supply voltage (pin
13,31) and power ground (pin 1,36,18,19), just to have a current recirculation path during the fast current decay
or during the phase change.
The range value of this capacitor is between few
F and 100
F, and it must be chosen depending on application
parameters like the motor inductance and load current amplitude.
A decoupling capacitor of 100nF is suggested also between the logic supply and ground.
The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to avoid coupled noise
on this signals. The suggestion is to put the components connected to this pins close to the L6258E, to surround
them with ground tracks and to keep as far as possible fast switching outputs of the device. Remember also an
1 Mohm resistor between EA_INx and EA_OUTx to avoid output current spike during supply startup/shutdown.
A non inductive resistor is the best way to implement the sensing. Whether this is not possible, some metal film
resistor of the same value can be paralleled.
The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should be connected di-
rectly on the sensing resistor Rs terminals, and the path lead between the Rs and the two sensing inputs should
be as short as possible.
ACload
Vsense
Vout
----------------------
V
S
Bemf
(
)
R
S
R
L
R
S
+
---------------------
V
S
-----------------------------------------------------------
=
=
Acload
V
S
Bemf
V
S
----------------------------
R
S
R
L
R
S
+
---------------------
=
ACload
dB
20
V
S
Bemf
V
S
----------------------------
R
S
R
L
R
S
+
---------------------
log
=
L6258E
18/24
Figure 12. Typical Application Circuit.
5.2 Motor Selection
Some stepper motor have such high core losses that they are not suitable for switch mode current regulation. Fur-
thermore, some stepper motors are not designed for continuous operating at maximum current. Since the circuit
can drive a constant current through the motor, its temperature might exceed, both at low and high speed operation.
5.3 Unused Inputs
Unused inputs should be connected to the proper voltage levels in order to get the highest noise immunity.
5.4 Notes on PCB Design
We recommend to observe the following layout rules to avoid application problems with ground and anomalous
recirculation current.
The by-pass capacitors for the power and logic supply must be kept as near as possible to the IC.
It's important to separate on the PCB board the logic and power grounds and the internal charge pump circuit
ground avoiding that ground traces of the logic signals cross the ground traces of the power signals.
Because the IC uses the board as a heat sink, the dissipating copper area must be sized in accordance with the
required value of R
thj-amb
.
STEPPER
MOTOR
M
12mH 10
0.33
0.33
21
20
14
35
34
5
OUT2B
SENSE2
OUT2A
SENSE1
OUT1B
OUT1A
PH1
2
I0_1
4
I1_1
3
I2_1
32
I3_1
33
PH2
17
I0_2
15
I1_2
16
I2_2
23
I3_2
22
DISABLE
6
10nF
100nF
1nF
TRI_CAP
7
VS
13,31
VBOOT
12
VCP2
11
VCP1
10
9
GND
1,36
18,19
PWR_GND
VS
27
SIG_GND
28
D97IN626E
VREF1
26
VREF2
29
EA_IN1
30
EA_OUT1
820pF
1M
25
EA_IN2
24
EA_OUT2
820pF
1M
VREF
8
V
DD
V
DD
(5V)
L6258
SOP36
PACKAGE
R2 1M
R1 1M
E
19/24
L6258E
6
OPERATION MODE TIME DIAGRAMS
Figure 13. Full step operation mode timing diagram (Phase - DAC input and Motor Current)
Ph2
FULL Step Vector
0
2
3
1
0
3
2
1
0
Position
DAC 2
Inputs
0
Motor drive
Current 2
0
Motor drive
Current 1
I3_2
I2_2
I1_2
I3_1
0
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
DAC 1
Inputs
Phase
2
Phase
1
I0_2
I2_1
I1_1
I0_1
0
3
2
1
Ph1
Ph2
Ph1
D97IN629A
95.2%
19.1%
95.2%
19.1%
I3
I2
I1
I0
Current level
% of I
MAX
0
0
0
0
100
0
0
0
1
98.4
0
0
1
0
95.2
0
0
1
1
92.1
0
1
0
0
88.9
0
1
0
1
82.5
0
1
1
0
77.8
0
1
1
1
71.4
1
0
0
0
63.5
1
0
0
1
55.6
1
0
1
0
47.6
1
0
1
1
38.1
1
1
0
0
28.6
1
1
0
1
19.1
1
1
1
0
9.5
1
1
1
1
No Current
L6258E
20/24
Figure 14. Half step operation mode timing diagram (Phase - DAC input and Motor Current)
Ph2
Half Step Vector
6
7
4
5
1
3
2
0
DAC 2
Inputs
Motor drive
Current 2
71.4%
100%
0
Motor drive
Current 1
I3_2
I2_2
I1_2
I3_1
0
71.4%
100%
-71.4%
-100%
-71.4%
-100%
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
DAC 1
Inputs
Phase 2
Phase 1
I0_2
I2_1
I1_1
I0_1
2
1
0
7
6
5
4
3
Ph1
Ph2
Ph1
D97IN627C
I3
I2
I1
I0
Current level%
of I
MAX
0
0
0
0
100
0
0
0
1
98.4
0
0
1
0
95.2
0
0
1
1
92.1
0
1
0
0
88.9
0
1
0
1
82.5
0
1
1
0
77.8
0
1
1
1
71.4
1
0
0
0
63.5
1
0
0
1
55.6
1
0
1
0
47.6
1
0
1
1
38.1
1
1
0
0
28.6
1
1
0
1
19.1
1
1
1
0
9.5
1
1
1
1
No Current
21/24
L6258E
Figure 15. 4 bit microstep operation mode timing diagram (Phase - DAC input and Motor Current)
Ph2
Micro Step Vector
32
24 28
20
16
12
8
4
0
Position
DAC 2
Inputs
0
Motor drive
Current 2
0
Motor drive
Current 1
I3_2
I2_2
I1_2
I3_1
0
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
0
5V
DAC 1
Inputs
Phase
2
Phase
1
I0_2
I2_1
I1_1
I0_1
16
8
0
56
48
40
32
24
Ph1
Ph2
Ph1
D97IN628A
60 64
56
52
48
44
40
36
100%
95.2%
82.5%
63.5%
47.6%
38.1%
0%
19.1%
I3
I2
I1
I0
Current level%
of I
MAX
0
0
0
0
100
0
0
0
1
98.4
0
0
1
0
95.2
0
0
1
1
92.1
0
1
0
0
88.9
0
1
0
1
82.5
0
1
1
0
77.8
0
1
1
1
71.4
1
0
0
0
63.5
1
0
0
1
55.6
1
0
1
0
47.6
1
0
1
1
38.1
1
1
0
0
28.6
1
1
0
1
19.1
1
1
1
0
9.5
1
1
1
1
No Current
L6258E
22/24
Figure 16. PowerSO36 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.25
3.5
0.128
0.138
A2
3.3
0.13
A4
0.8
1
0.031
0.039
A5
0.2
0.008
a1
0
0.075
0
0.003
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D
15.8
16
0.622
0.630
D1
9.4
9.8
0.37
0.38
D2
1
0.039
E
13.9
14.5
0.547
0.57
E1
10.9
11.1
0.429
0.437
E2
2.9
0.114
E3
5.8
6.2
0.228
0.244
E4
2.9
3.2
0.114
1.259
e
0.65
0.026
e3
11.05
0.435
G
0
0.075
0
0.003
H
15.5
15.9
0.61
0.625
h
1.1
0.043
L
0.8
1.1
0.031
0.043
N
10 (max)
s
8 (max)
Note: "D and E1" do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006")
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
0096119 B
23/24
L6258E
Table 8. Revision History
Date
Revision
Description of Changes
January 2004
5
First Issue in EDOCS DMS
May 2004
6
Restyling of the graphic form, changed all V
CC
with V
DD
;
delete TSD parameter in the Electrical characteristic on the page 5/24.
NOT FOR NEW DESIGN, it has been replaced by equivalent L6258EX.
September 2004
7
Changed on the page 5 the f
osc
parameter max. value from 17.5 to
18.5kHz
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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24/24
L6258E
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