1/14
L6382D5
January 2005
1
FEATURES
INTEGRATED HIGH-VOLTAGE START-UP
4 DRIVERS FOR PFC, HALF-BRIDGE & PRE-
HEATING MOSFETS
FULLY INTEGRATE POWER MANAGEMENT
FOR ALL OPERATING MODES
5V MICROCONTROLLER COMPATIBLE
INTERNAL TWO POINT Vcc REGULATOR
OVER-CURRENT PROTECTION WITH
DIGITAL OUTPUT SIGNAL
CROSS-CONDUCTION PROTECTION
(INTERLOCKING)
UNDER VOLTAGE LOCK OUT
INTEGRATED BOOTSTRAP DIODE
2
APPLICATIONS
DIMMABLE/NON-DIMMABLE BALLST
3
DESCRIPTION
Designed in High-voltage BCD Off-line technolo-
gy, the L6382D5 is provided with 4 inputs pin and
a high voltage start-up generator conceived for ap-
plications managed by a microcontroller. It allows
the designer to use the same ballast circuit for dif-
ferent lamp wattage/type by simply changing the
C software.
The digital input pins - able to receive signals up to
400KHz - are connected to level shifters that pro-
vide the control signals to their relevant drivers; in
particular the L6382D5 embeds one driver for the
PFC pre-regulator stage, two drivers for the ballast
POWER MANAGEMENT UNIT FOR MICROCONTROLLED
BALLAST
Figure 2. Block Diagram
S
R
Q
SHIFT
600V
LEVEL
5V
HSD
LSD
OCP
PFD
HED
BOOTSTRAP
S
R
Q
Q
Q
Q
Q
P UVLO
ON
L
O
G
I
C
5V
SUPPLY
>600V
"ON"
"OFF"
IC BIAS
TPR
PSW
HVSU
TPR
BOOT
HSG
OUT
LSG
CSO
CSI
HEG
PFG
PFI
HEI
LSI
HSI
Vcc
GND
REF
DIM
HIGH
VOLTAGE
START-UP
GENERATOR
Rev. 1
Figure 1. Package
Table 1. Order Codes
Part Number
Package
L6382D5
SO20 tube
L6382D5TR
SO20 in Tape & Reel
SO20
L6382D5
2/14
half-bridge stage (High Voltage, including also the bootstrap function) and the last one to provide supple-
mentary features like preheating of filaments supplied through isolated filaments in dimmable applications.
A precise reference voltage (+5V 1%) able to provide up to 30mA is available to supply the
C in
oper-
ating
mode. Instead, during
start-up
and
save
mode the current available at V
REF
is up to 10mA and it is
provided by the internal high voltage start-up generator.
The chip has been conceived with advanced power management logic to minimize power losses and in-
crease the application reliability.
In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode.
The L6382D5 integrates also a function that regulates the IC supply voltage (without the need of any ex-
ternal charge pump) and optimizes the current consumption.
Figure 3. Pin Connection (Top View)
Figure 4. Typical System Block Diagram
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PFI
LSI
HSI
HEI
PFG
N.C.
TPR
GND
LSG
VCC
VREF
CSI
CSO
HEG
N.C.
HVSU
N.C.
OUT
HSG
BOOT
TL
HV
START-UP
CHARGE
PUMP
REGULATOR
BOOTSTRAP
HB
DRIVER
PROTECTION
5V
SUPPLY
PFC
DRIVER
PFC
CIRCUIT
C
AC
MAINS
3/14
L6382D5
Table 2. Pin Functions
N.
Pin
Function
1
PFI
Digital input signal to control the PFC gate driver. This pin has to be connected to a 5V CMOS
compatible signal.
2
LSI
Digital input signal to control the half-bridge low side driver. This pin has to be connected to a
5V CMOS compatible signal.
3
HSI
Digital input signal to control the half-bridge high side driver. This pin has to be connected to a
5V CMOS compatible signal.
4
HEI
Digital input signal to control the HEG output. This pin has to be connected to a 5V CMOS
compatible signal.
5
PFG
PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor
connected between this pin and the power MOS gate can be used to reduce the peak current.
An internal 10K
resistor toward ground avoids spurious and undesired MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA
source and 250mA sink.
6
N.C.
Not connected
7
TPR
Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is
possible to implement a charge circuit for the Vcc.
8
GND
Chip ground. Current return for both the low-side gate-drive currents and the bias current of the
IC. All of the ground connections of the bias components should be tied to a track going to this
pin and kept separate from any pulsed current return.
9
LSG
Low Side Driver Output. This pin must be connected to the gate of the half-bridge low side
power MOSFET. A resistor connected between this pin and the power MOS gate can be used
to reduce the peak current.
An internal 20K
resistor toward ground avoids spurious and undesired MOSFET turn-on.
The totem pole output stage is able to drive power with a peak current of 120mA source and
120mA sink.
10
Vcc
Supply Voltage for the signal part of the IC and for the drivers.
11
BOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this
pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the
low-side gate-drive. This patented structure normally replaces the external diode.
12
HSG
High Side Driver Output. This pin must be connected to the gate of the half bridge high side
power MOSFET . A resistor connected between this pin and the power MOS gate can be used
to reduce the peak current.
An internal 20K
resistor toward OUT pin avoids spurious and undesired MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA
source and 120mA sink.
13
OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout
carefully the connection of this pin to avoid too large spikes below ground.
14
N.C.
Not connected
15
HVSU
High-voltage start-up. The current flowing into this pin charges the capacitor connected
between pin Vcc and GND to start up the IC. Whilst the chip is in save
mode, the generator is
cycled on-off between turn-on and save mode voltages. When the chip works in
operating
mode
the generator is shut down and it is re-enabled when the Vcc voltage falls below the
UVLO threshold. According to the required V
REF
pin current, this pin can be connected to the
rectified mains voltage either directly or through a resistor.
16
N.C.
High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and
comply with safety regulations (creepage distance) on the PCB.
17
HEG
Output for the HEI block; this driver can be used to drive the MOS employed in isolated
filaments preheating. An internal 20K
resistor toward ground avoids spurious and undesired
MOSFET turn-on.
L6382D5
4/14
Table 3. Absolute Maximum Ratings
(*) excluding
operating mode
Table 4. Thermal Data
N.
Pin
Function
18
CSO
Output of current sense comparator, compatible with 5V CMOS logic; during
operating
mode,
the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin
latches high.
19
CSI
Input of current sense comparator, it is enabled only during
operating mode
; when the pin
voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers
are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with
LGI=HGI=low simultaneously.
20
VREF
Voltage reference. During
operating
mode an internal generator provides an accurate voltage
reference that can be used to supply up to 30mA to an external circuit. A small film capacitor
(0.22
F min.), connected between this pin and GND is recommended to ensure the stability of
the generator and to prevent noise from affecting the reference.
Symbol
Pin
Parameter
Value
Unit
V
CC
10
IC supply voltage (I
CC
= 20mA)
Self-limited
V
HVSU
15
High voltage start-up generator voltage range
-0.3 to 600
V
V
BOOT
11
Floating supply voltage
-1 to V
HVSU
+V
CC
V
V
OUT
13
Floating ground voltage
-1 to 600
V
I
TPR(RMS)
6
Maximum TPR RMS current
200
mA
I
TPR(PK)
6
Maximum TPR peak current
600
mA
V
TPR
6
Maximum TPR voltage (*)
14
V
19
CSI input voltage
-0.3 to 7
V
1, 2, 3, 4
Logic input voltage
-0.3 to 7
V
9, 12, 17
Operating frequency
15 to 400
KHz
5
Operating frequency
15 to 600
KHz
Tstg
Storage Temperature
-40 to +150
C
Tj
Ambient Temperature operating range
-40 to +125
C
Symbol
Parameter
Value
Unit
R
th j-amb
Max. Thermal Resistance, Junction-to-ambient
120
C/W
Table 2. Pin Functions (continued)
5/14
L6382D5
Table 5. Electrical Characteristcs (T
j
= 25C, V
CC
=12V unless otherwise specified)
Symbol
Pin
Parameter
Test condition
min.
typ
max
UNIT
SUPPLY VOLTAGE
V
ccON
10
Turn-on voltage
13
14
15
V
V
ccOFF
10
Turn-off voltage
9.3
V
V
ccSM
10
Save mode voltage
12.75
13.8
14.85
V
VSMhys
10
Save mode hysteresys
0.115
V
V
REF(OFF)
10
Reference turn-off
7.65
V
IvccON
10
Start-up current
150
A
IvccSM
10
Save Mode current
consumption
190
A
(1)
150
230
A
Ivcc
10
Quiescent current in
operating mode
Vcc=13V; LGI=HGI=high; no
load on VREF.
2
mA
Vz
10
Internal Zener
TBD
V
HIGH VOLTAGE START-UP
IMSS
15
Maximum current
V
HVSU
> 50V
20
mA
15
Turn-on Voltage
I
HVSU
=5mA
TBD
V
ILSS
15
Leakage current off state
V
HVSU
= 600V
40
A
TWO POINT REGULATOR (TPR) PROTECTION
TPR
st
10
Vcc Protection level
Operating
mode
14.0
15.0
V
TPR
(ON)
10
Vcc Turn-on level
Operating
mode;
a
fter the first
falling edge on LSG
12.5
13.5
V
TPR
(OFF)
10
Vcc Turn-off level
Operating
mode; after the first
falling edge on LSG
12.45
13.48
V
7
Output voltage on state
I
TPR
= 200mA
2
V
7
Forward voltage drop
Diode
@ 600mA forward current.
2
V
7
Leakage current off state
V
TPR
= 13V
5
A
LSG, HEG & PFG DRIVERS
V
OH(LS
)
5, 9, 17
HIGH Output Voltage
ILSG = 10mA
V
CC
-0.5
V
V
OL(LS)
5, 9, 17
LOW Output Voltage
ILSG = 10mA
0.5
V
Sink Current Capability
LSG and PFG
120
mA
HEG
50
mA
L6382D5
6/14
Symbol
Pin
Parameter
Test condition
min.
typ
max
UNIT
Source Current
Capability
LSG
120
mA
HEG
70
PFG
250
T
RISE
5, 9, 17
Rise time
Cload = 1nF
TBD
ns
T
FALL
5, 9, 17
Fall time
Cload = 1nF
TBD
ns
T
DELAY
Propagation delay (input
to output)
LSG; high to low and low to
high
300
ns
HEG; high to low and low to
high
200
ns
PFG; high to low
250
ns
PFG; low to high
200
ns
R
B
Pull down Resistor
LSG
20
K
HEG
50
K
PFG
10
K
HSG DRIVER (VOLTAGES REFERRED TO OUT)
V
OH(HS)
12
HIGH Output Voltage
IHSG = 10 mA
V
CC
-0.5
V
V
OL(HS)
12
LOW Output Voltage
IHSG = 10 mA
0.5
V
12
Sink Current Capability
120
mA
12
Source Current
Capability
120
mA
T
RISE
12
Rise time
Cload = 1nF
TBD
ns
T
FALL
12
Fall time
Cload = 1nF
TBD
ns
T
DELAY
12
Propagation delay (LGI to
LSG)
high to low and low to high
300
ns
R
B
12
Pull down Resistor
to OUT
20
K
HIGH-SIDE FLOATING GATE-DRIVER SUPPLY
I
LKBOOT
11
V
BOOT
pin leakage
current
V
BOOT
= 580V
5
A
I
LKOUT
13
OUT pin leakage current
V
OUT
= 562V
5
A
R
DS(on)
Synchronous bootstrap
diode on-resistance
V
LVG
= HIGH
100
Forward Voltage Drop
at 10 mA forward current
1.9
2.4
V
Forward Current
at 5V forward voltage drop
25
mA
Table 5. Electrical Characteristcs (continued)
Table 5. Electrical Characteristcs (continued)
7/14
L6382D5
Notes: 1. Specification over the -40C to +125C junction temperature range are ensured by design, characterization and statistical corre-
lation.
Symbol
Pin
Parameter
Test condition
min.
typ
max
UNIT
VREF
V
REF
20
Reference voltage
15mA load.
4.9
5
5.1
V
15mA load, (1)
4.85
5.15
V
20
Load regulation
IRef = -3 to +30 mA
-20
2
mV
20
Voltage change
15mA load; Vcc = 9V to 15V
15
mV
20
V
REF
latched protection
3.2
V
20
V
REF
Clamp @3mA
V
CC
from 0 to V
CCON
during
start-up; Vcc from V
REF(OFF)
to
0 during shut-down; V
REF
<2V
1.2
V
I
REF
20
Current Drive Capability
-3
+30
mA
Save mode
-3
+10
mA
OVERCURRENT BUFFER STAGE
V
CSI
19
Comparator Level
Bandgap
0.52
0.54
0.56
V
I
CSI
19
Input Bias Current
500
nA
Propagation delay
CSO turn off to LSG low
200
ns
18
High output voltage
I
CSO
= 200
A
V
REF
-
0.5V
18
Low output voltage
I
CSO
= -150
A
0.5
V
DIM
Normal Mode Time Out
65
100
135
s
Vref enabling drivers
4.6
V
T
ED
Time enabling drivers
10
s
LOGIC INPUT
1 to 4
Low Level Logic Input
Voltage
1.3
V
1 to 4
High Level Logic Input
Voltage
3.7
V
LGI
Pull down resistor
100
K
Table 5. Electrical Characteristcs (continued)
L6382D5
8/14
4
APPLICATION INFORMATION
4.1 POWER MANAGEMENT
The L6382D5 has two stable states (
save
mode and
operating
mode) and two additional states that man-
age the Start-up and fault conditions: the Over Current Protection is a parallel asynchronous process en-
abled when in
operating
mode.
Following paragraphs will describe each mode and the condition necessary to shift between them.
Figure 5.
4.1.1 START-UP mode
With reference to the timing diagram of figure 6, when power is first applied to the converter, the voltage
on the bulk capacitor (Vin) builds up and the HV generator is enabled to operate drawing about 10mA.
This current, diminished by the IC consumption (less than 150A), charges the bypass capacitor connect-
ed between pin Vcc and ground and makes its voltage rise almost linearly.
During this phase, all IC's functions are disabled except for:
the current sinking circuit on V
REF
pin that maintains low the voltage by keeping disabled the
microcontroller connected to this pin;
the High-Voltage Start-Up (HVSU) that is ON (conductive) to charge the external capacitor on pin Vcc.
As the Vcc voltage reaches the start-up threshold (14V typ.) the chip starts
operating
and the HV generator
is switched off.
Summarizing:
the high-voltage start-up generator is active;
V
REF
is disabled with additional sinking circuit on pin V
REF
is enabled;
TPR is disabled;
OCP is disabled;
the drivers are disabled.
4.1.2 SAVE Mode
This mode is entered after the Vcc voltage reaches the turn-on threshold; the VREF is enabled in low cur-
rent source mode to supply the
C connected to it, whose wake-up required current must be less than
10mA: if no switching activity is detected at LGI input, the high voltage start-up generator cycles ON-OFF
keeping the Vcc voltage between VccON and VccSM.
SAVE MODE
OPERATING
MODE
SHUT DOWN
V
CC
>V
CC(ON)
V
CC
<V
REF(OFF)
V
REF
>4.6V
&
T
DE
>10
s
LGI low
for more
than 100
s
START-UP
V
CC
< V
CC(OFF)
or
V
REF
<3.2V
V
CC
<V
CC(ON)
V
CC
<V
REF(OFF)
9/14
L6382D5
Summarizing:
the high-voltage start-up generator is cycling;
V
REF
is enabled in low source current capability (I
REF
10mA);
TPR circuit is disabled;
OCP is disabled;
the drivers are disabled.
If the Vcc voltage falls below the V
REF(OFF)
threshold, the device enters the
start-up
mode.
4.1.3 OPERATING Mode
After 10
s in
save
mode and only if the votage at V
REF
is higher than 4.6V, on the falling edge on the HGI
input, the driver are enabled as well as all the IC's functions; this is the mode correspondent to the proper
lamp behaviour.
Summarizing:
HVSU is OFF
V
REF
is enabled in high source current mode (I
REF
< 30mA)
TPR circuit is enabled
OCP is enabled
the drivers are enabled
If there is no switching activity on LGI for more than 100
s, the IC returns in
save
mode.
4.1.4 Shut Down
This state permits to manage the fault conditions in
operating
mode and it is entered by the occurrence
on one of the following conditions:
1. Vcc<VccOff (Under Voltage fault on Supply),
2. V
REF
<3.2V (Under Voltage fault on V
REF
)
In this state the functions are:
The HVSU generator is ON
V
REF
is enabled in low source current mode (I
REF
< 10mA)
TPR is disabled
OCP is disabled
the drivers are disabled
In this state if Vcc reaches VccOn, the device enters the
save
mode otherwise, if Vcc<V
REF(OFF)
, also the
C is turned off and the device will be ready to execute the Start-up sequence.
Figure 6. Timing Sequences: TPR behavior (left) Start-up,
save
mode and
operating
mode (right).
TPR(ON)
TPR(OFF)
VREF
LGI
PSW
Vcc
VCCon
VccSM
VREF
LGI
HVSU
Vcc
VCCon
HGI
10
s
TPR Switching
VccOFF
LGI
OPERATING MODE
L6382D5
10/14
5
BLOCK DESCRIPTION
5.1 SUPPLY SECTION
PUVLO ( Power Under Voltage Lock Out): This block controls the power management of the
L6382D5 ensuring the right current consumption in each operating state, the correct V
REF
current
capability, the driver enabling and the high-voltage start-up generator switching.
During Start-up the device sinks the current necessary to charge the external capacitor on pin V
CC
from
the high voltage bus; in this state the other IC's functions are disabled and the current consumption of
the whole IC is less than 150
A.
When the voltage on V
CC
pin reaches VccON, the IC enters the
save
mode where the
PUVLO block
controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator.
HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc
supply voltage during START UP and SAVE MODE conditions and it reduces the power losses during
NORMAL MODE by switching OFF the MOS transistor. The transistor has a source current capability
of up to 30mA.
TPR (Two Point Regulator) & PWS: during
operating
mode, the TPR block controls the PSW switch
in order to regulate the IC supply voltage (VCC) to a value in the range between TPR(ON) and
TPR(OFF) by switching ON and OFF the PSW transistor.
Vcc > TPRst: the PSW is switched ON immediately;
TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of LGI;
Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI.
When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin
to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip with-
out adding any further external component. The diodes and the switch are designed to withstand a peak
current of at least 200mA
RMS
.
5.2 5V REFERENCE VOLTAGE
This block is used to supply the microcontroller; this source is able to supply 10mA in
save
mode and
30mA in normal mode; moreover, during
start-up
when V
REF
is not yet available, an additional circuit is
ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V.
The reference is available until Vcc is above V
REF(OFF)
; below that it turns off and the additional sinking
circuit is enabled again.
5.3 DRIVERS
LSD (
Low Side Driver
): it consists of a level shifter from 5V logic signal (LGI) to Vcc MOS driving level;
conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min).
HSD (
Level Shifter and High Side Driver
): it consists of a level shifter from 5V logic signal (HGI) to the
high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSD is
able to source 120mA from HSB to HSG (turn-on) and to sink 120mA to HSS (turn-off).
PFD (
Power Factor Driver
): it consists of a level shifter from 5V logic signal (PFI) to Vcc MOS driving
level: the driver is able to source 120mA from Vcc to PFG (turn-on) and to sink 250mA to GND (turn-
off); it is suitable to drive the MOS of the PFC pre-regulator stage.
HED (
Heat Driver
): it consists of a level shifter from 5V logic signal (HEI) to Vcc MOS driving level; the
driver is able to source 30mA from Vcc to HEG and to sink 75mA to GND and it is suitable for the
filament heating when they are supplied by independent winding.
Bootstrap Circuit
: it generates the supply voltage for the high side Driver (HSD). This circuit sources
current from Vcc to PIN HSB when LSG in ON. A patented integrated bootstrap section replaces an
11/14
L6382D5
external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage
to drive the high side power MOSFET. This function is achieved using a high voltage DMOS driver
which is driven synchronously with the low side external power MOSFET. For a safe operation, current
flow between BOOT pin and Vcc is always inhibited, even though ZVS operation may not be ensured.
5.4 INTERNAL LOGIC, OVER CURRENT PROTECTION (OCP) AND INTERLOCKING FUNCTION.
The DIM (
Digital Input Monitor
) block manages the input signals delivered to the drivers ensuring that they
are low during the described start-up procedure; the DIM block controls the L6382D5 behaviour during
both
save
and
operating
modes.
When the voltage on pin CSI overcomes the internal reference of 0.54V (typ.) the block latches the fault
condition: in this state the OCP block forces low both HSD and LSD signals while CSO will be forced high.
This condition remains latched until LSI and HSI are simultaneously low and CSI is below 0.54V.
This function is suitable to implement an over current protection or hard-switching detection by using an
external sense resistor.
As the voltage on pin CSI can go negative, the current must be limited below 2mA by external compo-
nents.
Another feature of the DIM block is the internal interlocking that avoids cross-conduction in the half-
bridge FET's: if by chance both HGI and LGI input's are brought high at the same time, then LSG and HSG
are forced low as long as this critical condition persists.
L6382D5
12/14
Figure 7. SO20 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D
(1)
12.60
13.00
0.496
0.512
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
(1) "D" dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
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Table 6. Revision History
Date
Revision
Description of Changes
January 2005
1
First Issue
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