1/16
L6562
June 2004
1
FEATURES
REALISED IN BCD TECHNOLOGY
TRANSITION-MODE CONTROL OF PFC PRE-
REGULATORS
PROPRIETARY MULTIPLIER DESIGN FOR
MINIMUM THD OF AC INPUT CURRENT
VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION
ULTRA-LOW (
70
A) START-UP CURRENT
LOW (
4 mA) QUIESCENT CURRENT
EXTENDED IC SUPPLY VOLTAGE RANGE
ON-CHIP FILTER ON CURRENT SENSE
DISABLE FUNCTION
1% (@ Tj = 25 C) INTERNAL REFERENCE
VOLTAGE
-600/+800mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN AND VOLTAGE CLAMP
DIP-8/SO-8 PACKAGES
1.1 APPLICATIONS
PFC PRE-REGULATORS FOR:
IEC61000-3-2 COMPLIANT SMPS (TV,
DESKTOP PC, MONITOR) UP TO 300W
HI-END AC-DC ADAPTER/CHARGER
ENTRY LEVEL SERVER & WEB SERVER
2
DESCRIPTION
The L6562 is a current-mode PFC controller oper-
ating in Transition Mode (TM). Pin-to-pin compati-
ble with the predecessor L6561, it offers improved
performance.
TRANSITION-MODE PFC CONTROLLER
Figure 2. Block Diagram
+
-
MULTIPLIER AND
THD OPTIMIZER
V
REF2
OVERVOLTAGE
DETECTION
VOLTAGE
REGULATOR
UVLO
INTERNAL
SUPPLY 7V
+
-
2.5V
R1
R2
R
S
Q
+
-
DRIVER
STARTER
+
-
ZERO CURRENT
DETECTOR
DISABLE
2.1 V
1.6 V
V
CC
8
1
2
3
4
ZCD
V
CC
INV
COMP
MULT
CS
GD
7
5
GND
6
25 V
40K
5pF
15 V
Starter
stop
REV. 6
Figure 1. Packages
Table 1. Order Codes
Part Number
Package
L6562N
DIP-8
L6562D
SO-8
L6562DTR
Tape & Reel
DIP-8
SO-8
L6562
2/16
2 DESCRIPTION (continued)
The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows
wide-range-mains operation with an extremely low THD, even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj =
25C) internal voltage reference.
The device features extremely low consumption (
70
A before start-up and <4 mA running) and includes
a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving
norms (Blue Angel, EnergyStar, Energy2000, etc.).
An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting
from load disconnection.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS-
FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solu-
tion for EN61000-3-2 compliant SMPS's up to 300W.
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection (Top view)
Table 3. Thermal Data
Symbol
Pin
Parameter
Value
Unit
V
CC
8
IC Supply voltage (Icc = 20 mA)
self-limited
V
IGD
7
Output Totem Pole Peak Current
0.8
A
---
1 to 4
Analog Inputs & Outputs
-0.3 to 8
V
IZCD
5
Zero Current Detector Max. Current
-50 (source)
10 (sink)
mA
P
tot
Power Dissipation @Tamb = 50C (DIP-8)
(SO-8)
1
0.65
W
T
j
Junction Temperature Operating range
-40 to 150
C
T
stg
Storage Temperature
-55 to 150
C
Symbol
Parameter
SO8
Minidip
Unit
R
th j-amb
Max. Thermal Resistance, Junction-to-ambient
150
100
C/W
ZCD
INV
COMP
MULT
CS
Vcc
GD
GND
1
2
3
4
8
7
6
5
3/16
L6562
Table 4. Pin Description
N
Pin
Function
1
INV
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
2
COMP
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
3
MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop.
4
CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped
reference, generated by the multiplier, to determine MOSFET's turn-off.
5
ZCD
Boost inductor's demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET's turn-on.
6
GND
Ground. Current return for both the signal part of the IC and the gate driver.
7
GD
Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high
Vcc.
8
Vcc
Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper
limit is extended to 22V min. to provide more headroom for supply voltage changes.
Table 5. Electrical Characteristics
(T
j
= -25 to 125C, V
CC
= 12, C
O
= 1 nF; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
V
CC
Operating range
After turn-on
10.3
22
V
V
CCon
Turn-on threshold
(1)
11
12
13
V
V
CCOff
Turn-off threshold
(1)
8.7
9.5
10.3
V
Hys
Hysteresis
2.2
2.8
V
V
Z
Zener Voltage
I
CC
= 20 mA
22
25
28
V
SUPPLY CURRENT
I
start-up
Start-up Current
Before turn-on, V
CC
=11V
40
70
A
I
q
Quiescent Current
After turn-on
2.5
3.75
mA
I
CC
Operating Supply Current
@ 70 kHz
3.5
5
mA
I
q
Quiescent Current
During OVP (either static or
dynamic) or V
ZCD
=150 mV
2.2
mA
MULTIPLIER INPUT
I
MULT
Input Bias Current
V
VFF
= 0 to 4 V
-1
A
V
MULT
Linear Operation Range
0 to 3
V
Output Max. Slope
V
MULT
= 0 to 0.5V
V
COMP
= Upper clamp
1.65
1.9
V/V
K
Gain
(2)
V
MULT
= 1 V, V
COMP
= 4 V
0.5
0.6
0.7
1/V
ERROR AMPLIFIER
V
INV
Voltage Feedback Input
Threshold
T
j
= 25 C
2.465
2.5
2.535
V
10.3 V < Vcc < 22 V
(1)
2.44
2.56
Line Regulation
Vcc = 10.3 V to 22V
2
5
mV
I
INV
Input Bias Current
V
INV
= 0 to 3 V
-1
A
V
CS
V
MUL T
---------------------
L6562
4/16
(1)
All parameters are in tracking
(2)
The multiplier output is given by:
(3)
Parameters guaranteed by design, functionality tested in production.
G
v
Voltage Gain
Open loop
60
80
dB
GB
Gain-Bandwidth Product
1
MHz
I
COMP
Source Current
V
COMP
= 4V, V
INV
= 2.4 V
-2
-3.5
-5
mA
Sink Current
V
COMP
= 4V, V
INV
= 2.6 V
2.5
4.5
mA
V
COMP
Upper Clamp Voltage
I
SOURCE
= 0.5 mA
5.3
5.7
6
V
Lower Clamp Voltage
I
SINK
= 0.5 mA
(1)
2.1
2.25
2.4
V
CURRENT SENSE COMPARATOR
I
CS
Input Bias Current
V
CS
= 0
-1
A
t
d(H-L)
Delay to Outpu
t
200
350
ns
V
CS clamp
Current sense reference clamp
V
COMP
= Upper clamp
1.6
1.7
1.8
V
V
CSoffset
Current sense offset
V
MULT
= 0
30
mV
V
MULT
= 2.5V
5
ZERO CURRENT DETECTOR
V
ZCDH
Upper Clamp Voltage
I
ZCD
= 2.5 mA
5.0
5.7
6.5
V
V
ZCDL
Lower Clamp Voltage
I
ZCD
= -2.5 mA
0.3
0.65
1
V
V
ZCDA
Arming Voltage
(positive-going edge)
(3)
2.1
V
V
ZCDT
Triggering Voltage
(negative-going edge)
(3)
1.6
V
I
ZCDb
Input Bias Current
V
ZCD
= 1 to 4.5 V
2
A
I
ZCDsrc
Source Current Capability
-2.5
-5.5
mA
I
ZCDsnk
Sink Current Capability
2.5
mA
V
ZCDdis
Disable threshold
150
200
250
mV
V
ZCDen
Restart threshold
350
mV
I
ZCDres
Restart Current after Disable
30
75
A
STARTER
t
START
Start Timer period
75
130
300
s
OUTPUT OVERVOLTAGE
I
OVP
Dynamic OVP triggering current
35
40
45
A
Hys
Hysteresis
(3)
30
A
Static OVP threshold
(1)
2.1
2.25
2.4
V
GATE DRIVER
V
OH
Dropout Voltage
I
GDsource
= 20 mA
2
2.6
I
GDsource
= 200 mA
2.5
3
V
V
OL
I
GDsink
= 200 mA
0.9
1.9
V
t
f
Voltage Fall Time
30
70
ns
t
r
Voltage Rise Time
40
80
ns
V
Oclamp
Output clamp voltage
I
GDsource
= 5mA; Vcc = 20V
10
12
15
V
UVLO saturation
V
CC
= 0 to V
CCon
, I
sink
=10mA
1.1
V
Table 5. Electrical Characteristics (continued)
(T
j
= -25 to 125C, V
CC
= 12, C
O
= 1 nF; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
cs
K V
MU LT
V
COM P
2.5
(
)
=
5/16
L6562
3
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 4. Supply current vs. Supply voltage
Figure 5. Start-up & UVLO vs. T
j
Figure 6. IC consumption vs. T
j
Figure 7. Vcc Zener voltage vs. T
j
Vcc(V)
0
0.005
0.01
0.05
0.1
0.5
1
5
10
I
CC
(mA)
0
5
10
15
20
Co = 1nF
f = 70 kHz
T
j
= 25C
25
Tj (C)
V
CC-ON
(V)
V
CC-OFF
(V)
-50
0
50
100
150
9
9.5
10
10.5
11
11.5
12
12.5
-50
0
50
100
150
0.02
0.05
0.1
0.2
0.5
1
2
5
10
Icc
[mA]
Operating
Quiescent
Disabled or
during OVP
Before start-up
Vcc = 12 V
Co = 1 nF
f = 70 kHz
Tj (C)
Tj (C)
Vcc
Z
(V)
-50
0
50
100
150
22
23
24
25
26
27
28
L6562
6/16
Figure 8. Feedback reference vs. T
j
Figure 9. OVP current vs. T
j
Figure 10. E/A output clamp levels vs. T
j
Figure 11. Delay-to-output vs. T
j
Figure 12. Multiplier characteristic
Figure 13. Multiplier gain vs. T
j
V
REF
(V)
-50
0
50
100
150
2.4
2.45
2.5
2.55
2.6
Vcc = 12 V
Tj (C)
I
OVP
(A)
-50
0
50
100
150
39
39.5
40
40.5
41
Vcc = 12 V
Tj (C)
Tj (C)
Vpin2
(V)
-50
0
50
100
150
2
3
4
5
6
Upper clamp
Lower clamp
Vcc = 12 V
Tj (C)
t
D(H-L)
(ns)
-50
0
50
100
150
0
100
200
300
400
500
Vcc = 12 V
V
MULT
(pin 3) (V)
V
COMP
(pin 2)
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
V
CS
(pin 4)
2.6
3.0
3.2
4
.5
5.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
(V)
4.0
2.8
upper voltage
clamp
3.5
Tj (C)
K
-50
0
50
100
150
0
0.2
0.4
0.6
0.8
1
Vcc = 12 V
V
COMP
=4 V
V
MULT
=1V
7/16
L6562
Figure 14. Vcs clamp vs. T
j
Figure 15. Start-up timer vs. T
j
Figure 16. ZCD clamp levels vs. T
j
Figure 17. ZCD source capability vs. T
j
Figure 18. Gate-drive output low saturation
Figure 19. Gate-drive output high saturation
Tj (C)
V
CSx
(V)
-50
0
50
100
150
1
1.2
1.4
1.6
1.8
2
Vcc = 12 V
V
COMP
= Upper clamp
Tj (C)
Tstart
(s)
-50
0
50
100
150
100
110
120
130
140
150
Vcc = 12 V
Tj (C)
V
ZCD
(V)
-50
0
50
100
150
0
1
2
3
4
5
6
7
Vcc = 12 V
I
ZCD
= 2.5 mA
Upper clamp
Lower clamp
Tj (C)
I
ZCDsrc
(mA)
-50
0
50
100
150
-8
-6
-4
-2
0
Vcc = 12 V
V
ZCD
= lower clamp
V
pin7
[V]
0
200
400
600
800
1,000
0
1
2
3
4
I
GD
[mA]
Tj = 25 C
Vcc = 11 V
SINK
0
100
200
300
400
500
600
700
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
V
pin7
[V]
I
GD
[mA]
Tj = 25 C
Vcc = 11 V
SOURCE
Vcc - 2.0
Vcc - 2.5
Vcc - 3.0
Vcc - 3.5
Vcc - 4.0
L6562
8/16
Figure 20. Gate-drive clamp vs. T
j
Figure 21. UVLO saturation vs. T
j
Tj (C)
Vpin7
clamp
(V)
-50
0
50
100
150
10
11
12
13
14
15
Vcc = 20 V
Tj (C)
-50
0
50
100
150
0.5
0.6
0.7
0.8
0.9
1
1.1
Vcc = 0 V
Vpin7
(V)
4
APPLICATION INFORMATION
4.1 Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator
close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo-
nents, the current through R1, I
R1
, equals that through R2, I
R2
. Considering that the non-inverting input of
the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:
.
If the output voltage experiences an abrupt change
Vo > 0 due to a load drop, the voltage at pin INV will
be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant to achieve high PF (this is why
Vo can be large). As a result,
the current through R2 will remain equal to 2.5/R2 but that through R1 will become:
.
The difference current
I
R1
=I'
R1
-I
R2
=I'
R1
-I
R1
=
Vo/R1 will flow through the compensation network and en-
ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about
37 A the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv-
ered to the output. As the current exceeds 40 A, the OVP is triggered (Dynamic OVP): the gate-drive is
forced low to switch off the external power transistor and the IC put in an idle state. This condition is main-
tained until the current falls below approximately 10 A, which re-enables the internal starter and allows
switching to restart. The output
Vo that is able to trigger the Dynamic OVP function is then:
.
An important advantage of this technique is that the OV level can be set independently of the regulated
output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another
advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on
Vo.
Since
Vo << Vo, the tolerance on the absolute value will be proportionally reduced.
Example: Vo = 400 V,
Vo = 40 V. Then: R1=40V/40
A=1M
; R2=1M
2.5/(400-2.5)=6.289k
. The tol-
erance on the OVP level due to the L6562 will be 400.12=4.8V, that is 1.2% of the regulated value.
I
R2
2.5
R2
--------
I
R1
Vo
2.5
R1
----------------------
=
=
=
I
'
R1
Vo
2.5
Vo
+
R1
----------------------------------------
=
Vo
R1 40 10
6
=
9/16
L6562
When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nom-
inal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier out-
put will saturate low; hence, when this is detected, the external power transistor is switched off and the IC
put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its lin-
ear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low.
When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge
of the Vcc capacitor and increase the hold-up capability of the IC supply system.
4.2 THD optimizer circuit
The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC
input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total
Harmonic Distortion) of the current is considerably reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively when the instan-
taneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after
the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be
reverse-biased and the input current flow to temporarily stop.
Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more
energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will
result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-
frequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key
waveforms of a standard TM PFC controller are compared to those of the L6562.
Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to
Imains
Vdrain
Imains
Vdrain
Input current
Input current
MOSFET's drain voltage
MOSFET's drain voltage
Rectified mains voltage
Rectified mains voltage
Input current
Input current
L6562
10/16
the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the
instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the
top of the sinusoid.
To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rec-
tifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a
conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre-
regulator - thus making the action of the optimizer circuit little effective.
Figure 23. Typical application circuit (250W, Wide-range mains)
Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic
NTC
2.5
8
3
BRIDGE
STBR606
R1
1.5 M
C1
1 F
400V
R3
22 k
C29
22 F
25V
FUSE
5A/250V
R4
180 k
D8
1N4150
D2
1N5248B
R14
100
C5 12 nF
R6
68 k
T
5
6
L6562
7
2
1
R7
10
MOS
STP12NM50
7 C/W heat sink
4
R11
750 k
C6
100 F
450V
Vo=400V
Po=250W
-
Vac
(85V to 265V)
R9
0.33
1W
R13
9.53 k
+
-
C4
100 nF
C2
10nF
D1
STTH5L06
R50 10 k
C3 2.2 F
R2
1.5 M
R5
180 k
R10
0.33
1W
R12
750 k
C23
680 nF
Boost Inductor Spec: EB0057-C (COILCRAFT)
D3 1N5406
NTC
2.5
8
3
BRIDGE
DF06M
R1
750 k
C1
0.47 F
400V
R3
10 k
C29
22 F
25V
FUSE
4A/250V
R4
180 k
D8
1N4150
D2
1N5248B
R14
100
C5 12 nF
R6
68 k
T
5
6
L6562
7
2
1
R7
33
MOS
STP8NM50
4
R11
750 k
C6
47 F
450V
Vo=400V
Po=80W
-
Vac
(85V to 265V)
R9
0.82
0.6 W
R13
9.53 k
+
-
C4
100 nF
C2
10nF
D1
STTH1L06
R50 12 k
C3 680 nF
R2
750 k
R5
180 k
R10
0.82
0.6 W
R12
750 k
C23
330 nF
Boost Inductor Spec (ITACOIL E2543/E)
E25x13x7 core, 3C85 ferrite
1.5 mm gap for 0.7 mH primary inductance
Primary: 105 turns 20x0.1 mm
Secondary: 11 turns 0.1 mm
11/16
L6562
Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)
Table 6. EVAL6562N: Evaluation results at full load
Table 7. EVAL6562N: Evaluation results at half load
Vin (V
AC
)
Pin (W)
Vo (V
DC
)
Vo(V
pk-pk
)
Po (W)
(%)
PF
THD (%)
85
86.4
394.79
12.8
80.16
92.8
0.998
3.6
110
84.6
394.86
12.8
80.20
94.8
0.996
4.2
135
83.8
394.86
12.8
80.20
95.7
0.991
4.9
175
83.2
394.87
15.5
80.20
96.4
0.981
6.5
220
82.9
394.87
15.7
80.20
96.7
0.956
7.8
265
82.7
394.87
15.9
80.20
97.0
0.915
9.2
Note: measurements done with the line filter shown in figure 23
Vin (V
AC
)
Pin (W)
Vo (V
DC
)
Vo(V
pk-pk
)
Po (W)
(%)
PF
THD (%)
85
42.8
394.86
6.6
40.20
93.9
0.994
5.5
110
42.5
394.90
6.6
40.20
94.6
0.985
6.2
135
42.5
394.91
6.7
40.20
94.6
0.967
7.1
175
42.5
394.93
8.0
40.19
94.6
0.939
8.3
220
42.6
394.94
8.2
40.19
94.3
0.869
9.8
265
42.6
394.94
8.3
40.19
94.3
0.776
11.4
Note: measurements done with the line filter shown in figure 23
L6562
12/16
Table 8. EVAL6562N: No-load measurements
Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation
Vin (V
AC
)
Pin (W)
Vo (V
DC
)
Vo(V
pk-pk
)
Po (W)
85
0.4
396.77
0.45
0
110
0.3
396.82
0.55
0
135
0.3
396.83
0.60
0
175
(*)
0.4
396.90
1.00
0
220
(*)
0.4
396.95
1.40
0
265
(*)
0.5
396.98
1.65
0
(*)
Vcc = 12V supplied externally
to the AC
source
B82732
47 mH, 1.3A
EPCOS
B81133
470 nF, X2
EPCOS
to
EVAL6562N
B81133
680 nF, X2
EPCOS
13/16
L6562
Figure 27. DIP-8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.32
0.131
a1
0.51
0.020
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
D
10.92
0.430
E
7.95
9.75
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
3.18
3.81
0.125
0.150
Z
1.52
0.060
DIP-8
L6562
14/16
Figure 28. SO-8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
(1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
Note:
(1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
15/16
L6562
Table 9. Revision History
Date
Revision
Description of Changes
January 2004
5
First Issue
June 2004
6
Modified the Style-look in compliance with the "Corporate Technical
Publications Design Guide".
Changed input of the power amplifier connected to Multiplier (Fig. 2).
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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L6562
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