1/29

L6610

April 2002

OV/UV DETECTION FOR 3.3V, ±5V, ±12V
RAILS AND 5V (OR 3.3V) AUX. VOLTAGE

OC DETECTION ON 12V AND 5V (OR 3.3V)
RAILS

AC MAINS UV (BROWNOUT) DETECTION
WITH HYSTERESIS

ON-LINE DIGITAL TRIMMING FOR 5V/12V,
3.3V, 5V (OR 3.3V) AUX. FEEDBACK
REFERENCES AND AC MAINS UV.

DIGITALLY SELECTABLE OPTIONS

ERROR AMPLIFIERS FOR 5V/12V RAILS
(MAIN SUPPLY), 3V3 POST-REGULATOR
(MAG_AMP OR LINEAR) AND AUXILIARY
SUPPLY.

MAIN SUPPLY ON/OFF CONTROL AND
POWER GOOD SIGNAL

50mA CROWBAR DRIVE FOR AUXILIARY
OUTPUT OVP.

OPEN GROUND PROTECTION

8ms DIGITAL SOFT START

64 ms UV/OC BLANKING AT START-UP

APPLICATIONS

SWITCHING POWER SUPPLIES FOR
DESKTOP PC'S, SERVERS AND WEB
SERVERS

SUPERVISOR FOR DISTRIBUTED POWER

SDIP24

SO24

ORDERING NUMBERS:

L6610N

L6610D
L6610DTR(T & Reel)

DIGITALLY PROGRAMMABLE SECONDARY

HOUSEKEEPING CONTROLLER

TYPICAL APPLICATION CIRCUIT

+5Vaux

WIDE RANGE

MAINS

+5V

COM

+3.3V

+12V

-5V

MAIN

CONTROL

AUXILIARY

CONTROL

VDD

12V

Cout

Gnd

MFault

Aout

3V3

-5V

L6610

-12V

-12V

Dmon

Bout

BCD TECHNOLOGY

6610

2/29

BL
O

K D

I
AG

+3
V

12V

Vd
d

Logic and Programmable Trimming

Pr
o

Gn
d

Ci
n

out

Dmon

Vd
d

2.50V

(
B

)

unc

Vd
d

Re
s

1.25V

(
A

)

2.50V

(
A

)

2.50V

(
B

)

Deboun

75ms

2.50V

(
C

)

10mA

Di
s

Gn
d

Bo
ut

out

5V
/
3

i
s

So
f
t
St
a

r
t

2.50V

(
A

)

V
+

12V

1.25V

(
B

)

50mV

5V
/
3

Di
s

2.50V

(
B

)

120mV

Dfaul

-
O

N / Cl

oc
k

Vr
e

-O
K

/ Data

Mfaul

-5

-1

12V

+5
V

12V

i
s

+3
V

50uA

Vd
d

r
o

r
a

i
ng i

nput

-
1

U
V

3V
3 +/-5

Vd
d

2.50V

(
B

)

2.50V

(
C

)

1.25V

(
A

)

1.25V

(
B

)

3/29

L6610

DESCRIPTION
The L6610 is a control and housekeeping IC developed in BCD technology; it is intended for acting at the sec-
ondary side of desktop PC's or server's switching power supplies, in presence of standard voltage rails (+3.3V,
±5V, ±12V) generated by a main converter and of a supply line generated by an auxiliary converter. The typical
application circuit is showed on the front page.
The Housekeeping's main function is to control and monitor the voltages generated by both the main and the
auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation
and, upon detection of an undervoltage (UV), overvoltage (OV) or overcurrent (OC) condition, reports such fault
and takes proper action to protect the system.
However, the peculiar feature of this IC is its digital programming capability that enables an accurate trimming
of the output voltage rails during production test via software, without any use of external discrete trimming com-
ponents or need for manual intervention on the PSU. It is also possible to program some of the monitoring func-
tions and select how UV and OC conditions are handled in the main converter: whether latched-mode (the
information is latched and released only by forcing the restart of the IC) or bouncing-mode (an attempt is made
to automatically restart the converter after 1 second wait).
A key feature of this IC is its contribution to a very low external component count. Besides the extensive use of
onboard programmable switches, which prevents the need for external trimming components, the IC embeds
reference voltages, error amplifiers and most of the housekeeping circuitry normally required.

PIN CONNECTION (top view)

PIN DESCRIPTION

Pin #

Name

Description

MFAULT

Main converter on/off control. This pin is a 10mA current sink used for driving an opto-isolator. It
is normally low when PS-ON (#15) is pulled low. If a fault is detected or PS-ON goes high, this
pin goes high too. To allow power up, the functions are digitally blanked out for a period (UVB
function) and MFAULT (#1) stays low. There is no delay for the OV protection function.

Binv

Inverting input to the error amplifier for the 3V3 post-regulator (either mag-amp or linear). The
non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed.

Bout

Output of the 3V3 error amplifier. It typically drives either a PNP transistor that sets the mag-amp
core or the pass element of a linear regulator. Also node for error amplifier compensation. The
maximum positive level of this output is clamped at about 3.5V to improve response time. Large
signal slew rate is limited to reduce noise sensitivity.

MFAULT

Binv

Bout

12V

3V3

-12V

VREF

PS-ON

PW-OK
ACsns

Vdd

DFAULT

Dmon

Cout

Aout

Ainv

GND

PROG

Cinv

12Visns

5V/3V3isns

GND

-5V

Binv

Bout

12V

3V3

-12V

VREF

PS-ON

PW-OK
ACsns

Vdd

DFAULT

Dmon

Cout

Aout

Ainv

GND

PROG

Cinv

12Visns

5V/3V3isns

GND

-5V

L6610

4/29

Aout

Output of the error amplifier for the main converter. This pin typically drives an optocoupler and is
also used for compensation along with Ainv (pin #5).

Ainv

Main loop error amplifier inverting input. The non-inverting input is connected to an internal 2.5V
reference that can be digitally trimmed. A high impedance internal divider from +12V and +5V
UV/OV sense pins (#23, #24) eliminates the need for external divider in most applications. The
pin is used for error amplifier compensation.

12Visns

Input pin for 12V current sense. Together with the 12V OV/UV sense pin (#24), this pin measures
the voltage across a current sense resistor in series with the output. If the load current exceeds a
preset threshold, MFAULT (#1) will go high. Depending on the mode set, MFAULT will be latched
off or pulled low again after about 1 second to allow autorecovery. To disable this function the pin
may be left open, shorted to ground or shorted to the 12V UV/OV pin.

5Visns/

3V3isns

Input pin for 5V or 3V3 current sense. Together with the OV/UV sense pin (#23 or #22), this pin
measures the voltage across a current sense resistor in series with the output. If the load current
exceeds a preset threshold, MFAULT (#1) will go high. Depending on the mode set, MFAULT will
be latched off or pulled low again after about 1 second to allow autorecovery. To disable this
function the pin may be left open, shorted to ground or shorted to the 5V UV/OV pin.

Cout

Auxiliary loop optocoupler drive. Also node for error amp compensation. Large signal slew rate is
limited to reduce sensitivity to switching noise.

Cinv

Inverting input for Auxiliary error amplifier. The non-inverting input is connected to an internal
1.25V reference that can be digitally trimmed.

Dmon

Dual or Auxiliary UV/OV monitor, Dmon is programmable to monitor 3V3 or 5V. To allow a correct
power up, the UV function on this pin is blanked out during initial start-up. There is no delay for
the OV function.

DFAULT

Dual or Auxiliary fault protection. When Dmon (#10) recognizes an over voltage, DFAULT and
MFAULT (#1) go high. DFAULT is capable of sourcing up to 50mA. Possible applications are a
crowbar across the Auxiliary output or an opto-coupled fault signal to the primary side.

Vdd

Positive input supply voltage. Vdd is normally supplied from the Auxiliary power supply output
voltage. If Vdd-UVL detects a sustained under voltage, PW-OK (#14) will be pulled low and
sending MFAULT (#1) high will disable the main converter.

ACsns

Analog of bulk voltage for AC fail warning. The usual source of this analog pin is one of the
secondary windings of the main transformer. Hysteresis is provided through a trimmable 50

current sink on this pin that is activated as the voltage at the pin falls below the internal reference
(2.5V).

PW-OK

/Data

Power good signal for the Main converter. When asserted high, this pin indicates that the
voltages monitored are above their UV limits. There will be typically 250ms delay from the Main
outputs becoming good and PW-OK being asserted. This is nominally an open drain signal. To
improve robustness, this output has a limited current sink capability. In programming mode, this
pin is used for data input; then the absolute maximum rating will be Vdd+0.5V.

PS-ON /

Clock

Control pin to enable the Main converter. This pin has debouncing logic. A recognized high value
on this pin will cause PW-OK (#14) to go immediately low and, after a delay of 2.5ms, to shut
down the main PWM by allowing MFAULT (#1) to go high. During normal operation (or if not
used) this pin has to be connected to a voltage lower than 0.8V. In programming mode, this pin
will be used to clock serial data into the chip.

VREF

2.5V reference for external applications. This is a buffered pin. Shorting this pin to ground or to
Vdd (#12) will not affect integrity of control or monitor references. An external capacitor (max.
100nF) is required whenever the pin is loaded (up to 5 mA), otherwise it can be left floating.

PIN DESCRIPTION (continued)

Pin #

Name

Description

5/29

L6610

-12V

-12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #16), the function
will be disabled.

-5V

-5V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #16), the function will
be disabled.

GND

Ground pin. The connection integrity of this pin is constantly monitored and in case of either a
bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#11) will be forced high
switching off the supply.

GND

Ground pin. See above.

PROG

The chip has 2 operating modes, depending on PROG input pin biasing:

normal mod

e: PROG should be floating or shorted to ground;

programming mod

e: forcing PROG high (+5V), the chip enters programming mode. PW_OK

(#14) and PS_ON (#15) pins are disconnected from their normal functionality and they become
inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode al-
lows selecting some options and adjusting some setpoints;

3V3

3V3 UV/OV monitor. It uses a separate reference to the feedback reference.

Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference
separate from that used for feedback. This pin connects the 5V part of the Main error amplifier
feedback divider.

12V

Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a
reference separate from that used for feedback. This pin connects the 12V part of the Main error
amplifier feedback divider.

FUNCTION DESCRIPTION

Name

Description

OVP

Whenever one of the Main output voltages is detected going above its own OVP threshold, this
function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON
(#15) switch or by reducing Vdd (#12) below the UV threshold.

UVP

Whenever one of the Main output voltages is detected going under its own UVP threshold, this
function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched.
Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#13) is
low due to a brownout condition, UVP is disabled.

OCP

Whenever either the 5V (or 3V3, digitally selectable) or the 12V output experiences an
overcurrent condition, the OCP function will force MFAULT (#1) high. If latch mode has been
selected, this condition will be latched otherwise an attempt is made to restart the supply after a
wait of 1 second.

UVB

Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits
must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the
auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts
as the ACsns pin detects a valid input voltage for the converter.

PW-OK delay

PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV
threshold the PW-OK pin (#14) will be kept low for additional 250ms (typ.) to make sure all the
outputs are settled.

OFF delay

Power-off delay. As soon as PS-ON (#15) pin is recognized high, indicating an imminent turn-off
condition, PW-OK (#14) pin will go low immediately . The converter will be turned off after a
delay of 2.5ms.

PIN DESCRIPTION (continued)

Pin #

Name

Description

L6610

6/29

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

(*) mounted on board

Debounce

The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored
inputs have digital filtering/debounce logic on board for high noise immunity.

AC-hysteresis

AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#13) to avoid
undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the
voltage ripple across the bulk capacitor.

Vdd-OVP

Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#11)
are latched high.

Vdd-UVL

To prevent false signals of any of IC's output pins, an under voltage lock-out circuit monitors Vdd
and keeps all IC's output at their default OFF level until Vdd reaches a sufficient minimum
voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and
volatile programming memory cleared.

Dual-OVP

Dmon (#10) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and
DFAULT (#11) are latched high.

Dual-UVP

Dmon (#10) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is
latched high and Cout (#8) is pulled low.

Soft-start

The IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A
error amplifier reference voltage, in order to avoid high current peaks in the primary circuit and
output voltage overshoots at start-up. In fact, if this reference gets the nominal value as soon as
the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus
forcing PWM to work with the maximum duty-cycle.

Bounce or

Latch-mode

This option allows setting either latched-mode or auto restart after 1 second delay in case of
overcurrent and undervoltage faults.

Symbol

Parameter

Value

Unit

Vdd

Supply voltage

-0.5 to +7

Voltage on PROG, PS-ON/Clock, DFAULT, VREF, and error
amplifier pins

-0.5 to Vdd+0.5

Voltage on MFAULT, PW-OK, Dmon and positive UV, OV, OC, AC
sense pins.

-0.5 to +16

Voltage on -5V and -12V UV/OV sense pins

-16 to +5

Maximum current in ESD clamp diodes

Operating Junction Temperature

-25 to 150

°C

STO

Storage Temperature

-50 to 150

°C

Lead Temperature (soldering, 10 seconds)

300

°C

Symbol

Parameter

SDIP24

SO24

Unit

th j-amb

Max. Thermal Resistance junction-to-ambient (*)

°C/W

FUNCTION DESCRIPTION (continued)

Name

Description

7/29

L6610

ELECTRICAL CHARACTERISTCS
(unless otherwise specified: T

= 0 to 105°C; V

= 5V, V

3V3

= 3.3V, V

= 5V, V

-12V

= -12V, V-

= -5V,

Dmon

= V

, PS-ON = low)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY SECTION

DD(ON)

Start-up threshold

4.2

4.3

4.6

DD(OFF)

Minimum operating voltage after
turn-on

3.7

3.8

4.1

DD(H)

Hysteresis

0.25

0.5

0.75

DDOV

Vdd overvoltage

6.1

6.3

6.8

DD-ON

Operating supply current

No Fault

FAULT THRESHOLDS

Vout = 3.3V

3V3 undervoltage

2.80

2.90

3.00

3V3 overvoltage

4.00

4.15

4.30

3V3 bias current

Vout = 5V

5V undervoltage

4.20

4.35

4.50

5V overvoltage

5.90

6.15

6.40

5V bias current

100

130

5V/3V3isns

Current sense threshold

= 4V to 6V

Bias current

5V/3V3isns

= 5V

Vout = 12V

12V undervoltage

10.60

10.80

11.00

12V overvoltage

13.50

14.00

14.50

12V bias current

100

130

12Visns

Current sense threshold

+12V

= 10V to 14V

120

144

Bias current

12Visns

= 12V

Vout = -12V

-12V undervoltage

-9.00

-9.50

-10.0

-12V overvoltage

-14.4

-15.0

-15.6

-12V disable voltage

Voltage to disable comparator

1.3

1.5

1.7

L6610

8/29

-12V bias current

-65

-50

Vout = -5V

-5V undervoltage

-3.80

-4.00

-4.20

-5V overvoltage

-6.20

-6.50

-6.80

-5V disable Voltage

Voltage to disable comparator

1.3

1.5

1.7

-5V bias current

-65

-50

Vout = 3.3V Aux/Dual (Dmon option)

3V3 undervoltage

2.80

2.90

3.00

3V3 overvoltage

4.00

4.15

4.30

Vout = 5V Aux/Dual (Dmon option)

5V undervoltage

4.25

4.40

4.55

5V overvoltage

6.00

6.25

6.50

Bias current

ACsense / Hysteresis

Bias current

ACsns

= 2.7V

AC undervoltage

2.375

2.50

2.625

Trim range

-5

Trim resolution

0.64

ACH

Hysteresis current

Hysteresis trim range

-20

+20

Hysteresis adjust step

FAULT OUTPUTS

POKL

PW-OK low state

SINK

= 15mA

0.4

MFAULT high state leakage

PS-ON = high

ISNK

MFAULT sink current

PS-ON = low, V

MFAULT

= 4V

MFAULT OV debounce

Minimum OV pulse before
MFAULT is latched.

MFAULT debounce
±12V UV

Minimum UV pulse before
MFAULT is latched.

MFAULT debounce
±5V, 3V3, UV/OC

Minimum UV/OC pulse before
MFAULT is latched.

250

450

650

ELECTRICAL CHARACTERISTCS (continued)
(unless otherwise specified: T

= 0 to 105°C; V

= 5V, V

3V3

= 3.3V, V

= 5V, V

-12V

= -12V, V-

= -5V,

Dmon

= V

, PS-ON = low)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

9/29

L6610

IOH

DFAULT output high source
current

Overvoltage condition
V

DFAULT

= 1.5V

-25

-50

-95

FVOH

DFAULT output high voltage

DFAULT

= 0mA, T

amb

= 25

Overvoltage condition

2.1

2.4

2.7

OUT

DFAULT output low voltage

DFAULT

= 1mA, no faults

0.3

0.5

0.7

DFAULT OV debounce

Minimum OV pulse before
DFAULT is latched.

DFAULT UV debounce

Minimum UV pulse before
DFAULT is latched.

250

450

650

START-UP / SHUTDOWN FUNCTIONS

DFAULT UV blanking delay

Delay from V

(on) to DFAULT

UV active.

MFAULT UV/OC blanking delay

Delay from AC

SNS

high to Main

UV/OC active

PW-OK blanking delay

Main's UV good to PW-OK high

175

250

325

DELAY

)

PS-ON delay time

Delay from PS-ON input to
MFAULT

1.75

2.5

3.25

PS-ON Input High Voltage

= -200

2.0

PS-ON Input Low Voltage

0.8

PS-ON Input high clamp

PS-ON

= 100 µA

Vdd

+0.7

PS-ON

PS-ON Pull-up to V

PS-ON

= 0V

100

PS-ON debounce

PS-ON input minimum pulse
width for a valid logic change.

100

Error Amp. A Soft-Start period

VFB quasi-monothonic ramp from
0 to 2.5V

STEP

Soft Start Step

Ramp 0V to 2.5V

VOLTAGE REFERENCE (BUFFERED EXTERNAL PIN)

REF

Output Voltage

REF

= 1 - 5 mA; C

REF

= 47nF

2.375

2.50

2.625

Short circuit current

REF

= 0

MAIN CONVERTER FEEDBACK (ERROR AMPLIFIER A)

Input Voltage

= 25° C

2.375

2.50

2.625

Trim Range

About nominal

-5

Trim resolution

0.64

ELECTRICAL CHARACTERISTCS (continued)
(unless otherwise specified: T

= 0 to 105°C; V

= 5V, V

3V3

= 3.3V, V

= 5V, V

-12V

= -12V, V-

= -5V,

Dmon

= V

, PS-ON = low)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L6610

10/29

Divider impedance

from Ainv to GND. 5V and 12V
connected to GND.

Temperature coefficient

Divider 5/12 weighting

5V contribution to 5/12 feedback

VOL

Voltage gain

2V<V

OUT

<4V

GBW

Unity gain bandwidth

MHz

PSRR

Power supply rejection ratio

4.5V<V

<6V

OUTL

Output sink current

= 2.7V, V

OUT

= 1.1V

OUTH

Output source current

= 2.3V, V

OUT

= 4V

-1.0

-1.5

-2.0

OUTH

Output high level

= 2.3V, I

SOURCE

= 1 mA

4.5

OUTL

Output low level

= 2.7V, I

SINK

= 2 mA

0.7

1.1

MAGAMP OR LINEAR POST-REGULATOR FEEDBACK (ERROR AMPLIFIER B)

Input Voltage

= 25° C

1.22

1.25

1.28

Trim Range

About nominal

-5

Trim resolution

0.64

BIAS

Input bias current

-0.1

-1

VOL

Voltage gain

2V<V

OUT

<4V

GBW

Unity gain bandwidth

MHz

PSRR

Power supply rejection ratio

4.5V<V

<6V

OUTL

Output sink current

= 1.4V, V

OUT

= 1.1V

OUTH

Output source current

= 1.1V, V

OUT

= 3V

-1.0

-1.5

-2.0

OUTH

Output high level

= 1.1V, I

SOURCE

= 1 mA

3.6

OUTL

Output low level

= 1.4V, I

SINK

= 2 mA

0.7

1.1

AUXILIARY CONVERTER FEEDBACK (ERROR AMPLIFIER C)

Input Voltage

amb

= 25° C

1.22

1.25

1.28

Trim Range

About nominal

-5

Trim resolution

0.64

BIAS

Input bias current

-0.1

-1

VOL

Voltage gain

2V<V

OUT

<4V

GBW

Unity gain bandwidth

MHz

ELECTRICAL CHARACTERISTCS (continued)
(unless otherwise specified: T

= 0 to 105°C; V

= 5V, V

3V3

= 3.3V, V

= 5V, V

-12V

= -12V, V-

= -5V,

Dmon

= V

, PS-ON = low)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

11/29

L6610

PSRR

Power supply rejection ratio

4.5V<V

<6V

OUTL

Output sink current

= 1.4V, V

OUT

= 1.1V

OUTH

Output source current

= 1.1V, V

OUT

= 4V

-1.0

-1.5

-2.0

OUTH

Output high level

= 1.1V, I

SOURCE

= 1 mA

4.5

OUTL

Output low level

= 1.4V, I

SINK

= 2 mA

0.7

1.1

OUTL

Output low level

Dmon = 2.7V, I

SINK

= 5 mA

0.25

PROGRAMMING FUNCTIONS

PROGLO

Prog Input Low

1.5

PROGHI

Prog Input High

3.5

PROG

Prog Pull Down

100

CLOCKLO

Clock Input Low

0.8

CLOCKHI

Clock Input High

CLOCK

Clock Frequency

0.8

MHz

DATALO

Data Input Low

1.5

DATAHI

Data Input High

FUSE

PROM Fuse Current

400

FUSE

PROM Fusing Time

ELECTRICAL CHARACTERISTCS (continued)
(unless otherwise specified: T

= 0 to 105°C; V

= 5V, V

3V3

= 3.3V, V

= 5V, V

-12V

= -12V, V-

= -5V,

Dmon

= V

, PS-ON = low)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L6610

12/29

Figure 1. Supply start-up, UV and OV

Figure 2. IC Supply current vs. supply voltage

Figure 3. IC Supply current

Figure 4. Monitored inputs bias current

Figure 5. Output's current sense thresholds

Figure 6. 3.3V fault thresholds

3.5

4.5

5.5

6.5

-50

-25

100 125 150

start-up

over voltage

[V]

T [

[V]

[mA]

Dmon = V

= 25 °C

-50 -25

100 125 150

[mA]

T [

-50

-25

100 125 150

3.3Voutput

5Voutput

12Voutput

T [

[

100

140

180

-50

-25

100 125 150

T [

+12V output

+5V output

[mV]

-50

-25

100

125 150

T [

undervoltage

overvoltage

3.3V

[V]

TYPICAL ELECTRICAL CHARACTERISTICS

13/29

L6610

Figure 7. 5V fault thresholds

Figure 8. 12V fault thresholds

Figure 9. 3.3V/5V Dmon fault thresholds

Figure 10. -5V and -12V bias current

Figure 11. -5V and -12V fault thresholds

Figure 12. ACsense reference

-50

-25

100

125

150

T [

overvoltage

undervoltage

[V]

-50

-25

100 125 150

T [

overvoltage

undervoltage

+12V

[V]

-18

-15

-12

-9

-6

-3

-50

-25

100 125

150

+3.3V undervoltage

+5V undervoltage

+5V overvoltage

+3.3V overvoltage

T [

DMON

[V]

-50

-40

-30

-20

-50

-25

100 125 150

T [

[mA]

-12

-5V

-12V

-18

-15

-12

-9

-6

-3

-50 -25

75 100 125 150

out

[V]

-12V overvoltage

-12V undervoltage

-5V undervoltage

-5V overvoltage

T [

2.3

2.4

2.5

2.6

2.7

-50 -25

75 100 125 150

T [

[V]

TYPICAL ELECTRICAL CHARACTERISTICS (continued)

15/29

L6610

APPLICATION INFORMATION INDEX

1 On board digital trimming and mode selection..................................................................................Page 16

2 Error amplifiers and reference voltages ..................................................................................................... 18

Main section: error amplifier A and Soft -Start

E/A and reference voltage

3.3V section: error amplifier B

Auxiliary section: error amplifier C

3 Normal operation timing diagram ............................................................................................................... 20

4 Undervoltage, overvoltage, overcurrent and relevant timings .................................................................... 21

5 AC sense (mains undervoltage warning) ................................................................................................... 21

6 Application example ................................................................................................................................... 23

7 Application ideas ........................................................................................................................................ 25

L6610

16/29

APPLICATION INFORMATION

ONBOARD DIGITAL TRIMMING AND MODE SELECTION

By forcing the PROG input pin high, the chip enters programming mode: the multifunction pins PW_OK and
PS_ON are then disconnected from their normal functions (output pins) and are connected to internal logic as
DATA and CLOCK inputs respectively, allowing chip programming even when the device is assembled on the
application board. Onboard chip programming allows:

selecting some working options;

reference voltage setpoints adjusting.

It is also possible to verify the expected results before programming the chip definitively, in first instance, data
can be loaded into a re-writeble volatile memory (a flip-flop array) where they are kept as long as the chip is
supplied and can be changed as many times as one desires. A further operation is necessary to confirm the
loaded data and permanently store them into a PROM (a poly-fuse array) inside the IC.

Several steps compose the trimming/programming process:

1. PROG pin is forced high;

2. a clock signal is sent to the PS-ON/clock pin;

3. a byte with the following structure:

is serially sent to the PW-OK/DATA pin and loaded into the IC's volatile memory bit by bit on the falling edges
of the clock signal (see Fig. 16); "Address" is the identification code of the parameter that has to be trimmed
and "Data" contains the tuning bits;

4. PROG pin is forced low (warning: Vdd must never fall below V

ddUVL0

during this process otherwise the con-

tents of the volatile memory will be lost) and the result of the previous step is checked;

5. after any iterations of the steps 1-4 that might be necessary to achieve the desired value, force PROG pin

high and send the following burn code

to permanently store the data in the PROM memory.

Table 1 shows the list of the 6 programmable classes of functions, each one identified by a different code
A0..A3, and the corresponding trimmable parameter(s); in table 2 it is possible to find the trim coding for the E/
A reference setpoints and in table 3 all the selections mode option coding are showed. The timing diagram of
fig. 16 shows the details of data acquisition.

Table 1. Programmable functions

MSB

LSB

Data

Address

MSB

LSB

Address

Parameter(s)

Default value

Tuning bits

0001

Error amplifier A threshold

2.50V

0010

Error amplifier B threshold

1.25V

0011

Error amplifier C threshold

1.25V

0100

AC sense threshold

2.50V

0101

AC sense hysteresis

Latch/Bounce mode selection

Latch mode

0110

Enable/Disable 12V UV/OV function

Enabled

Enable/Disable 5V UV/OV function

Enabled

5V/3V3 Dmon selection

5V selection

5V/3V3 Overcurrent selection

5V selection

17/29

L6610

Table 2. Trim Coding

Table 3. Mode coding

Figure 16. Trimming/programming procedure: timing diagram

Parameter

E/A A threshold

2.5V typ.

E/A B threshold

1.25V typ.

E/A C threshold

1.25V typ.

ACsns threshold

2.5V typ.

ACsns

Hysteresys

A typ.

Address

0001

0010

0011

0010

0101

Tuning Bits

D3 D2 D1 D0

V [mV]

D3 D2 D1 D0

V [mV]

D3 D2 D1 D0

V [mV]

D3 D2 D1 D0

V [mV]

D2 D1 D0

I [

0 1 1 1

+112

+56

+112

0 1 1 0

+96

+48

+96

0 1 0 1

+80

+40

+80

0 1 0 0

+64

+32

+64

0 0 1 1

+48

+24

+48

+7.5

0 0 1 0

+32

+16

+32

+5.0

0 0 0 1

+16

+2.5

0 0 0 0

1 1 1 1

-16

-8

-16

-2.5

1 1 1 0

-32

-16

-32

-5.0

1 1 0 1

-48

-24

-48

-7.5

1 1 0 0

-64

-32

-64

-10

1 0 1 1

-80

-40

-80

1 0 1 0

-96

-48

-96

1 0 0 1

-112

-56

-112

1 0 0 0

-128

-64

-128

Parameter

Bounce or

Latch Mode

Enable/Disable

12V UV/OV

Enable/Disable

5V UV/OV

5V/ 3.3V Dmon

Selection

5V/3.3V OCP

Selection

Address

A3 A2 A1 A0

0101

A3 A2 A1 A0

0110

Bit Value

Tuning Bit

Latch

Enabled

Bounce

Disabled

3.3V

MSB

LSB

PROG

PS_ON/Clock

PW_OK/Data

L6610

18/29

ERROR AMPLIFIERS AND REFERENCE VOLTAGES

Three error amplifiers are implemented on the IC to achieve regulation of the output voltages: a brief description
follows for each section.

Main section: error amplifier A and Soft-Start.

The circuit is designed to directly control the Main primary PWM through an optocoupler, providing
very good regulation and galvanic isolation from the primary side. Typical solutions require a shunt
regulator, like the TL431, as a reference and feedback amplifier to sense the output voltage and gen-
erate a corresponding error voltage; this voltage is then converted in a current transferred to the pri-
mary side through the optocoupler.
The feedback E/A amplifier is integrated in the IC: its non-inverting input is connected to an internally gen-
erated voltage reference, whose default value is typically 2.5V. It can however be trimmed to obtain a better
precision (see "On board trimming and mode operating" section). Then, no TL431 is needed.
The E/A inverting input (Ainv, pin#5) and the E/A output (Aout, pin#6) are externally available and the
frequency compensation network (Zc) will be connected between them (see fig. 17).
The high impedance (in the hundred k

) internal divider from 12V and 5V UV/OV sense pins elimi-

nates the need for an external one in most applications, allowing a further reduction in the number of
external component.
Under closed loop condition, the two upper branches, connected to 12V and 5V pins, supply equally
the current flowing through R3 = 80.6K (equal to 2.5V/R3).
In order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up,
the IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A error
amplifier reference voltage,. In fact, if this reference gets the nominal value as soon as the power-up
occurs, the A E/A will go out of regulation and tend to sink much more current, thus forcing PWM to
work with the maximum duty-cycle.

E/A and references voltage

Being the inverting input of E/A externally available, it is possible to change the "weight" of the two
contributions or even eliminate one of them by connecting external resistors of much lower value (R

and/or R

in fig. 17) that bypass the internal ones appropriately.

For example using R

=2.4K, R

=3.9K and R

=24K, then the ratio between +5V and +12V output

weight will be equal to 6:4.
By simply making R

= R

(for example 2.4K) with no R

, only the +5V output is kept under feed-

back because the contribution of +12V branch (through the internal 600K resistor) will be negligible.
The pin #24 (12V) has to be however connected to +12V output to guarantee the OV/UV monitoring.

Figure 17. Main feedback section

3.3V section, error amplifier B.

It is the error amplifier used to set the magamp core through an external circuitry (see a typical sche-
matic in figure 18).
The non-inverting input of the error amplifier is connected to a trimmable 1.25V internal voltage ref-
erence (see "On board trimming and mode operating" paragraph). The E/A inverting input is exter-
nally available (Binv, pin#2) and is connected to the output divider (R

and R

); the output pin (Bout,

to MAIN

control

Aout

12V

+2.5V

600K

168K

80.6K

8ms SS

L6610

GND

+12V output

+5V output

Ainv

optional, to change
feedback weight

19/29

L6610

pin#3) drives the external circuitry that biases the magamp core. Between these pins it is connected
the compensation network (Z

). The maximum positive output voltage is clamped at about 3.5V to

improve response time.
The feedback control circuit determines the magamp "off" time, converting the voltage at the output
of error amplifier into a current I

, which resets the magamp. If the output voltage exceeds its preset

value, V(B

out

) decreases; this causes a higher voltage across R

which, in turn, implies a larger volt-

age across R

and a larger reset current I

of Q

is supposed constant). A larger I

causes the

PWM waveform across D

to get narrower. This pulls the output voltage back to the desired level and

achieves regulation.
It is possible to use this section to drive a pass transistor to obtain 3.3V with a linear regulator; in the
"Application idea" section an example is showed to implement this solution.

Figure 18. Magamp control feedback section

Auxiliary section, error amplifier C. This section (fig. 19) provides the feedback signal for the auxiliary

converter following the same operating principles as the Main section. The auxiliary output voltage
(Vaux) is often defined as "Standby voltage" because the converter remains alive during standby con-
dition (the Main converter is stopped) to supply the chip and all the ancillary circuits. Typical values for
its output voltage are 5V or 3.3V.
The inverting input (Cinv, pin#9) is connected to the output voltage through an external resistor divider
whereas the non-inverting one is connected to a 1.25V trimmable internal voltage reference (see "On
board trimming and mode operating" paragraph).
The compensation network Zc(aux) is placed between E/A inverting input and output pins.
When Dmon recognizes an undervoltage condition on the auxiliary output, an internal n-channel MOS
(in open drain configuration) grounds E/A output pin; the high current flowing through the optocoupler
is then transferred to the primary side causing a duty cycle as short as possible; this prevents a high
energy transfer from primary to secondary under short circuit conditions, thus reducing the thermal
stress on the power components.

Figure 19. Auxiliary feedback section

+3.3V

Bout

Binv

+1.25V

L6610

magamp

+3.3V

Bout

Binv

+1.25V

L6610

magamp

AUX

to AUX
control

Zc(aux)

Cout

Cinv

+1.25V

L6610

OCP bounce

GND

DMON

L6610

20/29

NORMAL OPERATION TIMING DIAGRAM (FIG. 20)

The time intervals t1-t5 are listed below
t1: UV/OC blanking of MFAULT. While Main outputs are ramping up, the UV comparators are blanked

for this interval to prevent a false turn-off. No such blanking is applied to OV faults.

t2: PW-OK delay. This period starts when all monitored outputs and AC sense are above their respec-

tive UV levels and finishes at PW-OK going high.

t3: PS-ON debounce period. The voltage on PS-ON must be continuously present in a high or low state

for a minimum period for that state to be recognized.

t4: Tdelay. The time from PS-ON being recognized as going high to MFAULT going high. This is to

provide a power down warning. When PS-ON requests power off, PW-OK goes low immediately.

t5: UV blanking of DFAULT. During initial power up a period of UV blanking is applied to DFAULT as

soon as Vdd to the chip is in the correct range. No such blanking is applied to OV faults.

Figure 20. Normal Operation Timing Diagram (ON/OFF with PS-ON or the AC power switch).

Vdd

PS-ON

Mfault

Main
OPs

POK

UVBmfault

ACsns

Off

Vdd-ok

UVBdfault

ACsns_high

ACsns_low

Vdd(on)

21/29

L6610

UNDERVOLTAGE, OVERVOLTAGE, OVERCURRENT DETECTION AND RELEVANT TIMINGS

The IC provides on-board undervoltage and overvoltage protection for 3V3, ±5V, ±12V Main input pins and
Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The
internal fault logic is illustrated in figure 21.

Figure 21. Simplified Fault logic

Main inputs overvoltage: whenever one of main outputs (3.3V, ±5V, ±12V) is detected as going over-

voltage, MFAULT is latched high (which stops the Main PWM) and PW-OK goes low. Cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6µs is imple-
mented before MFAULT latching.
The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode op-
erating" section).

Main inputs undervoltage: when an undervoltage on main outputs is detected, MFAULT is latched

high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold (latching mode); optionally, an attempt is
made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode
(see "On board trimming and mode operating" section).
Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has
to last 450µs to be recognized as valid while 6µs debounce logic is implemented for 12V and -12V input
signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes
high after a delay of 250ms.

Dmon input overvoltage: whenever the Dmon input pin is detected as going overvoltage, both

MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage
threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the
overvoltage condition lasts more than 6µs.
To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by

Delay 1s

C lock

Out

R eset

Debounce 75ms

C lock

R eset

Out

PS-ON

Restart Mode

Vdd

Vdd_OV

Vdd_UVL

C lock

R eset

UVB 64ms

Out

C lock

R eset

UVB 64ms

Out

Dmon_UV

Dmon_OV

ACsense

Vref

Main_OC

Main_OV

R eset

C lock

Out

Debounce 6

R eset

C lock

Out

R eset

C lock

Out

Latch

C lock

R eset

Out

Delay 250ms

Delay 2.5ms

R eset

Out

C lock

Vdd

PW-OK

Cout

Latch

Dfault

Vdd

Mfault

Latch

Vdd

D_UVB

Reset

R eset

C lock

Out

Reset

R eset

C lock

Out

+/-12V_Main_UV

+3V3 +/-5V_Main_UV

Debounce 6

Debounce 500

Debounce 6

OCP_BOUNCE

L6610

22/29

DFAULT; in the "Application ideas" section, another simple circuit is showed to guarantee the same pro-
tection without the SCR.

Dmon input undervoltage: when an undervoltage on Dmon is detected, MFAULT is put high, Cout is

pulled low (an internal OCP_BOUNCE signal is generated, see fig. 21) and PW_OK falls down. This
function is enabled 64ms after the UVLO signal falls down. Debounce logic is implemented so that
MFAULT and OCP_BOUNCE signals are generated only if the undervoltage condition lasts more than
500µs.
The Dmon UV and OV protections can be set to work with thresholds set for 5V or 3.3V output voltage:
the choice depends on the IC programming.

Overcurrent protection: the IC provides an on-board overcurrent protection for 5V and 12V main input

pins. Optionally, it is possible to switch the monitoring from 5V to 3.3V output using the IC programming
(see "On board trimming and mode operating" section).

Figure 22. Fault timing diagram

The overcurrent function is implemented with a comparator detecting the voltage drop across an external cur-
rent sense resistor in series with the output. If this voltage gets higher than a fixed threshold (50mV for 5V input
monitoring and 120mV for 12V input monitoring), an internal MAIN_OC signal is generated; a 450

s debounce

time exists to assert MFAULT high. Depending on the selected operating mode, MFAULT will be latched high
(default latching mode) or pulled low again after about 1s to allow autorecovery (bounce mode).

To disable this function, the input sense pin may be left open (an internal pull-down is provided), shorted to
ground or shorted to 5V or 12V pin.

Dmon

(*)

Dmon

(*)

Mfault

POK

Dfault current

Cout

Output

Mfault

POK

Main output's overvoltage

Output

Mfault

POK

Main output's undervoltage

Auxiliary output's overvoltage

Auxiliary output's undervoltage

(*) Dmon is connected to the Auxiliary output Rail

23/29

L6610

AC SENSE (MAINS UNDERVOLTAGE WARNING)

The device monitors the primary bulk voltage and warns the system when the power is about to be lost pulling
down the PW_OK output.

The ACsns pin is typically connected to one of the windings of the main transformer (see fig. 23). Through a
single-diode rectification filter, a voltage equal to V

= V

BULK

/N (where V

BULK

is the voltage across the bulk ca-

pacitor on primary side and N is the transformer turn ratio) is present at point B. A resistor (R

) could be useful

to clamp voltage spikes present.

The fault signal is generated by means of AC_GOOD, the output of an internal comparator; this comparator is
internally referred to a trimmable 2.5V reference and indicates an AC fault if the voltage applied at its externally
available (non-inverting) input is below the internal reference, as shown in fig. 23.

This comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 50µA
current generator is ON if the voltage is below 2.5V and is turned off when the voltage applied at the non-invert-
ing input exceeds 2.5V.

This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF
threshold separately by properly choosing the resistors of the external divider. The following relationships can
be established for the ON (VB

(ON)

) and OFF (VB

(OFF)

) thresholds of the input voltage:

which, solved for R1 and R2, yields:

Both the ACsns threshold and the hysteresis current can be trimmed (see "On board trimming and mode oper-
ating" section).

Figure 23. ACsns circuit and timing diagram

APPLICATION EXAMPLE

In applications like desktop PC's, server or web server, the system usually consists of two converters (Main and
Auxiliary) that can be supplied directly from either the AC Mains or a PFC stage. The control and supervision at
the secondary side is usually entrusted to a housekeeping circuit.

The Auxiliary section supplies a stand-by voltage (5V typ.) through a flyback converter. The Main section, in
forward configuration, presents 5 standard outputs (3.3V, ±5V, ±12V).

At the secondary side, the housekeeping circuitry governed by the L6610 checks the outputs and sends control
signals to the primary side through three optocouplers. It also generates power good information to the system
while managing all timings during power-up and power-down sequences. In fig. 24 a detailed circuit for the sec-
ondary side is presented; it is possible to note the very low number of external components required.

O N

(

)

2.5

----------------------------------

2.5

--------

O FF

(

)

--------------------

2.5

O N

(

)

O FF

(

)

-------------------------------------------------

2.5

O FF

(

)

2.5

-------------------------------------

+2.5V

GND

HYS=50

AC_GOOD

L6610

ACsns

AC_GOOD

ACsns

VB(on)

VB(off)

=50

A*R

PW_OK

L6610

24/29

Simply connecting the power supply outputs to the L6610 relevant pins ensures the protection against over/un-
dervoltage in the Main section; the protection against overcurrent can be achieved (for 12V and 5V or 3.3V)
adding a small sense resistor.

A crowbar on the auxiliary output is switched on through DFAULT in case of overvoltage.

The L6610 is supplied by the Auxiliary output; the signals sent to the primary side are:

a "digital" ON/OFF signal through an optocoupler that drives the relevant pin of primary Main controller

to switch the Main converter ON and OFF;

two analog signals that provide voltage feedback for both the Auxiliary and the Main section, driving the

primary controller pins responsible for the duty cycle modulation.

In server's SMPS applications, a current sharing system is usually required to allow paralleling of several mod-
ules: the L6615 (ST's Current sharing IC, [1]) does the job providing an interface for this purpose (fig. 25) and
guaranteeing an homogeneous current distribution between the paralleled power supplies.

The voltage drop across the sense resistors for overcurrent detection can be also used whenever current shar-
ing is required for 5V (or 3.3V) and/or 12V: the L6615 has a differential sense amplifier whose inputs can be
connected (through two resistors) at the two sense resistor leads. The share bus, referred to ground, links all
the paralleled power supplies.

REFERENCES

[1] "L6615 - Load share controller" (Datasheet)

Figure 24. Detailed Secondary Side

+5Vaux

+5V

+12V

COM

-5V

+3.3V

-12

3V3

DMON

12V

GND

-5

Bout

Binv

M-FAULT

Ainv

Cout

PS-ON

12Visns

Cinv

VREF

Aout

3V3/5Visns

Vdd

ACsns

DFAULT

PW-OK

GND

FAN

I
M

S
I
DE

&
P
O

W
E

R
M

L6610

PROG

-12V

L6610

26/29

APPLICATION IDEAS

In fig. 26 a circuit is suggested to obtain the regulated +3.3V output with a linear configuration instead of the
Magamp circuitry.

In this case the output of the E/A modulates the gate-source voltage of a power MOS in series with the power
stage.

In fig. 27 a simple and cheap latch circuit is showed to manage an OV fault on the Auxiliary output in the same
way of an OC (UV) fault, without having recourse to a (expensive) power crowbar. By tuning the value of R

SET

it is possible to set the voltage value that triggers the latch circuit; C

DEL

defines the turn-on delay. A diode con-

nected between the collector of Q1 and Cout pulls down the output of the auxiliary E/A: this has the same effect
of the OCP_bounce internal signal that guarantees the reduction of duty cycle.

Figure 26. Controlling a Linear Regulator with the Error Amplifier B

Figure 27. Auxiliary OVP without Crowbar

+3.3V

Bout

Binv

+1.25V

L6610

+5V

+12V

L6610

AUX

DMON

100

5K6

BC558

BC548

SET

DEL

Cout

BAT42

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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http://www.st.com

29/29

L6610

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L6610N