1/20
L6615
July 2003
s
SSI SPECS COMPLIANT
s
HIGH/LOW SIDE CURRENT SENSING
s
FULLY COMPATIBLE WITH REMOTE
OUTPUT VOLTAGE SENSING
s
FULL DIFFERENTIAL LOW OFFSET
CURRENT SENSE
s
2.7V TO 22V V
CC
OPERATING RANGE
s
32k
SHARE SENSE AMPLIFIER INPUT
IMPEDANCE
s
HYSTERETIC UVLO
APPLICATION
s
DISTRIBUTED POWER SYSTEMS
s
HIGH DENSITY DC-DC CONVERTERS
s
(N+1) REDUNDANT SYSTEMS, N UP TO 20
s
SMPS FOR (WEB) SERVERS
DESCRIPTION
This controller IC is specifically designed to
achieve load sharing of paralleled and indepen-
dent power supply modules in distributed power
systems, by adding only few external components.
Current sharing is achieved through a single wire
connection (share bus) common to all of the paral-
leled modules.
DIP8
SO8
ORDERING NUMBERS:
L6615N
L6615D
L6615DTR(T & Reel)
HIGH/LOW SIDE LOAD SHARE CONTROLLER
TYPICAL APPLICATION DIAGRAM
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BUS
LOAD
(
*
) OR-ing FET can
be used to reduce
power dissipation
(
*
)
(
*
)
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BUS
LOAD
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BUS
LOAD
(
*
) OR-ing FET can
be used to reduce
power dissipation
(
*
)
(
*
)
BCD TECHNOLOGY
L6615
2/20
DESCRIPTION (continued)
Load sharing is a technique used in all the systems in which the load requires low voltage, high current
and/or redundancy; for this reason a modular power system is necessary in which two or more power sup-
plies or DC-DC converters are paralleled.
The device is able to perform both high side and low side current sensing, that is the sense current resistor
can be placed either in series to the power supplies output or on the ground return.
The L6615 then drives the share bus to a voltage proportional to the output current of the master that is
to the highest amongst the output currents delivered by the paralleled power supplies.
The share bus dynamics is independent of the power supply output voltage and is clamped only by the
device supply voltage (V
CC
).
The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that
they can support their amount of load current. The slave power supplies work as current-controlled current
sources.
Sharing the output currents is useful for equalizing also the thermal stress of the different modules and
providing an advantage in term of reliability.
Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the mod-
ules can be tolerated until the capability of the remaining power supplies is enough to provide the required
load current.
PIN DESCRIPTION
N
Pin
Function
1
GND
Ground.
2
CS-
Input of current sense amplifier; it is connected to the negative side of the sense resistor through
a resistor (R
G2
).
3
CS+
Input of current sense amplifier. A resistor (R
G1
, of the same value as R
G2
) is placed between
this pin and the positive side of the sense resistor: its value defines the transconductance gain
between I
CGA
and V
SENSE
.
4
ADJ
Output of Adjust amplifier; it is connected to both the load (through a resistor R
ADJ
) and to the
positive remote sense pin of the power system. This pin is an open collector diverting (from the
feedback path) a current proportional to the difference between the current supplied to the load
by the relevant power supply and the current supplied by the master.
5
COMP
Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier.
Typically, a compensation network is placed between this pin and ground. The maximum voltage
is internally clamped to 1.5V (typ.)
6
SH
Share bus pin. During the power supply
slave
operation, this pin acts as positive input from
share bus. During power supply
master
operation, it drives the share bus to a voltage
proportional to the load current.
The
share
bus connects the SH pins of all the paralleled modules. A capacitor between this pin
and GND could be useful to reduce the noise present on the share bus.
7
CGA
Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin
and ground defines the maximum voltage on the share bus and sets the gain of the current
sharing system.
8
V
CC
Supply voltage of the IC.
3/20
L6615
ABSOLUTE MAXIMUM RATINGS
All voltages are with respect to pin 1. Currents are positive into, negative out of the specified terminal.
(*) Maximum package power dissipation limits must be observed
PIN CONNECTION
THERMAL DATA
Symbol
Pin
Parameter
Value
Unit
V
CC
8
Supply Voltage (*) (I
CC
<50mA)
selflimit
V
I
CS
+, I
CS
-
Sense pin current
10
mA
V
CS
-, V
CS+
, V
SH
,
V
ADJ
, V
CGA
2, 3, 6, 4, 7
-0.3 to V
CC
V
V
COMP
5
Error amplifier output
-0.3 to 1.5
V
(V
CS+
) - (V
CS-
)
Differential input voltage (V
CS
+ from 0V to 22V)
-0.7 to 0.7
V
Ptot
Total power dissipation @ Tamb = 70C
SO8
DIP8
0.45
0.6
W
Tj
Junction temperature range
-40 to +125
C
Tstg
Storage temperature
-55 to +150
C
Symbol
Parameter
MINIDIP
SO8
Unit
R
th j-amb
Thermal Resistance junction to ambient
90
120
C/W
1
2
4
3
GND
VCC
CS-
5
6
8
7 CGA
SH
ADJ
COMP
CS+
1
2
4
3
GND
VCC
CS-
5
6
8
7 CGA
SH
ADJ
COMP
CS+
L6615
4/20
ELECTRICAL CHARACTERISTCS
(Tj = -40 to 85C, Vcc=12V, V
ADJ
= 12V, C
COMP
= 5nF to GND, R
CGA
= 16k
, unless otherwise specified;
V
SENSE
= I
L
* R
SENSE
, R
G1
= R
G2
= 200
)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vcc
V
cc
Operating range
2.7
22
V
I
cc
Quiescent current
V
SH
= 1V, V
SENSE
= 0V
5
6
mA
V
CC, ON
Turn-on voltage
V
SH
= 0.2V, V
SENSE
= 0V
2.45
2.60
2.75
V
V
CC,OFF
Turn-off voltage
2.35
2.5
2.65
V
V
H
Hysteresis
100
mV
Vz
I
CC
= 20mA
24
26
V
CURRENT SENSE AMPLIFIER
V
OS
Input offset voltage
0.1V
V
SH
10.0V
-1.5
0.0
1.5
mV
V
CGA
Out high voltage
V
SENSE
= 0.25V
V
cc
-2.2
V
I
CGAS
Short circuit current
V
CGA
= 0V, V
SENSE
= 0.45V
-1.5
-2.0
mA
I
B(CS-)
Input bias current (high side
sensing)
V
SENSE
= 0V, V
CS+
=+12V
1.0
A
I
B(CS+)
Input bias current (low side
sensing)
V
SENSE
= 0V, V
CS+
=0V
-1.0
A
CMR
Common mode dynamics range
V
CS-,
V
CS+
0
V
CC
V
VTH
CS+
Switchover threshold low side to
high side sensing
V
CS+
1.6
V
SW
H
Switchover hysteresis
0.16
V
SHARE DRIVE AMPLIFIER
HV
SH
SH high output voltage
V
SENSE
= 250mV, I
SH
= -1mA
V
cc
-2.2
V
LV
SH
SH low output voltage
V
CGA
= 0mV, R
SH
= 200
45
mV
(+)
High side sensing mirror accuracy
(*)
1
5
%
(-)
Low side sensing mirror accuracy
(*)
1
5
%
V
SH, load
Load regulation
-1.0mA
I
SDA(OUT)
-4mA
20
mV
I
SC
Short circuit current
V
SH
= 0V, V
SENSE
= 25mV
-20
-13.5
-8
mA
SR
Slew rate
V
SENSE
= -10mV to 90mV step,
R
SH
= 200
to GND
0.8
1.5
2.2
V/
s
V
SENSE
= 90mV to 10mV step,
R
SH
= 200
to GND
2
3
4
V/
s
SHARE SENSE AMPLIFIER
R
i
Input impedance
22.4
32
41.6
k
ERROR AMPLIFIER
G
m
Transconductance
3
4
5
mS
V
os
Input offset voltage
V
CGA
=1V
30
50
70
mV
5/20
L6615
(*) Mirror accuracy is defined as :
and it represents the accuracy of the transfer between the voltage sensed and the voltage imposed on the
share bus.
BLOCK DIAGRAM
I
OH
Source current
V
COMP
=1.5V, V
SH
300mV,
V
SENSE
=-10mV
-150
-350
-400
A
I
OL
Sink current
V
COMP
= 1.5V, V
SENSE
=-10mV
200
resistor SH to GND
100
200
300
A
V
COMP(L)
Low voltage
0.05
0.15
0.25
V
Z
Clamp Zener voltage
I
Z
= 1mA
1.5
V
ADJ AMPLIFIER
I
ADJ
Max. ADJ output current
V
SH
= 1V, V
SENSE
= 0V
6.5
10
13
mA
V
T
Threshold voltage
I
ADJ
=10
A
0.7
V
R
A
Emitter resistor
Guaranteed by design
60
100
140
V
ADJ(MIN)
Low saturation voltage
I
ADJ
=5mA
1
V
I
ADJ
=1mA
0.4
V
ELECTRICAL CHARACTERISTCS (continued)
(Tj = -40 to 85C, Vcc=12V, V
ADJ
= 12V, C
COMP
= 5nF to GND, R
CGA
= 16k
, unless otherwise specified;
V
SENSE
= I
L
* R
SENSE
, R
G1
= R
G2
= 200
)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S H
V
SE N SE
R
CG A
R
G
---------------
-----------------------------------------
1
100
=
_
ADJ OUTPUT
AMPLIFIER (AOA)
COMP
V
CC
40 mV
SH
+
+
_
CGA
_
+
7
I
CGA
UVLO
BIAS
8
6
CS-
CS+
2
3
4
ADJ
R
A
0.7V
Gm ERROR
AMPLIFIER (E/A)
1.5V
5
SHARE SENSE
AMPLIFIER (SSA)
SHARE DRIVE
AMPLIFIER (SDA)
+
_
1
GND
_
+
CURRENT SENSE
AMPLIFIER (CSA)
R
R
R
R
R
R
R
R
24V
_
ADJ OUTPUT
AMPLIFIER (AOA)
COMP
V
CC
40 mV
SH
+
+
_
CGA
_
+
7
I
CGA
UVLO
BIAS
8
6
CS-
CS+
2
3
4
ADJ
R
A
0.7V
Gm ERROR
AMPLIFIER (E/A)
1.5V
5
SHARE SENSE
AMPLIFIER (SSA)
SHARE DRIVE
AMPLIFIER (SDA)
+
_
1
GND
_
+
CURRENT SENSE
AMPLIFIER (CSA)
R
R
R
R
R
R
R
R
24V
L6615
6/20
Figure 1. Turn-on and turn-off voltage
Figure 2. Supply current vs. supply voltage
Figure 3. Supply current
Figure 4. Max CGA current
Figure 5. High side/low side sensing
switchover threshold
Figure 6. Max. share bus voltage at no load
V
CC(ON)
, V
CC(OFF)
[V]
2.2
2.6
3
-50
0
50
100
T
J
[
O
C]
I
CC
[ mA]
0.01
0.1
1
10
100
0.1
1
10
100
V
CC
[V]
)
I
CC
[mA]
2.7
3.1
3.5
3.9
4.3
4.7
- 50
0
50
100
T
J
[
O
C]
I
CGA(max)
[mA]
1.8
2
2.2
2.4
2.6
2.8
- 50
0
50
100
T
J
[
O
C]
V
TH
[V]
1.3
1.5
1.7
1.9
- 50
0
50
100
T
J
[
O
C]
V
SH(LOW)
[mV]
10
15
20
25
30
35
40
45
50
- 50
0
50
100
T
J
[
O
C]
7/20
L6615
Figure 7. Share bus input impedance
Figure 8. ADJ maximum current
R
I
[k ]
20
25
30
35
40
45
50
- 50
0
50
100
T
J
[
O
C]
I
AD J[MAX]
[mA]
5
7
9
11
13
15
- 50
0
50
100
T
J
[
O
C]
L6615
8/20
APPLICATION INFORMATION
Index
page
1.
Introduction
8
2.
Current sense section
9
3.
Share drive section, error amplifier and adjust amplifier
10
4.
Designing with L6615
10
5.
Current sense methods
13
6.
Application ideas
14
7.
Low voltage buses
15
8.
Offset Trimming
16
1
INTRODUCTION
Power supply systems are often designed by paralleling converters in order to improve performance and
reliability.
To ensure uniform distribution of stresses, the total load current should be shared appropriately among
the converters.
A typical application is showed in fig. 9 for a series of N paralleled modules (PS#1 to PS#N): each of them
exhibits 4 terminals: two for the power output (+OUT, -OUT) and two for the remote sense signals
(+OUT_S, -OUT_S).
On the power lines are placed the sense resistors R
SENSE
(for the current sensing) and the OR-ing diodes
(to avoid that the failure of one module shorts the load out)
L6615 allows attaining an automatic master-slave current sharing architecture: one L6615 is associated to each
power supply and all these IC's are linked each other through the share bus (referred to the common ground).
This kind of system configuration is preferred to the systems in which a single current sharing controller is
used because of robustness, reliability and flexibility.
To configure a load share controller, few passive components are used. A brief device explanation will
follow with the formulas useful to set these external components.
Figure 9. Typical high side connection
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BUS
LOAD
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
GND
PS #1
C
C
R
C
R
CGA
R
ADJ
R
SENSE
CS-
CGA
CS+
VCC
ADJ
SHARE
GND
COMP
3
2
4
1
5
6
7
8
L6615
+OUT
+OUT_S
-OUT_S
-OUT
PS #N
C
C
R
C
R
CGA
R
ADJ
R
SENSE
+OUT
+OUT_S
-OUT_S
-OUT
R
G1
R
G2
R
G1
R
G2
SHARE BUS
LOAD
9/20
L6615
2
CURRENT SENSE SECTION
A sense resistor is typically used to generate the voltage drop, proportional to the load current, measured
by the CSA (Current Sense Amplifier), whose input pins (pins #2 and #3) are connected across of R
SENSE
through two identical resistors (RG1 and RG2).
The CSA consists of 2 sections (see fig. 10), one responsible for the high side sensing, the other for low
side sensing. An internal comparator activates the relevant section in accordance with the voltage present
at CS+ pin: if this voltage is higher than 1.6V (typ), then the high side sensing section will be activated
(fig10.a) otherwise the low side sensing one will (fig 10.b). For the sake of simplicity we will consider R
G1
=
R
G2
= R
G
.
As the voltage drop I
OUT
*R
SENSE
is present at the input of the Sense Amplifier section, its output forces
the controlled current mirror to:
sink current from the CS+ pin in case of high side sensing (neglecting input bias current, no current flows
through CS- pin);
source current from the CS- pin in case of low side sensing (neglecting input bias current, no current
flows through CS- pin).
The local feedback imposes the same voltage at the current sense input pins, so under closed loop con-
dition V
SENSE
=VR
G
.
The current
(IC
S+
in case of high side, I
CS-
in case of low side) is then internally mirrored and sent to the CGA pin caus-
ing a drop across the R
CGA
external resistor: two internal buffers transfer V
CGA
signal on the share pin so:
Only the L6615 V
CC
limits the upper voltage at the CGA and SH pin, independently of the voltage present
at the current sense pins.
In noisy applications, two capacitors of small value (e.g. 1nF) connected between current sense pins and
ground could be useful to clean the signal at the input of the current sense amplifier.
For low voltage buses application, see paragraph 7.
Figure 10. Current sense section
I
C S
I
OU T
R
S EN SE
R
G
---------------------------------------
=
V
SH
V
SNS
R
G
--------------
R
CGA
=
COMPARE
CS-
CS+
LSA
CGA
PS+
LOAD(+)
I
OUT
R
SENSE
R
G
R
G
V
SENSE
I
CGA
I
CS+
V
RG
HSA
+
-
+
-
R
CGA
L6615
1.6V
CONTROLLED
CURRENT
MIRROR
1:1
SINK
CSA
LOAD(-) / GND
PS-
COMPARE
CS-
CS+
LSA
CGA
I
OUT
R
SENSE
R
G
R
G
V
SENSE
I
CGA
V
RG
HSA
+
-
+
-
R
CGA
L6615
1.6V
CONTROLLED
CURRENT
MIRROR
SOURCE
CSA
1:1
I
CS-
COMPARE
CS-
CS+
LSA
CGA
PS+
LOAD(+)
I
OUT
R
SENSE
R
G
R
G
V
SENSE
I
CGA
I
CS+
V
RG
HSA
+
-
+
-
R
CGA
L6615
1.6V
CONTROLLED
CURRENT
MIRROR
1:1
SINK
CSA
LOAD(-) / GND
PS-
COMPARE
CS-
CS+
LSA
CGA
I
OUT
R
SENSE
R
G
R
G
V
SENSE
I
CGA
V
RG
HSA
+
-
+
-
R
CGA
L6615
1.6V
CONTROLLED
CURRENT
MIRROR
SOURCE
CSA
1:1
I
CS-
a) high side sensing
b) low side sensing
L6615
10/20
3
SHARE DRIVE SECTION, ERROR AMPLIFIER AND ADJUST AMPLIFIER
The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so, for the master
power supply, V
CGA
= V
SH
; the voltage on the share bus is imposed by the master.
In the slave converters, being V
CGA(SLAVE)
< V
CGA(MASTER)
, the diode at the output of SDA (see block
diagram) isolates the output this amplifier from the share bus.
The Share Sense Amplifier (SSA) reads the bus voltage transferring the signal to the non-inverting input
of the error amplifier where it is compared with CGA voltage.
Whenever a controller acts as the master in the system, the voltage difference between the E/A inputs is
zero. To guarantee its output low in such condition, a 40mV offset is inserted in series with the inverting
input.
Instead in the slave converters the input voltage difference is proportional to the difference between the
master load current and the relevant slave load current.
The transconductance E/A converts the
V at its inputs in a current equal to
flowing in the compensation network connected between COMP pin and ground.
The E/A output voltage drives the adjust amplifier to sink current from the ADJ pin that is connected to the
output voltage through a small resistor along the sense path. The current sunk by ADJ pin is deviated from
feedback path of the slave power supply that reacts increasing its duty cycle.
In steady state the current sunk by the ADJ pin is proportional to the value of error amplifier output.
4
DESIGNING WITH L6615
The first design step is usually the choice of the sense resistor whose maximum value is limited by power
dissipation; this constraint must be traded off against the precision of L6615 current sensing. In fact a small
sense resistance value lowers the power dissipation but reduces the signal available at the inputs of the
L6615 current sense amplifier.
Once fixed R
SENSE
then the values for R
G
and R
GCA
will be chosen in accordance with the application
specs: usually these specs define the share bus voltage (V
SH(MAX)
) and the number of paralleled power
supplies.
Their value must comply with the constraints imposed by the L6615:
Figure 11. Simplified feedback block diagram.
I
O U T
G
M
V
=
PWM
CONTROLLER
PWM
CONTROLLER
Z
L
I
LOAD
R
SENSE
R
SENSE
+
+
-
-
SHARE BUS
G
M
*Z
COMP
(s)*R
ADJ
R
A
+
-
+
V
REF
K*V
OUT
(*)
G
M
*Z
COMP
(s)*R
ADJ
R
A
+
-
+
V
REF
K*V
OUT
(*)
POWER
STAGE 1
POWER
STAGE 2
V
OUT
* R
CGA
/ R
G
* R
CGA
/ R
G
I
OUT(1)
I
OUT(2)
(*) K depends on the
feedback divider ratio
PWM
CONTROLLER
PWM
CONTROLLER
Z
L
I
LOAD
R
SENSE
R
SENSE
+
+
-
-
SHARE BUS
G
M
*Z
COMP
(s)*R
ADJ
R
A
+
-
+
V
REF
K*V
OUT
(*)
G
M
*Z
COMP
(s)*R
ADJ
R
A
+
-
+
V
REF
K*V
OUT
(*)
POWER
STAGE 1
POWER
STAGE 2
V
OUT
* R
CGA
/ R
G
* R
CGA
/ R
G
I
OUT(1)
I
OUT(2)
(*) K depends on the
feedback divider ratio
11/20
L6615
maximum share bus voltage is internally limited up to 2.2V below L6615 V
CC
voltage (pin#8);
V
SH(MAX)
represents an upper limit but the designer should select the full scale share bus voltage
keeping in mind that every Volt on the share bus will increase the master controller's supply current
by approximately 45
A for each slave unit connected in parallel; this total current, provided by the
master share drive amplifier, must be lower than its minimum output capabilty (8mA) so
This condition is not tough to meet in normal applications, as one can easily see by using sensible
values for N (number of paralleled power supplies) and V
SH(MAX)
. For example, with V
SH(MAX)
=8V,
solving for N, we obtain Nmax=20;
maximum share drive amplifier current capability (I
CGA(MAX)
=2mA);
for safety reasons the following relation must be met:
in this way no fault will cause I
CS+
(or I
CS-
) to overcome its absolute maximum ratings.
At full load,
V
SENSE(MAX)
= I
OUT(MAX
) R
SENSE(MAX)
is the maximum voltage drop across the resistor
R
SENSE
(typically few hundreds of millivolt).
I
OUT(MAX)
is the maximum current carried by each of the paralleled power supply; in non redundant sys-
tems composed by N power supplies, each of them works at its nominal current, so:
This relationship is true also in N+M redundant system, even if under normal condition each power supply
provides I
LOAD
/(N+M).
For example in a system composed by two paralleled power supplies 100% redundant (N=M=1), each
module is sized to sustain the entire load current (in normal operation it carries only one half): for this rea-
son the sense resistor must be sized considering the whole load current.
The temperature variation of the sense resistor (hence of its resistance value) has to be taken into ac-
count, so R
SENSE(MAX)
is the value at maximum operating temperature to avoid saturating the share bus.
Once fixed V
SENSE(MAX)
, the ratio R
CGA
/R
G
(gain from the sensing section to the share bus) can be cal-
culated:
where V
SH(MAX)
is defined by the application.
A small capacitor in parallel to R
CGA
is useful to reduce the noise.
The effect of current sharing feedback loop is to force the voltages of the slave's CGA pins to be equal to
V
SH
(that is to reduce the voltage difference at the inputs of the L6615 error amplifier). For the sake of
simplicity we consider 2 paralleled power supplies (as in fig. 11): under closed loop condition:
Ideally all the external component and
are matched so:
Any mismatch will have repercussion on the sharing precision: in particular the maximum difference be-
tween the output currents (sharing error) will be given by the sum of the mismatches amongst the relevant
values.
V
SH MA X
(
)
R
i MIN
(
)
N
-------------------
8m A
<
R
G
1
2
---
V
out
10m A
----------------
40
>
I
OUT MAX
(
)
I
LOAD
N
----------------
=
R
CGA
R
G
---------------
V
SH MAX
(
)
V
SENSE MAX
(
)
-------------------------------------
=
I
OUT 1
( )
R
SNS 1
( )
R
G 1
( )
----------------------
R
CGA 1
( )
I
OUT 2
( )
R
SNS 2
( )
R
G 2
( )
----------------------
R
CGA 2
( )
=
I
OUT 1
( )
I
OUT 2
( )
I
LOAD
2
----------------
=
=
L6615
12/20
Figure 12. ADJ network
To set the R
ADJ
value it is necessary to know the tolerance required of the power supply output voltage
(V
OUT
V
O
); the maximum difference between master and slave output voltage is 2*
V
O
and this amount
represents the voltage that the L6615 must be able to correct.
Now two different approaches are feasible depending on whether the SMPS (whose output current must
be shared) has to be completely designed or it is an "off the shelf" component and only the current sharing
section must be designed.
In the first case, the adjustment resistor (R
ADJ
) can be considered as a fraction of the high resistor of the
feedback divider R
H
(see fig.12.a): typically the first step consist of fixing the current flowing, under steady
state condition, through the feedback divider I
FB
; by choosing the value for R
2
:
we will have:
It can be an useful rule of thumb to use R
ADJ
lower than (or equal to) one tenth of R1, considering that, in
worst case condition, it will be:
This value must not exceed the one indicated in the "Electrical characteristic section" but this is very easy
to meet, as one can easily see by using sensible values for
V
OUT
and R
2
.
In the second case (fig 12.b), the feedback divider has been already designed by the SMPS manufacturer
and it is not possible to modify it: the design of R
ADJ
must be done to make the L6615 able to correct the
maximum spread without significantly shifting the SMPS regulation point. A minimum R
ADJ
value can be
found by:
where I
ADJ(max)
is 8mA.
Especially for low voltage output buses it is important to avoid adjustment network saturation; the design
must satisfy the following relationship:
where V
ADJ(MIN)
can be found in the "Electrical characteristic section" for different I
ADJ
values.
V
OUT
V
REF
Off the shelf
POWER SUPPLY
R
ADJ
E/A
to L6615
ADJ pin
I
ADJ
V
OUT
V
REF
R
ADJ
E/A
to L6615
ADJ pin
I
ADJ
R
1
R
2
a)
b)
V
OUT
V
REF
Off the shelf
POWER SUPPLY
R
ADJ
E/A
to L6615
ADJ pin
I
ADJ
V
OUT
V
REF
R
ADJ
E/A
to L6615
ADJ pin
I
ADJ
R
1
R
2
a)
b)
I
FB
V
REF
R
2
--------------
=
R
H
R
1
R
ADJ
+
V
OUT
V
REF
---------------
1
R
2
=
=
I
ADJ max
(
)
V
OUT
R
ADJ
------------------
=
R
ADJ min
(
)
V
OUT
I
ADJ ma x
(
)
--------------------------
=
V
OUT
R
ADJ
I
ADJ
I
FB
+
(
)
V
A DJ MIN
(
)
>
13/20
L6615
The last point is the design of the compensation network Z
C
(s) connected between the COMP pin and
ground.
Besides the power supply feedback loop, the current sharing system introduces another, outer loop. To
avoid interaction between them it is important to design the bandwidth of the sharing loop at least one or-
der of magnitude lower than the bandwidth of the power supply loop.
For the total system, the loop gain is:
where
A
PWR
(s) is the transfer function of PWM controller and power stage (see fig. 11)
R
LOAD
is the equivalent load resistance
Typically the compensation network is built by a R-C series.
A resistor in series with C
C
is required to boost the phase margin of the load share loop. The zero is placed
at the load share loop crossover frequency, f
C(SH)
.
If f
C(SH)
is the share loop crossover frequency, then:
5
CURRENT SENSE METHODS
Several are the methods to sense the power supply output current; the simplest one is to use a power
resistor (fig. 13a) but increasing load current could require expensive resistor to support the inherent pow-
er dissipation, imposing the use of several paralleled resistor.
Other methods to sense the output current are showed in fig. 13b and 13c:
1. R
DS(ON)
: a power MOS is placed in series to the output and its channel resistance (R
DS(ON)
) is used
as sense resistor (fig 13a): the L6615 sense pins will be connected, through R
G
resistors to the drain
and to the source of the MOS. Besides providing the sense resistor, the FET is used as "ORing" el-
ement: driving properly its gate, it is possible isolate the power supply output from the load (the body
diode is reversed biased so it doesn't conduct).
This is useful whenever features like hot swap or hot plug are required; compared with the well-known
solution using ORing diode, the ORing FET greatly reduces the power dissipation, in particular:
where V
F
is the forward drop across the diode.
2. Current transformer: in case of very high load currents, a transformer allows sensing a smaller cur-
rent, obtained through a scaling factor equal to the transformer turn ratio. In this way, the sense re-
sistor power dissipation requirements can be less tight: obviously this is paid with the cost of the
transformer.
In fig. 13c it is showed the simplified output stage of a power supply in forward configuration: through
two current transformers the load current is reproduced in the sensing circuit scaled by a factor N.
R
SENSE
will read a ripple (at the switching frequency) superimposed on the average current value
that doesn't affect the correct behaviour of the current sharing system because its loop gain is de-
signed with a low bandwidth - at least 2 order of magnitude lower than the switching frequency - that
will cut this high frequency.
G
LOOP s
( )
R
SENSE
R
CGA
R
G
---------------
G
M
Z
C
s
( )
R
ADJ
R
A
--------------
A
PWR
s
( )
1
R
L OA D
------------------
=
C
C
1
2
f
C SH
(
)
--------------------------------
R
CGA
G
M
R
G
-----------------------------
R
ADJ
R
A
--------------
R
SENSE
R
L OAD
----------------------
A
PW R f
C SH
(
)
(
)
=
R
C
1
2
f
C SH
(
)
C
C
---------------------------------------------
=
P
DIO DE
(
)
V
F
I
OUT
R
SE NSE
I
OUT
2
+
=
P
MOS
(
)
R
DS O N
(
)
I
OUT
2
=
L6615
14/20
Figure 13. Current sense methods.
6
APPLICATION IDEAS
In fig. 14 is showed a single section of a system in which several DC to DC modules can be paralleled,
typical solution whenever the load requires high current at low voltage; the converter is designed for a step
down configuration using a synchronous rectification controller (for example L6910 [1] or L6911 [2] ST de-
vice).
The L6615 reads the drop across the Rds(ON) of the OR-ing FET and the LM293 drives its gate, pulling
it down whenever a fault condition (e.g. short on the low side) appears.
A charge pump could be necessary to be sure that the ORing FET V
GS
is higher than V
GS(TH)
(depending
on the input and output voltage).
Figure 14. 0.9 to 5V DC-Dc converter with Current Sharing and output hot-pluggability
a)
b)
c)
GATE
CONTROL
I
OUT
R
G
R
G
CS+
CS-
L6615
ORing FET
L
O
A
D
I
OUT
R
G
R
G
CS+
CS-
L6615
POWER
SUPPLY
L
O
A
D
R
SNS
POWER
SUPPLY
L
O
A
D
CS+
CS-
L6615
R
SNS
R
G
R
G
I
OUT
1:N
SENSING
CIRCUIT
1:N
GATE
CONTROL
I
OUT
R
G
R
G
CS+
CS-
L6615
ORing FET
L
O
A
D
I
OUT
R
G
R
G
CS+
CS-
L6615
POWER
SUPPLY
L
O
A
D
R
SNS
POWER
SUPPLY
L
O
A
D
CS+
CS-
L6615
R
SNS
R
G
R
G
I
OUT
1:N
SENSING
CIRCUIT
1:N
-SOUT
VOUT
P_GND
VIN
SH
VFB
COMP
BOOT
PGND
6
LM293
4
5
8
7
CS+
CS-
L6615
ADJ
COMP
CGA
GND
+S_OUT
VIN
GND
SS
LGATE
UGATE
PHASE
VCC
Vcc
SH
Q1
R1
L6910
-SOUT
VOUT
P_GND
VIN
SH
VFB
COMP
BOOT
PGND
6
LM293
4
5
8
7
CS+
CS-
L6615
ADJ
COMP
CGA
GND
+S_OUT
VIN
GND
SS
LGATE
UGATE
PHASE
VCC
Vcc
SH
Q1
R1
L6910
15/20
L6615
Figure 15. Distributed power system for +48V bus
In this application is inserted also a circuit for the square current limit protection in case of overcurrent (R1-
Q1): being the voltage at the CGA pin directly proportional to the current carried by the relevant section,
it is possible to set the CGA resistor such that, until the output current is in the right range, the CGA voltage
is lower than V
REF
+0.7. As soon as this value is overcome, then the bipolar pushes current in the feedback
path, reducing the duty cycle and consequently the output voltage.
Current sharing can be required in AC to DC application like distributed power system (DPS) for telecom
applications: if the output voltage is higher than the absolute maximum rating for the current sense pins
(CS+ and CS-) high side sensing can not be performed unless adding other components; the current
sense is performed on the ground return.
To maintain high side sensing two resistor dividers (between the edge of R
SENSE
and ground) could be
introduced to translate the sense signal in the L6615 input pin common mode range.
In fig.15 two AC-DC converters supply the same load through a +48V bus; these converters usually exhibit
also a +12V auxiliary output useful to supply the L6615 whose ADJ pin works on the +48V feedback sec-
tion (COMP pin and CGA pin connections are not showed) in figure 15.
7
LOW VOLTAGE BUSES
The L6615 has a "doubled" sense structure, designed to perform both high side and low side sensing: the
first solution is usually considered more convenient. Actually low side sensing means to split the ground
return as many times as the power supplies paralleled are: on each of these paths it is then necessary to
place the sense resistor introducing a drop between the power supply ground and the common load neg-
ative reference.
The voltage at CS+ pin is read by an internal comparator and compared with a reference corresponding
to the switchover threshold V
THcs+
whose value is typically 1.6V. If such value is overcome, then the com-
parator triggers the High Side Amplifier (HSA); being the threshold provided by hysteresis, then the Low
Side Amplifier (LSA) will be triggered as VCS+ is lower than 1.44V (typ.).
Hence V
THcs+
defines the threshold between the operating range of LSA, (referring to fig.10) and the op-
erating range of HSA; usually LSA is operating when the sense resistor is placed on the ground return,
between the negative load terminal and the negative power supply output (fig 10.b) and HSA when the
sense resistor is placed between the power supply positive output and the load.
It is however possible to perform high side sensing for applications whose output voltage is close to V
THcs+
threshold (or even lower) exploiting the low sense internal structure (LSA).
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L
O
A
D
+48V
+48V
SH bus
+12V
+12V
SH
Vcc
CS-
CS+
Vcc
CS-
CS+
SH
L6615
R
G
R
G
R
G
R
G
R
SNS
R
SNS
AC
Mains
AC
Mains
AC
Mains
+48V GND
+48V GND
DPS1
DPS2
ADJ
ADJ
+48V (*)
feedback
+48V (*)
feedback
I
OUT1
I
OUT2
GND
GND
L6615
(*) the center of the
output feedback divider
is usually connected to
a voltage compatible
with L6615 AMR
L6615
16/20
Consider, for example an application with V
OUT
= 1.2V and the sense resistor placed high side; the voltage
at CS+:
V
CS+
= V
OUT
-
V
SENSE
is lower than 1.6V so the internal comparator triggers on the LSA structure and the pin CS- sources the
current I
CS
(see paragraph "2. CURRENT SENSE SECTION"). The IC works properly because the dy-
namics of LSA spreads down to zero: in this case it is necessary to pay attention to the design of ADJ
network.
Now consider, for example, an application with V
OUT
=1.5V where, because of the drop across R
SNS
, the
voltage at CS+ pin could be very close to the threshold: if such voltage is overcome (start-up, load regu-
lation, overvoltage,...) , then the HSA structure will be activated; as nominal conditions are restored, the
hysteresis will then keep HSA active (unless V
CS+
falls under the lower threshold).
8
OFFSET TRIMMING
The current sharing accuracy strongly depends on the unbalance between the relevant parameters of the
paralleled sections. Each percentage point on the relevant parameters tolerance introduces a maximum
error equal to the double of the tolerance.The L6615 introduces an inherent error in current sharing due
to the 40mV offset at the negative input of the error amplifier; this offset is necessary to guarantee the low
value of the master COMP pin.
Considering perfectly matched all other parameters, the offset introduces a percentage error equal to 4%
divided by the voltage on the share bus. In particular:
Being V
SH
directly proportional to the load current and fixed the ratio R
CGA
/R
G
, higher are the currents
involved in the sharing, lower is the error.
Another error is introduced by the current sense amplifier due to its input offset whose amplitude can be
1mV: being typically the drop across R
SNS
about one hundred mV at full load, the offset could lead to an
error of some percentage point.
Whenever the application requires very high current sharing accuracy, it is possible to correct these offsets
through a triggering process, introducing a trimmer (R
K
) between current sense input pins.
Referring to fig. 16, in case of high side sensing, the equations governing the circuit are:
V
P
= V
M
+ V
O
where V
O
is the current sense amplifier input offset.
Solving for I
G
, we get:
Ideally I
G
should be equal only to the first term: this current will be sunk by CS+ pin, internally mirrored
with 1:1 ratio and sent to CGA pin.
Imposing that the sum of two latter terms is zero it is possible to find the value of
deleting the effect of
the offset:
I
SLAV E
I
MAST ER
1
40m A
V
S H
----------------
=
V
OUT
V
M
R
G
-----------------------------
V
M
1
(
)
R
K
-----------------------------
=
V
OUT
V
SENSE
V
P
+
R
G
---------------------------------------------------------
V
P
R
K
---------------
I
G
=
I
G
V
SENSE
R
G
----------------------
R
K
R
G
+
R
K
R
G
------------------------------
V
O
V
OUT
2
1
R
K
1
(
)
R
G
+
[
]
--------------------------------------------------------
+
=
OPT
1
2
---
2 V
OUT
R
G
4 V
OUT
2
R
G
2
V
O
2
R
K
2
4 V
O
2
R
G
R
K
+
+
2 V
O
R
K
------------------------------------------------------------------------------------------------------------------------------------------------------------
=
17/20
L6615
Figure 16. Offset Trimming
Because of the tolerance of the output voltage, it is not possible to delete completely the effect of the offset
on CGA pin on all the allowed output voltage range: if the trimming operation is performed at V
OUT(MIN)
,
then on pin CGA the maximum residual voltage will be present at V
OUT(MAX)
and its value will be:
To simplify the procedure, the following step-by step process can be used:
s
a trimmer has to be placed between sense pins of each section: the value of the trimmer resistance
must be at least one order of magnitude higher than R
G
and it has to be set at one half of its range
(
=0.5);
s
once the application is running at a load defined by the designer based on the required sharing
accuracy, the master section has to be located;
s
on the slave sections it is then necessary to operate on the trimmer to make equal the output currents.
REFERENCE
[1] "L6910 - Adjustable step down controller with synchronous rectification" (Datasheet)
[2] "L6911 - 5 bit programmable step down controller with synchronous rectification" (Datasheet
I
LOAD
L6615
CS-
CS+
R
CGA
CGA
R
G
R
G
R
K
(
1-
)
R
K
V
OUT
+V
SENSE
V
OUT
+
_
R
SNS
I
G
V
M
V
P
I
LOAD
L6615
CS-
CS+
R
CGA
CGA
R
G
R
G
R
K
(
1-
)
R
K
V
OUT
+V
SENSE
V
OUT
+
_
R
SNS
I
G
V
M
V
P
R
CGA
V
OUT MAX
(
)
V
OUT MIN
(
)
(
)
1
2
OPT
OPT
R
K
OPT
R
K
R
G
(
)
-----------------------------------------------------------------------------
L6615
18/20
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.32
0.131
a1
0.51
0.020
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
D
10.92
0.430
E
7.95
9.75
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
3.18
3.81
0.125
0.150
Z
1.52
0.060
Minidip
19/20
L6615
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.069
a1
0.1
0.25
0.004
0.010
a2
1.65
0.065
a3
0.65
0.85
0.026
0.033
b
0.35
0.48
0.014
0.019
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.020
c1
45
(typ.)
D (1)
4.8
5.0
0.189
0.197
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
3.81
0.150
F (1)
3.8
4.0
0.15
0.157
L
0.4
1.27
0.016
0.050
M
0.6
0.024
S
8
(max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
SO8
OUTLINE AND
MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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