1/23
L6668
May 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
General Features
MULTIPOWER BCD TECHNOLOGY
LOAD-DEPENDENT CURRENT-MODE CON-
TROL: FIXED-FREQUENCY (HEAVY LOAD),
FREQUENCY FOLDBACK (LIGHT LOAD),
BURST-MODE (NO-LOAD)
ON-BOARD HIGH-VOLTAGE START-UP
IMPROVED STANDBY FUNCTION
LOW QUIESCENT CURRENT (< 2 mA)
SLOPE COMPENSATION
PULSE-BY-PULSE & HICCUP-MODE OCP
INTERFACE WITH PFC CONTROLLER
DISABLE FUNCTION (ON/OFF CONTROL)
LATCHED DISABLE FOR OVP/OTP FUNC-
TION
PROGRAMMABLE SOFT-START
2% PRECISION REFERENCE VOLTAGE EX-
TERNALLY AVAILABLE
800 mA TOTEM POLE GATE DRIVER WITH
INTERNAL CLAMP AND UVLO PULL-DOWN
BLUE ANGEL, ENERGY STAR, EU CODE OF
CONDUCT COMPLIANT
SO16 PACKAGE ECOPACK
1.1 APPLICATIONS
HI-END AC-DC ADAPTERS/CHARGERS FOR
NOTEBOOKS.
LCD/CRT MONITORS, LCD/CRT TV
DIGITAL CONSUMER
Figure 2. Block Diagram
16
Vref
+
-
1.5V
12
BLANKING
R
S
Q
25V
Vcc_OK
DIS
0.8V
4R
11R
DIS
11
10
3
4
8
5
15
15V
CLK
COMP
SS
ISEN
RCT
S-COMP
V
CC
VREF
GND
OUT
HICCUP
13
SLOPE
COMP.
VREG
VREG
0.4mA
TIMING
PWM
+
-
1
HV
ST-BY
HV generator ON/OFF
and UVLO management
Vcc_OK
14
PFC_STOP
2.2/2.7V
-
+
OCP
DIS
OCP
-
+
9
SKIPADJ
SOFT-START
HYST. CTRL
S
Q
R
S
Q
R
STANDBY
2.2V
7
DIS
-
+
6
N.C.
16
Vref
+
-
1.5V
12
BLANKING
R
S
Q
25V
Vcc_OK
DIS
0.8V
4R
11R
DIS
11
10
3
4
8
5
15
15V
CLK
COMP
SS
ISEN
RCT
S-COMP
V
CC
VREF
GND
OUT
HICCUP
13
SLOPE
COMP.
VREG
VREG
0.4mA
TIMING
PWM
+
-
1
HV
ST-BY
HV generator ON/OFF
and UVLO management
Vcc_OK
14
PFC_STOP
2.2/2.7V
-
+
OCP
DIS
OCP
-
+
9
SKIPADJ
SOFT-START
HYST. CTRL
S
Q
R
S
Q
R
STANDBY
2.2V
7
DIS
-
+
6
N.C.
PRELIMINARY DATA
SMART PRIMARY CONTROLLER
Rev. 1
Figure 1. Package
Table 1. Order Codes
Part Number
Package
L6668
SO-16
L6668TR
SO-16 in Tape & Reel
SO-16 (Narrow)
L6668
2/23
2
Description
L6668 is a current-mode primary controller IC, designed to build single-ended converters.
The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a
smooth frequency reduction as the load is progressively reduced. At very light load the device enters a
special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to
the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption
from the mains and be compliant with energy saving regulations. To allow meeting compliance with these
standards in power-factor-corrected systems too, an interface with the PFC controller is provided that en-
ables to turn off the pre-regulator when the load level falls below a threshold.
The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles
greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity,
latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even
in case the secondary diode fails short.
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Figure 3. Pin Connection (Top view)
Symbol
Pin
Parameter
Value
Unit
V
cc
5
IC Supply voltage (Icc = 20 mA)
Self-limited
V
V
HV
1
High-voltage start-up generator voltage range
-0.3 to 700
V
I
HV
1
High-voltage start-up generator current
Self-limited
A
---
Analog Inputs & Outputs, except pin 14
-0.3 to 8
V
I
PFC_STOP
14
Max. sink current (low state)
2
mA
V
PFC_STOP
14
Max. voltage (open state)
16
V
P
tot
Power Dissipation @Tamb = 50C
0.75
W
T
j
Junction Temperature Operating range
-25 to 150
C
T
stg
Storage Temperature
-55 to 150
C
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to AmbientMax
120
C/W
VREF
SKIPADJ
HV
HVS
GND
OUT
Vcc
N.C.
DIS
RCT
S-COMP
PFC_STOP
STBY
ISEN
SS
COMP
VREF
SKIPADJ
HV
HVS
GND
OUT
Vcc
N.C.
DIS
RCT
S-COMP
PFC_STOP
STBY
ISEN
SS
COMP
3/23
L6668
Table 4. Pin Description
Pin
Number
Pin Name
Function
1
HV
High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A
0.8 mA internal current source charges the capacitor connected between pin Vcc and GND
to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the gen-
erator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below
5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls
0.5V below the start-up threshold.
2
HVS
High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and
comply with safety regulations (creepage distance) on the PCB.
3
GND
Chip ground. Current return for both the gate-drive current and the bias current of the IC. All
of the ground connections of the bias components should be tied to a track going to this pin
and kept separate from any pulsed current return.
4
OUT
Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive
MOSFET's. The voltage delivered to the gate is clamped at about 15V so as to prevent too
high values when the IC is supplied with a voltage close to or exceeding 20V.
5
Vcc
Supply Voltage of both the signal part of the IC and the gate driver. The internal high volt-
age generator charges an electrolytic capacitor connected between this pin and GND as
long as the voltage on the pin is below the start-up threshold of the IC, after that it is dis-
abled. Sometimes a small bypass capacitor (0.1F typ.) to GND might be useful to get a
clean bias voltage for the signal part of the IC.
6
N.C.
Connect the pin to GND.
7
DIS
Latched device shutdown. Internally the pin connects a comparator that, when the voltage
on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely
higher than before start-up. The information is latched and it is necessary to recycle the
input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below
the UVLO threshold. Connect the pin to GND if the function is not used.
8
VREF
Voltage reference. An internal generator furnishes an accurate voltage reference (5V4%,
all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film
capacitor (0.1F typ.), connected between this pin and GND is recommended to ensure the
stability of the generator and to prevent noise from affecting the reference.
9
SKIPADJ
Burst-mode control threshold. A voltage is applied to this pin, derived from the reference
voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV
below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip
is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage
start-up generator is not invoked. The function is disabled during the soft-start ramp. The
pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables
the function, if the pin is pulled below 0.8V the IC is shut down.
10
COMP
Control input for PWM regulation. The pin is to be driven by the phototransistor (emitter-
grounded) of an optocoupler to modulate the voltage by modulating the current sunk from
(sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor
between the pin and GND, as close to the IC as possible to reduce switching noise pick up,
to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on
pin SKIPADJ shuts down the IC and reduces its current consumption.
11
SS
Soft start. An internal 20A generator charges an external capacitor connected between
the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin
COMP during start-up, thus the duty cycle of the power switch starts from zero. During the
ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is
quickly discharged as the chip goes into UVLO.
12
ISEN
Current sense (PWM comparator) input. The voltage on this pin is internally compared with
an internal reference derived from the voltage on pin COMP and when they are equal the
gate drive output (previously asserted high by the clock signal generated by the oscillator)
is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking
time for improved noise immunity. A second comparison level located at 1.5V shuts the
device down and brings its consumption almost to a "before start-up" level.
L6668
4/23
13
STBY
Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is
higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks
that on pin COMP and is capable of sinking current. A resistor connected from the pin to the
oscillator allows programming frequency foldback at light load.
14
PFC_STOP
Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a
PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at
light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower
than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the
IC is shutdown, either latched (DIS>1.5V, ISEN >1.5V) or not (UVLO, SKIPADJ<0.8), the
pin is open as well.
15
S-COMP
Voltage ramp for slope compensation. When the gate-drive output is high the pin delivers a
voltage tracking the oscillator ramp (shifted down by one V
BE
); when the gate-drive output
is low the voltage delivered is zero. The pin is to be connected to pin ISEN via a resistor to
make slope compensation and allow stable operation at duty cycles close to and greater
than 50%.
16
RCT
Oscillator pin. A resistor to VREF and a capacitor to GND define the oscillator frequency (at
full load). A resistor connect to STBY modifies the oscillator frequency when the voltage on
pin COMP is lower than 3V.
Table 5. Electrical Characteristcs
(T
j
= 0 to 105C, Vcc=15V, Co=1nF; R
T
=13.3k , C
T
=1nF; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
Vcc
Operating range
After turn-on
9.4
22
V
V
CCOn
Turn-on threshold
(1)
12.5
13.5
14.5
V
V
CCOff
Turn-off threshold
(1)
After turn-on
8.0
8.7
9.4
V
Hys
Hysteresis
4.0
V
V
Z
Zener Voltage
Icc = 20 mA
22
24
28
V
SUPPLY CURRENT
I
start-up
Start-up Current
Before turn-on,
Vcc=Vcc
ON
-0.5
150
A
I
q
Quiescent Current
After turn-on
2
2.5
mA
I
CC
Operating Supply Current
4
mA
I
qdis
Shutdown quiescent
current
V
DIS
> 2.2, or V
ISEN
> 1.5
180
A
V
SKIPADJ
<0.8
1
1.8
mA
0.8 <V
COMP
< V
SKIPADJ
1.3
mA
HIGH-VOLTAGE START-UP GENERATOR
V
HV
Breakdown voltage
I
HV
< 100 A
700
V
V
HVstart
Start voltage
I
Vcc
< 100 A
50
80
110
V
I
charge
Vcc charge current
V
HV
> V
Hvstart
, Vcc > 3V
0.55
0.85
1
mA
I
HV, ON
ON-state current
V
HV
> V
Hvstart
, Vcc > 3V
1.6
mA
V
HV
> V
Hvstart
, Vcc = 0
0.8
I
HV, OFF
Leakage current (OFF state)
V
HV
= 400 V
40
A
V
CCrestart
HV generator restart voltage
4.4
5
5.6
V
(1)
After DIS tripping
12
13
14
V
Table 4. Pin Description (continued)
Pin
Number
Pin Name
Function
5/23
L6668
REFERENCE VOLTAGE
V
REF
Output voltage
(2)
Tj = 25 C; I
REF
= 1 mA
4.925
5
5.075
V
V
REF
Total variation
Vcc= 9.4 to 22 V,
I
REF
= 1 to 5 mA
4.8
5.13
V
I
REF
Short circuit current
V
REF
= 0
10
30
mA
Sink capability in UVLO
Vcc = 6V; Isink = 0.5 mA
0.2
0.5
V
PWM CONTROL
V
COMP
H
Maximum level
I
COMP
=0
5.5
V
I
COMP
Max. source current
V
COMP
= 1 V
320
400
480
A
R
COMP
Dynamic resistance
V
COMP
= 2 to 4 V
22
k
D
max
Maximum duty cycle
V
COMP
= 5 V
70
75
%
D
min
Minimum duty cycle
V
COMP
= 1 V
0
%
CURRENT SENSE COMPARATOR
I
ISEN
Input Bias Current
V
ISEN
= 0
-1
A
t
LEB
Leading Edge Blanking
After gate drive low-to-high
transition
160
225
290
ns
t
d(H-L)
Delay to Output
100
ns
Gain
3.56
3.75
3.94
V/V
V
ISENx
Maximum signal
V
COMP
= 5 V
0.725
0.8
0.875
V
V
ISENdis
Hiccup-mode OCP level
(2)
1.35
1.5
1.65
V
STANDBY FUNCTION
V
drop
V
COMP
- V
STBY
I
STBY
= 0.8 mA, V
COMP
<3V
35
mV
V
th
Threshold on V
COMP
(2)
Voltage falling
3
V
Hysteresis
50
mV
LATCHED DISABLE FUNCTION
I
DIS
Input Bias Current
V
DIS
= 0 to Vth
-1
A
Vth
Disable threshold
(2)
voltage rising
2.1
2.2
2.3
V
OSCILLATOR
fsw
Oscillation Frequency
Tj = 25C, V
COMP
= 5 V
95
100
105
kHz
Vcc = 9.4 to 22V, V
COMP
= 5 V
93
100
107
kHz
Vpk
Oscillator peak voltage
(2)
2.85
3
3.15
V
Vvy
Oscillator valley voltage
(2)
0.75
0.9
1.05
V
SLOPE COMPENSATION
S-COMP
pk
Ramp peak
R
S-COMP
= 3 k
to GND,
OUT pin high, V
COMP
= 5 V
1.6
1.75
1.9
V
S-COMP
vy
Ramp starting value
R
S-COMP
= 3 k
to GND,
OUT pin high
0.15
0.35
0.55
V
Ramp voltage
OUT pin low
0
Source capability
V
S-COMP
=
V
S-COMPpk
0.8
mA
SOFT-START
I
SSC
Charge current
Tj = 25 C
14
20
26
A
Table 5. Electrical Characteristcs (continued)
(T
j
= 0 to 105C, Vcc=15V, Co=1nF; R
T
=13.3k , C
T
=1nF; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
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