1/17
L6911D
November 2001
s
OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES
s
UP TO 1.3A GATE CURRENT CAPABILITY
s
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 9.0 :
1.100V TO 1.850V WITH 0.025V BINARY
STEPS
s
VOLTAGE MODE PWM CONTROL
s
EXCELLENT OUTPUT ACCURACY: 1%
OVER LINE AND TEMPERATURE
VARIATIONS
s
VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE
s
POWER GOOD OUTPUT VOLTAGE
s
OVERVOLTAGE PROTECTION AND
MONITOR
s
OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET'S R
dsON
s
200KHz INTERNAL OSCILLATOR
s
OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz
s
SOFT START AND INHIBIT FUNCTIONS
APPLICATIONS
s
POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE
s
DISTRIBUTED POWER SUPPLY
s
HIGH POWER DC-DC REGULATORS
DESCRIPTION
The device is a power supply controller specifically de-
signed to provide a high performance DC/DC conver-
sion for high current microprocessors. A precise 5-bit
digital to analog converter (DAC) allows adjusting the
output voltage from 1.30V to 2.05V with 50mV binary
steps and from 2.10V to 3.50V with 100mV binary steps.
The high precision internal reference assures the se-
lected output voltage to be within 1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
The device assures a fast protection against load
overcurrent and load overvoltage. An external SCR is
triggered to crowbar the input supply in case of hard
over-voltage. An internal crowbar is also provided
turning on the low side mosfet as long as the over-
voltage is detected. In case of over-current detection,
the soft start capacitor is discharged and the system
works in HICCUP mode.
SO-20
ORDERING NUMBERS: L6911D
L6911DTR (Tape and Reel)
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
BLOCK DIAGRAM
PGND
PHASE
GND
VFB
LGATE
BOOT
UGATE
VCC
OCSET
Vcc 5 to 12V
Vin 5V to12V
Vo
1.100V to 1.850V
PGOOD
COMP
VSEN
SS
OVP
RT
VD0
VD1
VD2
VD3
VD4
MONITOR and
PROTECTION
OSC
D/A
E/A
PWM
+
-
-
+
D98IN957_2
L6911D
2/17
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION (Top view)
Symbol
Parameter
Value
Unit
V
CC
V
CC
to GND, PGND
15
V
V
BOOT
-V
PHASE
Boot Voltage
15
V
V
HGATE
-V
PHASE
15
V
OCSET, LGATE, PHASE
-0.3 to Vcc+0.3
V
RT, SS, FB, PGOOD, VSEN, VID0-4
7
V
OVP, COMP
6.5
V
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
110
C/W
T
j
Maximum junction temperature
150
C
T
stg
Storage temperature range
-40 to 150
C
T
J
Junction temperature range
0 to 125
C
VSEN
OCSET
SS/INH
VID0
VID1
VID3
VID2
VID4
COMP
PGOOD
PHASE
UGATE
PGND
BOOT
LGATE
VCC
OVP
RT
1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
FB
GND
D98IN958
3/17
L6911D
PIN FUNCTION
Pin
Num.
Name
Description
1
VSEN
Connected to the output voltage is able to manage over-voltage conditions and the PGOOD
signal.
2
OCSET
A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
The internal 200
A current generator sinks a current from the drain through the external resistor.
The Over-Current threshold is due to the following equation:
3
SS/INH
The soft start time is programmed connecting an external capacitor from this pin and GND. The
internal current generator forces through the capacitor 10
A.
This pin can be used to disable the device forcing a voltage lower than 0.4V
4 - 8
VID0 - 4
Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They
are used to program the output voltage as specified in Table 1 and to set the overvoltage and
power good thresholds.
Connect to GND to program a `0' while leave floating to program a `1'.
9
COMP
This pin is connected to the error amplifier output and is used to compensate the voltage control
feedback loop.
10
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
11
GND
All the internal references are referred to this pin. Connect it to the PCB signal ground.
12
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
13
PHASE
This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver. This pin monitors the drop across the upper mosfet for the current limit
14
UGATE
High side gate driver output.
15
BOOT
Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot).
16
PGND
Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
reduce the noise injection into the device
17
LGATE
This pin is the lower mosfet gate driver output
18
VCC
Device supply voltage. The operative nominal supply voltage ranges from 5 to 12V.
DO NOT CONNECT V
IN
TO A VOLTAGE GREATER THAN V
CC
.
19
OVP
Over voltage protection. If the output voltage reaches the 17% above the programmed voltage
this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage.
If not used, it may be left floating.
20
RT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
If the pin is not connected, the switching frequency is 200KHz.
The voltage at this pin is fixed at 1.23V (typ). Forcing a 50
A current into this pin, the built in
oscillator stops to switch.
I
P
I
OC SE T
R
O CS ET
R
DS on
----------------------------------------------
=
f
S
200kHz
4.94 10
6
R
T
k
(
)
-------------------------
+
=
f
S
200kHz
4.306 10
7
R
T
k
(
)
-----------------------------
=
L6911D
4/17
ELECTRICAL CHARACTERISTCS (V
CC
= 12V, T
amb
= 25C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
CC
SUPPLY CURRENT
Icc
Vcc Supply current
UGATE and LGATE open
5
mA
POWER-ON
Turn-On Vcc threshold
VOCSET=4.5V
4.6
V
Turn-Off Vcc threshold
VOCSET=4.5V
3.6
V
Rising V
OCSET
threshold
1.24
V
I
SS
Soft start Current
10
A
OSCILLATOR
Free running frequency
R
T
= OPEN
180
200
220
KHz
Total Variation
6 K
< RT to GND < 200 K
-15
15
%
V
osc
Ramp amplitude
R
T
= OPEN
1.9
Vp-p
REFERENCE AND DAC
DACOUT Voltage
Accuracy
VID0, VID1, VID2, VID3, VID4
see Table1; Tamb = 0 to 70
C
-1
1
%
VID Pull-Up voltage
4
V
ERROR AMPLIFIER
DC Gain
88 dB
GBWP
Gain-Bandwidth Product
10
MHz
SR
Slew-Rate
COMP=10pF
10
V/
S
GATE DRIVERS
I
UGATE
High Side Source
Current
V
BOOT
- V
PHASE
=12V,
V
UGATE
- V
PHASE
= 6V
1
1.3
A
R
UGATE
High Side Sink
Resistance
V
BOOT
-V
PHASE
=12V,
I
UGATE
= 300mA
2
4
I
LGATE
Low Side Source
Current
Vcc=12V, V
LGATE
= 6V
0.9
1.1
A
R
LGATE
Low Side Sink
Resistance
Vcc=12V, I
LGATE
= 300mA
1.5
3
Output Driver Dead Time
PHASE connected to GND
120
ns
PROTECTIONS
Over Voltage Trip
(V
SEN
/DACOUT)
V
SEN
Rising
117
120
%
I
OCSET
OCSET Current Source
V
OCSET
= 4.5V
170
200
230
A
I
OVP
OVP Sourcing Current
V
SEN
> OVP Trip, V
OVP
=0V
60
mA
POWER GOOD
Upper Threshold
(V
SEN
/DACOUT)
V
SEN
Rising
110
112
114
%
Lower Threshold
(V
SEN
/DACOUT)
V
SEN
Falling
86
88
90
%
Hysteresis
(V
SEN
/DACOUT)
Upper and Lower threshold
2
%
V
PGOOD
PGOOD Voltage Low
I
PGOOD
= -5mA
0.5
V
5/17
L6911D
Table 1. VID Settings
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N-Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc rang-
ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.100V to 1.850V
with 25mV binary steps, with a maximum tolerance of 1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz.
The error amplifier features a 15MHz gain-bandwidth product and 10V/
s slew rate which permits high convert-
er bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device
protects against over-current conditions entering in HICCUP mode. The device monitors the current by using
the r
DS(ON)
of the upper MOSFET which eliminates the need for a current sensing resistor.
The device is available in SO20 package
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50
A (Fsw=200KHz) and may be varied using an external resistor (R
T
) connected between
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sunk (forced) from (into) the pin.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), according to the
following relationship:
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
VID4 VID3
VID2
VID1
VID0
Output
Voltage (V)
VID4 VID3
VID2
VID1
VID0
Output Voltage
(V)
1
1
1
1
1
Output OFF
0
1
1
1
1
1.475
1
1
1
1
0
1.100
0
1
1
1
0
1.500
1
1
1
0
1
1.125
0
1
1
0
1
1.525
1
1
1
0
0
1.150
0
1
1
0
0
1.550
1
1
0
1
1
1.175
0
1
0
1
1
1.575
1
1
0
1
0
1.200
0
1
0
1
0
1.600
1
1
0
0
1
1.225
0
1
0
0
1
1.625
1
1
0
0
0
1.250
0
1
0
0
0
1.650
1
0
1
1
1
1.275
0
0
1
1
1
1.675
1
0
1
1
0
1.300
0
0
1
1
0
1.700
1
0
1
0
1
1.325
0
0
1
0
1
1.725
1
0
1
0
0
1.350
0
0
1
0
0
1.750
1
0
0
1
1
1.375
0
0
0
1
1
1.775
1
0
0
1
0
1.400
0
0
0
1
0
1.800
1
0
0
0
1
1.425
0
0
0
0
1
1.825
1
0
0
0
0
1.450
0
0
0
0
0
1.850
f
S
200kH z
4.94 10
6
R
T
k
(
)
-------------------------
+
=
L6911D
6/17
V
CC
= 12V
V
CC
= 5V
Switching frequency variations vs. R
T
are reported in Fig.1.
Note that forcing a 50
A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1.
Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.30V to 2.05V with
50mV binary steps and from 2.10V to 3.50V with 100mV binary steps as shown in the previous table 1. The
internal reference is trimmed to ensure the precision of 1%.
The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a par-
tition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the V
PROG
voltage reference (i.e. the
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5
A current generator); in this
way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short
the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
The VID code "11111" disable the device (as a short on the SS pin) and no output voltage is regulated.
Soft Start and Inhibit
At start-up a ramp is generated charging the external capacitor C
SS
by means of a 10A constant current, as
shown in figure 1.
When the voltage across the soft start capacitor (V
SS
) reaches 0.5V the lower power MOS is turned on to dis-
f
S
200kH z
4.306 10
7
R
T
k
(
)
-----------------------------
+
=
f
S
200kH z
15 10
7
R
T
k
(
)
--------------------
+
=
1 0
1 0 0
1 0 0 0
F re q u e n cy [kH z]
1 0
10 0
1 00 0
1 0 00 0
R
e
si
st
a
n
c
e
[
k
O
h
m
]
R T to G N D
R T to V C C =1 2 V
R T to V C C =5 V
7/17
L6911D
charge the output capacitor. As V
SS
reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper
MOS begins to switch and the output voltage starts to increase.
The V
SS
growing voltage initially clamps the output of the error amplifier, and consequently V
OUT
linearly in-
creases, as shown in figure 2. In this phase the system works in open loop. When V
SS
is equal to V
COMP
the
clamp on the output of the error amplifier is released. In any case another clamp on the input of the error ampli-
fier remains active, allowing to V
OUT
to grow with a lower slope (i.e. the slope of the V
SS
voltage, see figure 2).
In this second phase the system works in closed loop with a growing reference. As the output voltage reaches
the desired value V
PROG
, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss
increases until a maximum value of about 4V.
The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of
the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept
off.
Figure 2. Soft Start
Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the R
DSON
), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.
The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 4nF capacitive
load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot-
Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
V cc Turn-on thre sh old
V in Turn-o n threshold
0.5 V
1V
V cc
Vin
V ss
LGATE
Vo ut
to G ND
Timing Diagram
Aquisition: CH1 = PHASE; CH2 = V
OUT
;
CH3 = PGOOD; CH4 = V
SS
L6911D
8/17
Figure 3. High Side driver peak current. Vboot-Vphase=12V (left) Vboot-Vphase=5V (right)
Figure 4. Low Side driver peak current. Vcc=12V (left) Vcc=5V (right)
Monitoring and Protections
The output voltage is monitored by means of pin 1 (VSEN). If it is not within 12% (typ.) of the programmed
value, the powergood output is forced low.
The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) grater than the
nominal one. If the output voltage exceeds this threshold, the OVP pin is forced high, triggering an external SCR
to shuts the supply (VIN) down, and also the lower driver is turned on as long as the over-voltage is detected.
To perform the overcurrent protection the device compares the drop across the high side MOS, due to the
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of
the upper MOS. Thus the overcurrent threshold (I
P
) can be calculated with the following relationship:
Where the typical value of I
OCS
is 200
A. To calculate the ROCS value it must be considered the maximum
R
DSON
(also the variation with temperature) and the minimum value of I
OCS
. To avoid undesirable trigger of
CH1 = High Side Gate
CH4 = Gate Current
CH1 = Low Side Gate
CH4 = Gate Current
I
P
I
O C S
R
O C S
R
D S O N
---------------------------------
=
9/17
L6911D
overcurrent protection this relationship must be satisfied:
Where
I is the inductance ripple current and I
OUTMAX
is the maximum output current.
In case of output short circuit the soft start capacitor is discharged with constant current (10
A typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-
charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 5.
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where f
SW
is the switching frequency, V
IN
is the input voltage and V
OUT
is the output voltage. Figure 5b shows
the ripple current vs. the output voltage for different values of the inductor, with V
IN
= 5V and V
IN
= 12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for
I load transient in case of enough fast compensation network response:
I
P
I
O U T MAX
l
2
-----
+
I
PEA K
=
0
1
2
3
4
5
6
7
8
9
0 .5
1 .5
2 .5
3 .5
O utput Voltage [V ]
Inductor Ripple [A]
L=3
H,
Vin=12V
L=2
H,
Vin=12V
L=1.5
H, Vin=12V
L=2
H,
Vin=5V
L=1.5
H,
Vin=5V
L=3
H, Vin=5V
a: Hiccup Mode
b: Inductor Ripple Current vs. Vout
L
V
IN
V
O U T
f
S
I
L
------------------------------
V
OU T
V
IN
---------------
=
L6911D
10/17
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Output Capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/
sec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
V
OUT
=
I
OUT
ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where D
MAX
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
Compensation network design
The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-
inal level, while at high load the output voltage will be lower than the nominal value.
t
a pplic atio n
L
I
V
IN
V
O U T
------------------------------
=
t
rem ov al
L
I
V
O U T
---------------
=
V
O U T
I
O U T
2
L
2 C
OU T
V
IN M IN
D
M AX
V
O U T
(
)
---------------------------------------------------------------------------------------------
=
I
rm s
I
O U T
D
1
D
(
)
=
P
ESR I
rm s
2
=
11/17
L6911D
Figure 6. Output transient response without (a) and with (b) the droop function
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
the intrinsic resistance of the inductance (a few m
). So the low-pass filtered inductor voltage (that is the induc-
tor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
Where V
PROG
is the output voltage of the digital to analog converter (i.e. the set point) and R
L
is the inductance
resistance. The second term of the equation allows a positive offset at zero load (
V
+
); the third term introduces
the droop effect (
V
DROOP
). Note that the droop effect is equal the ESR drop if:
Figure 7. Compensation network
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
s
Choose a value for R2 in the range of hundreds of K
to obtain realistic values for the other
components.
V
MAX
V
MIN
V
NOM
(a)
(b)
ESR DROP
ESR DROP
V
DROOP
V
O U T
V
P R O G
V
P R O G
R3
R 8 // R9
+
R2
-------------------------------------
R
L
R8 // R9
R8
-----------------------------------
I
O U T
+
=
R
L
R 8 // R9
R8
-----------------------------------
ESR
=
C 1 8
C 2 0
R 4
R 3
R 9
L 2
E S R
C 6 - 1 5
R 8
R 2
P W M
C 2 5
V
I N
V
P R O G
R
L
Z
F
Z
I
V
O U T
V
P H A S E
V
C O M P
L6911D
12/17
s
From the above equations, it results:
;
;
Where I
MAX
is the maximum output current.
s
The component R3 must be chosen in order to obtain R3<<R8//R9 to permit these and successive
simplifications.
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output
impedance is equal to a resistance R
OUT
. It is easy to verify that the output voltage deviation under load tran-
sient is minimum when the output impedance is constant with frequency.
To choose the other components of the compensation network, the transfer function of the voltage loop is con-
sidered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9).
Figure 8. Compensation network definition
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later,
this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this as-
sumption, the voltage loop has the following transfer function:
R8
V
+
R 2
V
P R O G
-----------------------
R
L
I
M AX
V
D R OO P
---------------------------
=
R9
R8
=
V
D R O O P
R
L
I
M AX
---------------------------
1
1
V
D R O O P
R
L
I
M AX
---------------------------
+
-------------------------------------
| A v |
|R |
|G lo o p |
f
f
f
fc
f
D
f
2
f
1
f
3
R
0
2
f
L C
f
C E
f
E C
f
C C
G
0
acitor
CeramicCap
Cceramic
Rceramic
CC
f
by
Introduced
Cceramic
ESR
EC
f
ESRzero
OUT
C
ESR
CE
f
doublepole
LC
LC
f
ingularity
ConverterS
=
=
=
=
2
/
1
2
/
1
2
/
1
2
/
1
25
2
/
1
25
3
2
/
1
3
20
)
4
3
(
2
/
1
2
20
4
2
/
1
1
C
Rd
d
f
C
R
f
C
R
R
f
C
R
f
ingularity
onNetworkS
Compensati
=
=
+
=
=
13/17
L6911D
Where
Where Z
C
(s) and Z
L
(s) are the output capacitor and inductor impedance respectively.
The expression of Z
I
(s) may be simplified as follow:
Where:
1
= R4C20,
2
= (R4+R3)C20 and
d
= RdC25.
The regulator transfer function became now:
Figure 8 shows a method to select the regulator components (please note that the frequencies f
EC
and f
CC
cor-
responds to the singularities introduced by additional ceramic capacitors in parallel to the output main electro-
lytic capacitor).
s
To obtain a flat frequency response of the output impedance, the droop time constant
d
has to be equal
to the inductor time constant (see the note at the end of the section):
s
To obtain a constant -20dB/dec Gloop(s) shape the singularity f
1
and f
2
are placed in proximity of f
CE
and f
LC
respectively. This implies that:
s
To obtain a Gloop bandwidth of f
C
, results:
Note.
To understand the reason of the previous assumption, the scheme in figure 9 must be considered.
In this scheme, the inductor current has been substituted by the load current, because in the frequencies range
of interest for the Droop function these current are substantially the same and it was supposed that the droop
network don't represent a charge for the inductor.
G loo p s
( )
Av s
( )
R s
( )
Av s
( )
Z f s
( )
Z i s
( )
--------------
=
=
Av s
( )
Vi n
V
o sc
----------------
Z
C
s
( )
Z
C
s
( )
Z
L
s
( )
+
-------------------------------------
=
Z
I
s
( )
Rd
1
s
---
C 25
Rd
1
s
---
+
C25
----------------------------------
R4
1
s
---
C20
+
R 3
R 4
1
s
---
C20
+
R3
+
------------------------------------------------------
+
Rd 1
s
1
d
+
(
)
s
2
R3
R
d
--------
1
d
+
+
1
s
2
+
(
)
1
s
d
+
(
)
---------------------------------------------------------------------------------------------------
=
=
=
R d
1
s
R3
R
d
--------
d
+
1
s
1
+
(
)
1
s
2
+
(
)
1
s
d
+
(
)
---------------------------------------------------------------------
=
R s
( )
1
s
2
+
(
)
1
s
d
+
(
)
s C 18 R
d
1
s
R3
R
d
--------
d
+
1
s
1
+
(
)
--------------------------------------------------------------------------------------------------------
d
R
d
C 25
L
R
L
-------
L
C25
L
R
L
R
d
(
)
-----------------------
=
=
=
=
f
2
f
1
----
f
LC
f
C E
---------
R4
R3
f
LC
f
C E
---------
1
=
=
f1
f
C E
C20
1
2
---
R 4 f
C E
=
=
G
0
f
LC
1 f
C
G
0
A
0
R
0
V IN
Vosc
------------------
C20 // C25
C18
-----------------------------
f
C
f
LC
--------
C 18
VIN
Vosc
------------------
C20 C25
C20
C25
+
-----------------------------
f
LC
f
C
--------
=
=
=
=
=
L6911D
14/17
Figure 9. Voltage regulation with droop function block scheme
It results:
Because in the interested range |Gloop|>>1.
To obtain a flat shape, the relationship considered will naturally follow.
Application Idea: 1.100V to 1.850V / 25A
Figure 10 shows an application schematic for a 1.100V to 1.850V conversion with 25A of current capability.
Since the device's high gate drive, more than one mosfet for both high side and low side can be used: three
STS11NF30L (30V, 9mW typ @ Vgs=10V) mosfet are suggested for high side while four of them are suggested
as low side switch.
Figure 10. Schematic Circuit
A v(s)
R (s )
V o u t
V co m p
Io u t
d
s
L
s
OUT
R
+
+
1
1
Z
O U T
V
o
I
LO AD
----------------
R
d
1
s
L
+
1
s
d
+
------------------
G
LO O P
1
G
L O O P
+
-----------------------------
R
O U T
1
s
L
+
1
s
d
+
------------------
=
=
=
L2
L1
R7
R8
R9
C1-3
C23
C4-9
C17
Q4,Q5,Q6
Q1,Q2, Q3
D2
C17
F1
16
17
13
14
2
4
5
6
7
8
U1
L6911D
+5 VIN
+12Vcc
VOUTCORE
Vss
10
15
9
3
20
18
11
19
12
1
VCC
GND
VID0
VID1
VID2
VID3
VID4
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VSEN
VFB
COMP
R3
R4
R5
R2
C18
C19
C20
VID0
VID1
VID2
VID3
VID25mV
C24
D1
R6
R1
OVP
R10
C16
PWRGD
R15
R14
R13
C21-22
BOOT
15/17
L6911D
Part List
Resistor
R1
Not Mounted
SMD 0805
R2
470
1%
SMD 0805
R3
1k
SMD 0805
R4
82
SMD 0805
R5
Not Mounted
SMD 0805
R6
1k
SMD 0805
R7
1k
SMD 0805
R8
13k
SMD 0805
R9
100k
SMD 0805
R10
Not Mounted
SMD 0805
R12
20k
SMD 0805
R13, R14
Short Circuit
SMD 0805
Capacitor
C1-C3
680
F
- 6.3V
OSCON 6SP680M
Radial 10x10.5
C4-C9
820
F
- 4V
680
F
- 6.3V
OSCON 6SP680M
OSCON 4SP820M
Radial 10x10.5
Radial 10x10.5
C16
100n
SMD 0805
C17
100n
SMD 0805
C18
2.2n
SMD 0805
C19
Not Mounted
SMD 0805
C20
100n
SMD 0805
C23
1n
SMD 0805
C24
100n
SMD 0805
C25
47n
SMD 0805
Magnetics
L1
1.5
H
T44-52 Core, 7T-18AWG
L2
1.8
H
T50-52B Core, 7T-16AWG
Transistors
Q1-Q5
STS12NF30L
STMicroelectronics
SO8
Diodes
D1
1N4148
STMicroelectronics
SOT23
D2
STPS3L25U
STMicroelectronics
SMB
Ics
U1
L6911D
STMicroelectronics
SO20
Fuse
F1
251015A-15A
Littlefuse
AXIAL
L6911D
16/17
1
1
0
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
SO20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0 (min.)8 (max.)
OUTLINE AND
MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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17/17
L6911D
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