1/26

L6996

July 2002

5 BIT DAC WITH AVAILABLE EXTERNAL
OUTPUT VOLTAGE.

0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE
OUTPUT VOLTAGE RANGE.

±1% OUTPUT ACCURACY OVER LINE AND LOAD.

ACTIVE DROOP.

CONSTANT ON TIME TOPOLOGY ALLOWS
LOW DUTY CYCLE AND FAST LOAD
TRANSIENT.

90% EFFICIENCY FROM 12V TO 1.35V/8A.

1.750V TO 28V BATTERY INPUT RANGE.

OPERATING FREQUENCY UP TO 1MHZ.

INTEGRATED HIGH CURRENT DRIVERS.

LATCHED OVP AND UVP PROTECTIONS.
OCP PROTECTION.

350

A TYP. QUIESCENT CURRENT.

A TYP. SHUTDOWN SUPPLY CURRENT.

PGOOD AND OVP SIGNALS.

ZERO-CURRENT DETECTION AND PULSE-
FREQUENCY MODE.

APPLICATIONS

ADVANCED MOBILE CPUs SUPPLY WITH
DYNAMIC TRANSITIONS.

NOTEBOOK/LAPTOP, CONCEPT PC CPUs
SUPPLY.

DC/DC FROM BATTERY SUPPLY EQUIPMENTS.

DESCRIPTION

The device is dc-dc controller specifically designed to
provide extremely high efficiency conversion for mo-
bile advanced microprocessors.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feedfor-
ward" provides nearly constant switching frequency
operation.
A precise 5-bit DAC allows select output voltage from
0.6V to 1V with 25mV steps and from 1V to 1.75V
with 50mV steps.
L6996 is capable of supporting CPUs VID combina-
tion changing during normal operation.
The active droop allows adjust both the output load-
line slope and the zero-load output voltage.

TSSOP24

ORDERING NUMBERS: L6996D (TSSOP24)

L6996DTR (Tape & Reel)

DINAMICALLY PROGRAMMABLE SYNCHRONOUS

STEP DOWN CONTROLLER FOR MOBILE CPUs

APPLICATION DIAGRAM

SENSE

VPROG

SHDN

1.25V

VCC

VDR

25V

PGOOD

OVP

VPROG

VFB+

VFB-

VID4:0

OUT

L6996

CS-

PGND

LGATE

CS+

GND

PHASE

HGATE

ILIM

BOOT

OSC

L6996

2/26

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

PIN CONNECTION

Symbol

Parameter

Value

Unit

to GND

-0.3 to 6

to GND

-0.3 to 6

HGATE and BOOT, to PHASE

-0.3 to 6

HGATE and BOOT, to PGND

-0.3 to 36

PHASE

-0.3 to 30

LGATE to PGND

-0.3 to V

+0.3

ILIM, VFB+, VFB-, CS-, CS+, SHDN, VID0-4, PGOOD, OVP,
VPROG to GND

-0.3 to V

+0.3

tot

Maximum Power dissipation at T

amb

= 25°C

Junction operating temperature range

0 to 125

°C

stg

Storage temperature range

-55 to 125

°C

Symbol

Parameter

Value

Unit

th j-amb

Thermal Resistance Junction to Ambient

125

°C/ W

VID2

VID1

VID0

PGND

PGOOD

SHDN

OVP

ILIM

VFB+

CS+

CS-

LGATE

PHASE

VDR

HGATE

BOOT

VID4

VID3

VFB-

VCC

OSC

GND

VPROG

TSSOP24

3/26

L6996

PIN FUNCTIONS

Name

Description

1,2,3,
23,24

VID4-0

Voltage Identification inputs. VID0 is the LSB and VID4 is the MSB for the DAC (see VID table)

CS-

This pin is used for both current sensing and to detect overvoltage and undervoltage
conditions.

CS+

Current sense pin. Overcurrent condition is detected by sensing CS+ to CS- voltage.

VCC

Supply voltage for analogy blocks. Connect it to 5V bus.

GND

Signal ground

VPROG

DAC output voltage. This pin provides the voltage programmed by the DAC. Connect a 10nF
capacitor between this pin and GND.

VFB+

PWM comparator reference input. Connect this pin to VPROG.
An additional external voltage divider between output and VPROG may be used to realize the
active droop function.

VFB-

PWM comparator feedback input, to be connected to the regulated output.
By inserting a resistor between this pin and the regulated output, a positive offset can be
added to the output voltage.

OSC

Connect this pin to the battery through a voltage divider in order to provide the voltage
feedforward feature.

Soft start pin. 5

A constant current charges an external capacitor whose value sets the soft-

start time.

ILIM

An external resistor connected between this pin and GND sets the current limit threshold.

SHDN

ShutDown input. When connected to GND the device stops working. When high, it enables
the IC operation.

OVP

Open drain output. The pull-down transistor is off either in OV condition or during a VID
transition.

PGOOD

Open drain output. The pull-down transistor is on during soft-start, dynamic transitions and
when an output voltage fault occurs.

PGND

Power Ground. This pin has to be connected close to the low side MOSFET source in order to
minimize switching noise.

LGATE

Lower MOSFET gate driver output.

Voltage supply for the low side internal driver.

PHASE

This pin provides the return path of the high side driver.

HGATE

High side MOSFET driver output.

BOOT

Bootstrap capacitor pin. The high side driver is supplied through this pin.

L6996

4/26

ELECTRICAL CHARACTERISTICS
(V

= V

= 5V; T

amb

= 0°C to 70°C unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY SECTION

Vin

Input voltage range

Vout=1V Fsw=110Khz Iout=1A

Vcc, V

4.5

5.5

Vccoff

Turn-off voltage

4.1

4.3

HYST

UVLO Hysteresys

100

Iqcc

)

Quiescent current driver

VFB- > VFB+

Iqcc

(Vcc)

Quiescent current

VFB- > VFB+

600

SHUTDOWN SECTION

SHDN

SHDN Threshold

0.6

1.2

)

Driver quiescent current in
shutdown.

SHDN to GND

(Vcc) Shut down current

SHDN to GND

SOFT START SECTION

SS charge current

Soft-start active range

0.9

ON TIME

Ton

On time duration

Vprog=CS- =1.15 Osc=250mV

720

800

880

Vprog=CS-=1.15 Osc=500mV

355

420

485

Vprog=CS-=1.15 Osc=1V

210

250

290

Vprog=CS-=1.15 Osc=2V

120

150

180

OFF TIME

Minimum Off Time

580

OSC

OFFMIN

OSC=250mV V

PROG

=CS-=1.15V

0.28

DAC

Vprog

Voltage Accuracy

VID0-4 see table 1

-1

PWM COMPARATOR

Input voltage offset

PROG

=1.6V=V

FB-

-2

VFB-

Input bias current (VP)

VFB-

=1.6V

CURRENT LIMIT AND ZERO CURRENT COMPARATOR

LIM

ILIM input bias current

CS-=V

PROG

=1.6V

ILIM to GND = 120K

4.95

Positive and negative Current
Limit factor.

ILIM

= 120 K

0.18

0.3

0.24

PHASE-

GND

Zero Crossing Comparator offset

-2

GATE DRIVERS

High side rise time

=5V; C=7nF

HGATE - PHASE from 2 to 4.5V

High side fall time

Low side rise time

Low side fall time

PROTECTIONS

OVP

Over voltage trip

CS- rising

117

120

123

5/26

L6996

Table 1. DAC Output Voltage

UVP

Under voltage trip

CS- falling

PGOOD

Upper threshold
(CS-/V

PROG

)

CS- rising; PGOOD active

109

112

115

PGOOD

Lower threshold
(CS-/V

PROG

)

CS- falling; PGOOD active

Ron

GOOD

SOURCE

=2mA

100

VID4 VID3

VID2

VID1

VID0

Output

Voltage

(V)

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.050

1.100

1.150

1.200

1.250

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

ELECTRICAL CHARACTERISTICS (continued)
(V

= V

= 5V; T

amb

= 0°C to 70°C unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L6996

6/26

Figure 1. Functional & Block Diagram

configur

ation

Ref

erence chain

OUT

mode

ansition

dynamic

CS-

CS+

VID4:0

dela

off min

one-shot

80 us

detection

ansition

dynamic

CS-

VID4:0

5 bit D

VPR

OSC

FB+

FB-

PGND

LGA

VDR

PHASE

HGA

BOO

GND

VCC

PGOOD

SHDN

ILIM

negativ

e current limit

CS-

CS+

1.416

1.236V

bandgap

OSC

0.05

compar

ator

LS and HS anti-cross-conduction compar

ators

comp

V(LGA

TE)<0.5V

comp

V(PHASE)<0.2V

HS control

pwm compar

ator

compar

ator

positiv

e current limit

under

oltage compar

ator

OSC

one-shot

0.05

ILIM

LS control

dynamic tr

ansition control

HS dr

dynamic

oltage compar

ator

ansition

5 uA

on= K

osc

V(CS-)/V(OSC)

VCC

el shifter

LS dr

5 uA

PHASE

0.6 VPR

mode

CS-

on= K

osc

V(CS-)/V(OSC)

on min

one-shot

ero-cross compar

ator

pgood compar

ators

soft-star

1.075 VPR

0.925 VPR

er management

control

1.12 VPR

CS-

IC enab

L6996

8/26

Figure 7. Test Condition: V

= 20V, V5v=5V, F

= 300kHz, T

amb

= +25°C

Figure 8. Test Condition: V

out

= 1.75V, F

= 300kHz, V5v = 5V, T

amb

= +25°C

Figure 9. Test Condition: V

out

= 1.75V, V5v = 5V, T

amb

= +25°C

0.76

0.78

0.8

0.82

0.84

0.86

0.88

0.10

1.00

10.00

100.00

Current [A]

Efficency [%]

Vout=1.35

Vout=1.25

Vout=1.7

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.9

0.91

0.92

0.1

1.0

10.0

100.0

Current [A]

Efficency [%]

Vin=7

Vin=12

Vin=20

250

270

290

310

330

350

370

390

410

Current [A]

Frequency [KHz]

Vin=20

Vin=12

Vin=7

9/26

L6996

Figure 10. Typical Application with Active Voltage Droop

Figure 11. Typical Application without Active Voltage Droop

VIN1

OUT

BOOT

VIN1

PU1

IL2

PU2

VIN2

VPROG

IL1

V52

VP3

V51

SHDN

VP3

VP1

VP2

VIN2

SENSE

OUT1

VID4:0

VCC

OSC

BOOT

ILIM

HGATE

PHASE

LGATE

PGND

GND

CS+

CS-

VFB-

VFB+

OUT

CPU

VPROG

BOOT

L6996

VDR

PGOOD

OVP

OUT

VIN1

V52

IL1

VIN2

VPROG

PU1

VIN1

V51

SENSE

SHDN

IL2

BOOT

VIN2

PU2

OUT1

VID4:0

VCC

OSC

BOOT

ILIM

HGATE

PHASE

LGATE

PGND

GND

CS+

CS-

VFB-

OUT

CPU

VFB+

BOOT

L6996

VDR

PGOOD

OVP

VPROG

L6996

10/26

DEVICE DESCRIPTION

1.1 Constant On Time PWM Topology

Figure 12. Loop block schematic diagram

This device implements a Constant On Time control, where the Ton is the on time duration forced by a one-shot
circuit. The controller calculates the one-shot time directly proportional to the V

CS-

pin voltage and inversely to

the OSC pin voltage as in Eq 1:

Eq 1

where K

OSC

=180ns and

is the internal propagation delay time (Typ. 40ns). The system imposes in steady

state a minimum on time corresponding to V

OSC

= 2V. In fact if the V

OSC

voltage increases above 2V the cor-

responding Ton will not decrease. Connecting OSC pin to a voltage partition from V

to GND, it allows steady-

state switching frequency F

independent of V

. It results:

Eq 2

where

Eq 3

The above equations allow setting the frequency divider ratio aOSC once output voltage has been set; note that
such equations hold only if V

OSC

<2.A minimum off-time constrain of about 500nS is introduced in order to as-

sure the boot capacitor charge and to limit switching frequency after a load transient as well as to mask PWM
comparator output against switching noise and spikes.

The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three

Vprog

VFB+

CS-

VID0-4

Rsense

Vout

Vin

HGATE

LGATE

PWM comparator

VFB-

FFSR

One-shot generator

OSC

DAC

O N

O SC

C S -

OS C

---------------

O U T

---------------

O N

-----------

O SC

OS C

---------------

--------------------

11/26

L6996

conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the ref-
erence voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the induc-
tor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV
and 2V to ensure the system linearity.

1.2 Closing the loop

The loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator
negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes
lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side
MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the pre-
vious section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side
MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way.
For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the aver-
age output voltage is different from the programmed one as shown in figure 13.

Figure 13. Valley Regulation

Figure 14. Voltage positioning network

The L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5m

sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure
14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current

Time

Vout

Vref

<Vout>

DC Error Offset

L6996

Vprog

To Vout

Rsense

To inductor

VFB-

VFB+

COMPARATOR

PWM

L6996

12/26

has an average value equal to Io. The intention is to find the output average value called Vo. It is important to
remember that the loop is closed a valley of the ripple, in this conditions the inputs of PWM comparator must be
equal, so the VFB+ =VFB-. Suppose R4=0 and R3=open.

Considering this and watching the figure 14 it can be written two equations at the VFB+ and VFB- node:

Eq 4

Rsense · Io = Vc

Eq 5

Imposing Eq4=Eq5 it can be found the V

OVALLEY

value:

Eq 6

Vovalley = Vprog + Rs · (1 + R1/R2) · Io

Form Eq6 it can be noted the active drop effect due to R1, R2 resistors; it can be also noted the output average
value is different from the V

PROG

value, the error is due to the valley control, and it is equal to half of the ESR

voltage ripple.

To reduce the error of the average output voltage we can change the V

PROG

value using resistors. In fact con-

sidering the R3 resistor we can make a Thevenin equivalent:

Eq 7

Vprogeq = Vprog · R3/(R3 + R2)

Eq 8

Req = R3//R2

How it can be seen the V

PROGEQ

is less the V

PROG

and so we can reduce the average output error. Remember

that the R1, R2 and R

SENSE

are selected in base at the Voltage Positioning needs.

The R4 resistor can be used to set also a positive offset at zero load. Considering the PWM comparator inputs:

Eq 9

Vo = V

FB+

+ R4 · 5

Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hys-
teretic system the frequency can change with some parameters (input voltage, output current). In L6996 is im-
plemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate
operation with the input voltage variation. There are many factors affecting switching frequency accuracy in
steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver.
Others related to the external components as high side MOSFET gate charge and gate resistance, voltage
drops on supply and ground rails, low side and high side RDS

and inductor parasitic resistance.

During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).

1.3 Transition from PWM to PFM

To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turns-
on the low side MOSFET, until the current reaches the zero A value, when the zero-crossing comparator turns
off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground, through
the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps the low
side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow through the
low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in fact in PFM
mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when
the output voltage goes down a reference value. The device works in discontinuous mode at light load and in

ov alle y

prog

(

)

------------------------------------------------------------

13/26

L6996

continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the
inductor current ripple. This threshold value depends on V

, L, and V

OUT

. Note that the higher the inductor val-

ue is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient
response is. In PFM mode the frequency changes, with the output current changing, more than in PWM mode;
in fact if the output current increase, the output voltage decreases more quickly; so the successive turn-on ar-
rives before, increasing the switching frequency. The PFM waveforms may appear more noisy and asynchro-
nous than normal operation, but this is normal behaviour mainly due to the very low load. The NOSKIP feature
cannot be disabled.

1.4 Softstart

If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side
MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to in-
crease and the system starts to switch. The softstart is realized by gradually increasing the current limit thresh-
old to avoid output overvoltage. The active soft start range (where the output current limit increase linearly)
starts from 0.6V to 1.5V. In this range an internal current source (5

A typ) charges the capacitor on the SS pin.

The reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage
and it saturates at 5

A (typ.) when SS voltage is close to 1.5V; so the maximum current limit is active. Output

protections like undervoltage is disabled until SS pin voltage reaches 1.5V, instead the overvoltage is always
present.

Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation
anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first
turn-on the power section and after the logic section (V

pin).

Figure 15. Soft-start diagram

1.5 Current limit

The current limit comparator senses inductor current through the sense resistor when the low side MOSFET is
on and compares this value with the ILIM pin voltage. While the current is above the prefixed value, the control
inhibits the one-shot start.

To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, V

e V

OUT

Eq 10

OUT

= I

MAX_VALLEY

/ 2

Time

0.6V

Maximum current limit

Soft-start active range

4.1V

1.5V

Ilim current

Vss

L6996

14/26

To set the current threshold, choose R

ILIM

according to the following equation:

Eq 11

Where K

is the current limit factor (0.25

A typ.). A negative current limit is also introduced during dynamic tran-

sitions, when zero-cross comparator is disabled and at the inductor current is allowed to reverse. The negative
current limit is useful when performing a negative transition (that is, output voltage is reduced) to avoid too high
discharging current.

Both positive and negative current limit have the same threshold; but the negative current limit can be set using
the OVP signal plus a transistor, that changes during the dynamic transition, as in Fig. 16 (Q5, R11).

The system accuracy is function of the exactness of the resistance connected to I

LIM

pin and RSENSE resistor.

Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the system linearity.

1.6 Protection and fault

Sensing CS- pin voltage performs the output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is within the 90% 110% range, PGOOD is high.
If an overvoltage or an undervoltage occurs, the device is latched. low side MOSFET is turned ON and high side
MOSFET off. PGOOD goes low. OVP goes high in case of overvoltage, allowing the fault nature to be detected.

To recuperate the functionality either the device must be shut down, thought the SHDN pin, or the supply has
to be removed. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET
short (OV fault).

1.7 Drivers

The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-
FETS.

The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
root square of the MOSFET gate charge and the switching frequency. So the power dissipation of the device is
function of the external power MOSFET gate charge and switching frequency.

Eq 12

driver

= V

· Q

gTOT

· F

The maximum gate charge values for the low side and high side are given from:

Eq 13

Eq 14

Where f

SW0

= 500kHz. The equations above are valid for T

= 150°C. If the system temperature is lower the Q

can be higher.

For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;

M AX_VAL LEY

ILIM

S E N S E

----------------------

M A X H S

SW0

-------------

75 nC

M AXLS

SW 0

-------------

125nC

15/26

L6996

in this case the maximum value is Q

MAXLS

= 125nC.

The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.

1.8 Digital to analog converter

The built-in digital to analog converter (DAC) allows the adjustment of the output voltage in correspondence to
the Table1 in pag 4: from 0.6V to 1V with 25mV steps, and from 1V to 1.75V with 50mV steps. The DAC can
receive the digital input from the CPU. The programmed voltage is available on VPROG pin, which is capable
of sourcing or sinking up to 250

A. The internal reference accuracy is ±1%.

1.9 Dynamically changing DAC code

L6996 detects as a transition any change in VID code which duration is larger than 200ns. Then, a timer forces
the chip in a 'transition state' for about 100µs. In such a state, output protections are disabled and OVP pin goes
high.

Current limit threshold can be reduced during the transition state duration by using an external mos shorting part
of the R

ILIM

resistor. The MOSFET gate is driven by OVP. Reducing current limit threshold prevents from output

voltage overshoot/undershoot once the new-programmed voltage has been reached (see waveforms reported
below), especially when the droop is not implemented. Note that the reduced threshold must be however high
enough to allow the output capacitor to charge/discharge within the transition time. During the transition state
duration, zero-cross comparator is disabled and inductor current is allowed to reverse. A negative current limit
is introduced. During OFF time, if inductor current is negative and reaches the threshold, low side MOSFET is
forced OFF, and remain OFF, allowing negative current to flow across high side body diode, for at least T

After then, the low side or high side turns ON again, depending on PWM comparator output. This allows switch-
ing frequency to be close to steady state frequency also when the device works in negative current limit protec-
tion.

Dynamically changing the VID code is useful for portable computers, where the CPU is supply at a higher volt-
age when the AC-DC adapter is plugged-in, to increase speed. A lower voltage is instead provided when only
the battery powers the CPU, to save energy.

The dynamic transition is usually made at light load condition, to allow the full current to be available for charg-
ing/discharging the output capacitor:

Iout ~ 300mA

Vout

max

~250mV

The current limit threshold should be set high enough to charge/discharge the output capacitor within the tran-
sition state duration (see below). If the output voltage changing is higher than 250mV the system can detect an
overvoltage or undervoltage that can shut down the device.

L6996

16/26

APPLICATION INFORMATION

2.1 Demo board description

The demoboard shows the device operation in general purpose applications. The evaluation board needs two
different supplies; one for the IC section (5V), and another for the conversion section (up to 28V). Output current
in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when
the supplies are already present) and to select the VID code (i.e. the output voltage).

Figure 16. Schematic Diagram

+5V

PGOOD

GNDSENSE

+5V

OVP

VPR

+5V

Rout

VOUTSENSE

+5V

R18

R19

R24

+5V

R20

R21

R22

R23

SHDN

DPSLVR

+5V

DPSLP

+5V

VID4:0

GMUXSEL

R14

L6996

PGOOD

OVP

VPROG

VFB+

VFB-

CS-

CS+

GND

PGND

LGATE

PHASE

HGATE

ILIM

BOOT

OSC

VCC

VID4:0

VDR

R2..R6

C10

R16

R15

VIN

VOUT

GND

C11

R11

R10

R12

R13

R17

SHDN

+5V

C18..C23

C12..C17

GND

Q3,4,5

Q1,2

+5V

L6996

18/26

Table 2. PCB Layout guidelines

DESIGN EXAMPLES

3.1 V

= 20V I

OUT

= 23A

In this design it is considered a low profile demoboard, so a great attention is given to the components height.

3.2 Input capacitor

A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com-
ponent of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor:

Eq 15

The I

RMS

current is given by:

Eq 16

Neglecting the last term, the equation reduces to:

Eq 17

CIN

, and also I

CINRMS

, has a maximum equal to I

OUT

/2 (@ V

= 2 × V

OUT

, that is, 50% duty cycle). The input,

therefore, should be selected for a RMS ripple current rating as high as half the respective maximum output
current. Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide
range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are
physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR
and small size. The only problem is that they occasionally can burn out if subjected to very high current during
the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be sub-
jected to high surge current when connected to the power supply. If available for the requested value and volt-
age rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the
very low ESR). From the equation 17 it is found:

Goal

Suggestion

Low radiation and low magnetic coupling with the
adjacent circuitry

1) Small switching current loop areas. (For example Placing

, high side and Low Side MOSFET, Schottky diode, as

close as possible each to others).

2) Controller placed as close as possible to the Power

MOSFET.

3) Group the gate drive component (Boot cap and diode

together near the IC.

Don't penalty the efficiency

Keep the power traces and load connections short and wide.

Ensure high accuracy in the current sense system

Cs+, CS- traces must be made by Kelvin connection. Also the
traces should be separated from the power plane by a ground
plane, run parallel.

Reduce the noise effects on IC

1) Put the feedback component (like the VP network as close

as possible to the IC)

2) The feedback connection (like the FB trace, or CS+/CS-

traces....) should be route as far as possible from the
switching current loops.

3) Make the controller ground connection like in the figure 16.

C IN

ESR

C IN

Iou t

Vin

Vi n

Vout

(

)

Vin

------------------------------------------------

Icin

rm s

Iout

(

)

------

(

)

Icin

rm s

Io ut

(

)

19/26

L6996

Icin

rms

= 6.4A

Considering 10uF capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed.

3.3 Inductor selection

In order to determine the inductor value is necessary considering the maximum output current to decide the in-
ductor current saturation. Once the inductor current saturation is found automatically it is found the inductor val-
ue also. The inductor value is important also to determine the duration of the dynamic output voltage transition.
In our design it is considered a very low profile inductor.

L = 0.6

The saturation current for this choke is 25A

3.4 Output capacitors

The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related
to the output voltage ripple value, while the dynamic accuracy is related to the output current load step.

If the static precision is around +/- 4% for the 1.25V output voltage, the output accuracy is ±50mV.

To determine the ESR value from the output precision is necessary before calculate the ripple current:

Eq 18

Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A.

So the maximum ESR should be:

Eq 19

The dynamic specifications are sometime more relaxed than the static requirements so the ESR value around
7m

should be enough.

Sometimes can be considered the output capacitor effect also:

Eq 20

From the above equation can be calculated the minimum output capacitance value. Considering

OUT

100mV, C

OUT

> 1600

F should be used.

Five capacitor of 330

F from PANASONIC correspond to the request. To allow the device control loop to prop-

erly work, output capacitor ESR zero must be at least ten times smaller than switching frequency. Low ESR tan-
talum capacitors, which ESR zero is close to 10 kHz, are suitable for output filtering. Output capacitor value
COUT and its series resistance, should be large enough and small enough, respectively, to keep output voltage
within the accuracy range during a load transient, and to give the device a minimum signal to noise ratio.

The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sus-
tain this ripple: the RMS current value is given from Eq21.

Eq 21

But this is usually a negligible constrain when choosing output capacitor.

Vin

-----------------------

Vi n

---------

ESR

rip ple

-----

---------------------

50m V

3.5

----------------

14m

Vo ut

Io ut

2 Vo ut

----------------------

C out

--------------

Icout

rms

2 3

-----------

L6996

20/26

3.5 Power MOSFET and Schottky Diodes

Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFET is highly recommended,
especially for high current applications. The breakdown voltage V

BRDSS

must be greater than VINMAX with a

certain margin, so the selection will address 20V or 30V devices (depends on applications).

The RDS

can be selected once the allowable power dissipation has been established. By selecting identical

Power MOSFET as the main switch and the synchronous rectifier, the total power they dissipate does not de-
pend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required

RDS

(@ 25 °C) can be derived from:

Eq 22

is the temperature coefficient of RDS(ON) (typically, a = 5*10

-3

°C

-1

for these low-voltage classes) and T the

admitted temperature rise. It is worth noticing, however, that generally the lower RDS

, the higher is the gate

charge Q

, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q

moves

from the input source to ground, resulting in an equivalent drive current:

Eq 23

The Schottky diode to be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM
greater than VINMAX.

For this application are selected: two high side MOSFET STS11NF3LL and two STS17NF3LL for the low side
section.

3.6 RSENSE selection

The droop function consists to change the output voltage changing the output current; at high output current the
output voltage is lower than the reference voltage. To implement the droop function, for the high current status,
we use the R

SENSE

resistor in series to the inductor. Since inductor current can be very high, so the resistor

must be capable to dissipate high power. Moreover we use the sense resistor to measure the output current for
the current limit feature, so the R

SENSE

value must be very accurate also for temperature variation. To ensure

higher temperature stability it could possible to split the R

SENSE

value. To achieve high efficiency also the

SENSE

value must be as low as possible, so the Active voltage droop implemented in L6996 is very useful. For

this application it are selected two 3mohms resistors from PANASONIC.

3.7 VP Network Design

The voltage-positioning network is selected by the load regulation needed. In this application wit is considered
4mV/A; with a RSENSE resistor around 1.5mohms it can be used a gain around 2.66 and so a rate between R1
and R2 around 1.66 from the Eq6.

It can be selected:

R1=1.66K

R2=1K

A capacitor C

VP1

is required in parallel with RVP1 to correctly compensate the network response. Its value is

given by the following equation:

Eq 24

where C

OUT

is the output capacitor value. When C

VP1

is well chosen, a step decrease of output voltage should

be observed, as an effect of a step load increase. Too small or too large C

VP1

produces overshoot or undershoot

instead of a step waveform.

RD S

O N

Iou t

(

)

-------------------------------------------------

Q g F

VP1

ESRC

O U T

VP1

--------------

VP2

--------------

21/26

L6996

With our parameter:

VP1

= 7.8pF

No-load offset is obtained by R

VP3

and of a current source internally connected to VFB+ pin. Thus:

Eq 25

where I

OFFSET

= 5

The capacitor C

VP3

in parallel to R

VP3

is a filter which time constant can be the same as in Eq22, so

Eq 26

3.8 Input divider

The input divider can be selected with the Eq1, Eq2, Eq3 . Choosing a switching frequency around 270kHz it
results:

OSC = 0.048.

R1 = 560K

R2 = 27K

3.9 Current limit resistor

From the Eq12 it can be set the current limit resistor, for the positive current limit; it results:

R10 + R11 = 120K

The negative current limit is set by the time available for the negative dynamic transition; a value around 30K

for R10 is a match between negative peak current and time to end the dynamic transition (around 80mS).

R10=150KW

R11=30KW

3.10 Softstart capacitor

The soft start capacitor is selected once the soft start time is imposed. It can be consider a soft start time around
1ms. The soft start capacitor is given by:

Eq 27

Where

is the soft start active range and

T is the soft stat time. From Eq 28 results: C

= 10nF.

VP3

O U T I

P R O G

O F FSET

-----------------------------------------------------

VP2

VP1

--------------

------------------------

VP3

ESRC

OU T

O U T

VP 3

-------------------------------------------------

l im

s s

--------------------

L6996

22/26

Table 3. Component List

The component list is shared in two sections: the first for logic and general-purpose component, the second for
power section:

GENERAL PURPOSE COMPONENTS

Part name

Value

Part number

Manufacturer

Notes

R1, R2, R3, R4, R5, R6,

R7, R9, R18, R19, R24

33k

47k

R10

120k

Current limit resistors

(to set the current limit)

R11

30k

R12

1.66k

Voltage positioning

resistors

R13

R15

560k

Input resistor divider (to

set the switching

frequency)

R16

27k

R20

130k

IMVPII resistor network

R21

39k

R22

36k

R23

270k

Tantalum/SP

C2, C3

100nF

220nF

10nF

220nF

6.8nF

Voltage positioning

capacitor

47pF

C10

10nF

C11

47pF

U2, U6, U8

Or gate

NC7SZ32M5

FAIRCHILD

Logic network

U9, U7

Inverter gate

NC7SZ04P5

FAIRCHILD

U3,U4,U5

Nor gate

NC7SZ02P5

FAIRCHILD

BAT54A

PHILIPS

Q5,Q6,Q7,Q8

BSS131

Q62702-S565

INFINEON

SW1, SW2

DIP SWITCH

23/26

L6996

POWER SECTION

SENSE RESISTOR

It is important, for this component, to keep in mind three factor: it must be able to dissipate high power. Again
its variation with the temperature must be small and the precision must be high to ensure high precision with the
ST voltage droop function.

INPUT CAPACITOR

For this components can be useful control the temperature coefficient and the equivalent serie resistor and the
voltage rated.

OUTPUT CAPACITOR

For this components can be useful control the temperature coefficient and the equivalent series resistor and the
voltage rated.

INDUCTOR

For the inductor important factors are the saturation current and the equivalent series resistor (for the efficiency
improvements)

POWER MOS

Note N.M.=Not Mounted.

For the MOSFET choose is important to know the input voltage and output voltage. The MOSFET must able

Part name

Value

Part number

Manufacturer

Notes

R14, R17

ERJM1WSF3M0U

PANASONIC

Part name

Value

Part number

Manufacturer

Notes

C12,C13,C14,C15,C16,C17

ECJ5YB1E106M

PANASONIC

25V ceramic

ECJ5YF1E106M

PANASONIC

25V ceramic

C34Y5U1E106ZTE12

TOKIN

25V ceramic

GMK325F106ZH

TAIYO-YUDEN

35V ceramic

TMK325F106ZH

TAIYO-YUDEN

25V ceramic

TMK432BJ106MM

TAIYO-YUDEN

25V ceramic

Part name

Value

Part number

Manufacturer

Notes

C18,C19,C20,C21,C22,C23

270

EEFUE0D271R

PANASONIC

C18,C19,C20,C21,C22

330

EEFUE0D271R

PANASONIC

Part name

Value

Part number

Manufacturer

Notes

0.6

ETQP6F0R6BFA

PANASONIC

0.6

A959AS-R60N

TOKO

0.6

CEP12D38H-0R6

SUMIDA

Part name

Value

Part number

Manufacturer

Notes

High side

Q1, Q2

STS11NF3LL

STS11F3LL

STMicroelectronics

STSJ25NF3LL

STMicroelectronics

Low Side

Q3, Q4

STS17NH3LL

STMicroelectronics

Q5 N.M

STS25NH3LL

STMicroelectronics

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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L6996

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L6996D

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L6996D