QUAD POWER LOWSIDE DRIVER WITH 2 x 5A
AND 2 x 3A OUTPUT CURRENT CAPABILITY
LOW R
DSON
TYPICALLY 200m
AND 300m
@ Tj = 25
C
INTERNAL OUTPUT CLAMPING STRUC-
TURES WITH V
FB
= 50V FOR FAST INDUC-
TIVE LOAD CURRENT RECIRCULATION
LIMITED OUTPUT VOLTAGE SLEW RATE
FOR LOW EMI
PROTECTED
P
COMPATIBLE ENABLE
AND INPUT
WIDE
OPERATING
SUPPLY
VOLTAGE
RANGE 4.5V TO 32V
REAL TIME DIAGNOSTIC FUNCTIONS:
- OUTPUT SHORTED TO GND
- OUTPUT SHORTED TO VSS
- OPEN LOAD MEASURED IN ON AND OFF
CONDITION
- LOAD BYPASS DETECTION
- OVERTEMPERATURE
DEVICE PROTECTION FUNCTIONS:
- OVERLOAD DISABLE
- REVERSE SUPPLY VOLTAGE
PROTECTED VS UP TO -2V
- SELECTIVE THERMAL SHUTDOWN
DESCRIPTION
The L9346 is a monolithic integrated quad low
side driver realized in an advanced Multipow-
May 2000
OUT1
OUT4
VS
Channel1
Channel4
Output
Control
Overtemp
R
Q
S
Delay
Timer
Overload
Openload
G ND
D4
IN4
EN
D1
IN1
R IO
Diagnostic
Control
OUT2
Channel2
D2
IN2
OUT3
Channel3
D3
IN3
52V
BLOCK DIAGRAM
ORDERING NUMBERS: L9346PD (power SO20)
L9346DIE (chip)
L9346
QUAD INTELLIGENT POWER LOW SIDE SWITCH
Power SO20
Chip
1/13
erBCD mixed technology. The device is intended
to drive valves in automotive environment.
The inputs are
P compatible. Particular care has
been taken to protect the device against failures,
to avoid electromagnetic interferences and to of-
fer extensive real time diagnostic.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Value
Unit
V
S
DC Supply Voltage
-2 to 32
V
V
SP
Supply Voltage Pulse (duration <200ms)
-2 to 45
V
dV
S
dt
Supply Voltage Slope
10
V/
s
V
IN, EN
Input Voltage
I
10mA
-2 to 16
V
V
D
Diagnostic DC Output Voltage
I
50mA
-0.3 to 16
V
V
ODC
DC Output Voltage
-0.3 to 45
V
I
O1, 2
DC Output Current Out 1, 2
5
A
I
O3, 4
DC Output Current Out 3, 4
3
A
I
OR1, 2
Reverse Output Current
-5
A
I
OR3, 4
Reverse Output Current
-3
A
E
O1, 2
Switch-off Energy for Inductive Loads
t
EO
= 250
s,
1)
50
mJ
E
O3, 4
T = 5ms
30
mJ
V
GND
GND Potential Difference
T
j
= -40 to 150
C
0.3
V
T
jEO
Juntion Temperature During Switch-off
t
30 min
175
C
t
15 min
190
C
T
j
Juntion Temperature
-40 to T
jDIS
C
T
stg
Storage Temperature
-55 to 150
C
T
jDIS
Thermal Disable Junction Temp. Threshold
180 to 210
C
The device is ESD protected, tested according to MIL883C with
2KV.
Note
1)
: t
EO
is the clamping time (see fig.1)
P G N D
O U T 1
D 1
IN 4
E N
G N D
IN 3
D 2
O U T 2
P G N D
P G N D
P G N D
O U T4
D 4
IN 1
V S
N C
IN 2
D 3
O U T3
H e at s in k c o n ne c te d to pin s 1, 1 0, 1 1 , 2 0
PIN CONNECTION
DESCRIPTION (continued)
L9346
2/13
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-c
Thermal Resistance junction to case
3
K/W
PIN FUNCTIONS
N.
Name
Function
1
GND
Power Grounded
2
Out 1
Output 1 (5A)
3
D1
Diagnostic 1
4
IN 4
Input 4
5
VS
Supply Voltage
6
NC
Not Connected
7
IN 3
Input 3
8
D2
Diagnostic 2
9
Out 2
Output 2 (5A)
10
GND
Power Ground
11
GND
Power Ground
12
Out 3
Output 3 (3A)
13
D3
Diagnostic 3
14
IN 2
Input 2
15
GND
Signal Ground
16
EN
Common Enable
17
IN 1
Input 1
18
D4
Diagnostic 4
19
Out 4
Output 4 (3A)
20
GND
Power Ground
t
EO
V
S
T
t
VO 1 - 4
V
O C L
Figure 1: t
EO
Clamping Time
L9346
3/13
ESD
Figure 2: Pad Position (Chipsize 4.95 x 3.88)
L9346
4/13
Pad Coordinates (Reference point X = 0, Y = 0: Center of die)
Pat opening center position
Pad Nr.
Pad Name
Size in (
m)
Description
Coordinates in (
m)
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PG3
PG3
PG2
PG2
OUT2
OUT2
D2
IN3
VS
IN4
D1
OUT1
OUT1
PG1
PG1
PG4
PG4
OUT4
OUT4
D4
IN1
EN
GND
IN2
D3
OUT3
OUT3
178 x 280
178 x 280
178 x 280
178 x 280
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
Power Ground 3
Power Ground 3
Power Ground 2
Power Ground 2
Output 2 5A
Output 2 5A
Diagnostic 2
Input 3
Supply Voltage
Input 4
Diagnostic 1
Output 1 5A
Output 1 5A
Power Ground 1
Power Ground 1
Power Ground 4
Power Ground 4
Output 4 3A
Output 4 3A
Diagnostic 4
Input 1
Common Enable
Signal Ground
Input 2
Diagnostic 3
Output 3 3A
Output 3 3A
2286.5
2286.5
2286.5
2286.5
1472.5
1722.5
1036
648
-260
-648
-1036
-1722.5
-1472.5
-2286
-2286
-2286
-2286
-1448
-1656
-970
-582
-194
194
582
970
1656.5
1448.5
1175
506
98
-842
-844
-1644
-1644
-1644
-1644
-1644
-1644
-1644
-844
-842
98
506
1175
865
1644
1644
1644
1644
1644
1644
1644
1644
865
Test pad
Size
X
Y
Gate 2
VTERM2
IOLRED
ESD
VTERM1
GATE1
GATE4
VTERM4
VTERM3
GATE3
d = 102
d = 102
d = 102
178 x 178
d = 102
d = 102
d = 102
d = 102
d = 102
d = 102
1447
1260
449.5
260
-1260
-1447
-1381
-1194.5
1194.5
1381
-1612
-1600
-1455.5
-1644
-1600
-1612
1600
1600
1600
1600
L9346
5/13
ELECTRICAL CHARACTERISTICS (Operating Range)
The electrical characteristics are valid within the below defined operating range, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
Board Supply Voltage
4.5
12
32
V
T
j1
Junction Temperature
-40
150
C
T
j2
Junction Temperature
t
15min
2)
over life time
150
T
jDIS
C
NOTE:
2)
Parameters guaranteed by correlation
ELECTRICAL CHARACTERISTICS (V
S
= 4.5 to 32V; -40
C
j1
150
C < T
j2
jDIS
, unless other-
wise specified.)
Symbol
Parameter
Test Condition
Value T
j1
Value T
j2
Unit
Min.
Typ.
Max.
Min.
Max.
Supply
I
VS OFF
DC Supply Current Off
EN = 1.0V
5
10
mA
I
VS ON
DC Supply Current On
V
S
14V; V
IN
, V
EN
= 2V
8
mA
Diagnostic Outputs D 1 - D 4
V
DL
Diagnostic Output Low
Voltage
I
D
3mA
0.65
1.0
1.5
V
I
DLE
Diagnostic Output
Leakage Current
V
D
= 14V
3)
0.1
2
20
A
Outputs Out 1 - Out 4
V
OUV 1-4
Open Load Voltage
Threshold
V
IN =
1V
0.525 x
V
S
0.55 x
V
S
0.575 x
V
S
0.5 x V
S
0.65 x
V
S
V
V
OUV hys 1-4
Hysteresis
0.003 x
V
S
V
V
OUV 1-4,
2-3, 4-1, 3-2
Open Load Difference
Voltage Threshold
V
IN1,4/2,3 =
1V,
4.5V
VO
c
16V,
4.5V
V
S
16V,
VO
c
= output voltage of
other channel
VO
C
-
1.0V
VO
C
-
1.25V
VO
C
-
1.5V
VO
C
-
0.8V
VO
C
-
1.7V
V
V
OUV hys 1-4,
2-3, 4-1, 3-2
Open Load Hysteresis
40
mV
I
OUC 1, 2, 3, 4
Open Load Current
Threshold
V
EN
= V
IN
= 2V;
V
S
= 6.5 to 16V
160
320
480
580
mA
I
OOC 1, 2
Over Load Current
Threshold
V
S
> 6.5V;
V
OUT
= 32V
5
10
4
A
I
OOC 3, 4
3
6
2.4
A
V
OCL
Output Voltage During
Clamping
I
OCL
200mA
45
52
60
V
S
ON,OFF
Output (fall, rise) slew
rate
4)
I
OUC
I
O
I
OOC
400
1500
2850
200
3500
V/ms
R
IO
Internal Output Pull
Down Resistor
V
EN
= 1V
10
20
40
50
K
R
DSON 1, 2
Output On Resistance
T
j
= 25
C
T
j
= 150
C
V
S
> 9.5V, I
O1,2
= 2A
200
300
500
m
R
DSON 3, 4
T
j
= 25
C
T
j
= 150
C; I
O3,4
= 1.3A
300
450
750
m
NOTE:
2)
Parameters guaranteed by correlation
3)
The diagnostic output is short circuit protected up to V
D
= 16V
4)
V
S
= 9 to 16V
L9346
6/13
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Value T
j1
Value T
j2
Unit
Min.
Typ.
Max.
Min.
Max.
Inputs IN1-4, EN
V
IN,EN L
Logic Input/Enable Low
Voltage
-0.3
1
0.8
V
V
IN,EN H
Logic Input/Enable High
Voltage
IN, EN
2.0
16
V
V
EN,IN hys
Logic Input Hysteresis
0.2
0.4
0.8
V
I
IN
Input Sink Current
V
IN
= 2 to 12V
5)
10
30
60
240
A
I
EN
Enable Sink Current
10
20
40
240
A
Timing
t
D ON
Output Delay ON Time
6)
Fig. 7
4
25
s
t
D OFF
Output Delay OFF Time
6)
Fig. 7
5
15
30
s
t
DH-L, Diag
Diag. Delay Output
OFF Time
6)
Fig. 6
8
65
90
s
t
D IOU
Diagnostic Open Load
Delay Time
V
S
= 9 to 16V, Fig 8
I
O
I
OUC
8
50
s
t
DOL
Diagnostic Overload
Delay Switch-OFF Time
V
S
= 9 to 16V, Fig 8
I
O
> I
OOC
50
160
300
s
t
D EN ON
Enable ON Time
6)
Fig. 7
4
25
s
t
D EN OFF
Enable OFF Time
6)
Fig. 7
4
25
s
NOTE:
5)
Open pins (EN, IN) are detected as low
6)
V
S
= 9 to 16V
I
OUC
I
O
I
OOC
DIAGNOSTIC TABLE
CONDITIONS
EN
IN
OUT
DIAG.
Normal Function
L
X
off
L
H
L
off
L
H
H
on
7)
H
GND short
V
Otyp
< 0.55V
S
L
X
off
H
Load bypass
V
O1-4/2-3
1.25V
H
L
off
H
Open Load
I
O1,2,3,4typ
< 320mA
H
H
on
7)
L
T
jtyp
190
C Overtemperature
8)
X
X
off
L
Over Load
I
Omin 1,3
> 5A
I
Omin 2,4
> 3A
H
H
off
L
Reset and Overtemperature Latch
X
DC don't care
DC don't care
NOTE:
7)
For V
S
= 4.5 to 6.5V, I
O
2A, the diag. table is valid
8)
If one diag. status shows the overtemperature, recognition, in parallel this output will be switched OFF internally.
The corresponding channel should be switched OFF additionally by its input signal, otherwise the overload latch will be set aftert
DOL
is passed.
This behaviour is related to the overdrop sensing which is used as over load recognition.
The overtemperature is latched (DIAG = L) until the level of the IN signal changes to low.
L9346
7/13
CIRCUIT DESCRIPTION
The L9346 is a quad low side driver for inductive
loads like valves in automotive environment. The
internal pull down current sources
at the EN-
ABLE and INPUT pins assure in case of open in-
put conditions that the device is switched off. An
output voltage slope limitation for du/dt is imple-
mented to reduce the EMI. An integrated active
flyback voltage limitation clamps the output volt-
age during the flyback phase to 50 V.
Each driver is protected against short circuit at
V
OUT
< 32V and thermal overload. In short circuit
condition the output will be disabled after a short
delay time t
DOL
. The thermal disable for TJ >
180
C of the output will be reseted if the junction
temperature decreases about 20
C below the dis-
able threshold temperature.
The overtemperatureinformation is stored until IN = L.
For the real time error diagnosis the voltage and
the current of the outputs are compared with in-
ternal fixed values V
OUV
for OFF and I
OUC
for ON
conditions to recognize open load (R
L
20 K
,
R
L
> 38
) in OFF and ON conditions.
Also the output voltages V
O1
- 4 are compared to
each other output in OFF condition with a fixed
offset of
V
OUV
to recognize load bypasses. To
suppress the
V
OUV
diagnoses during the flyback
phases of the compared output, the
VOUV diag-
nostic includes a latch function.
Reaching the flyback clamping voltage V
OCL
the
diagnostic signal is reseted by a latch. To activate
again this kind of diagnostic a low signal at the
correspondent INPUT or the ENABLE pin must
be applied (see also Fig.3). The outputs 1 and 4
are compared for
V
OUV
and also outputs 2 and 3
are compared.
The diagnostic output level in connection with dif-
ferent ENABLE and INPUT conditions allows to
recognize different fail states, like overtemp, short
to V
SS
, short to GND, bypass to GND and
dis-
connected load (see diagnostic table).
The diagnostic output is protected against short
circuit. Exceeding the over load current threshold
I
OOC
, the output current will be limited internally
during the diagnostic overload delay switch-off
time t
DOL
.
The device complies the ISO pulses imposed to
the supply voltage of the valves without any fail-
ures of the functionality.
5V
t
t
5V
t
5A
3A
IN
V
I O
I OOL
I OUC
D
V
t
DOL
Figure 3. Diagnostic Overload Delay Time
L9346
8/13
E N , IN
V
O N
0.85 x VO UT
0.15 x V
O U T
,
D O N
t
t D EN ON
,
DO FF
t
t
DE N OFF
Figure 5. TIMING (t
DENON
, t
DON
, t
DENOFF
, t
DOFF
)
5V
t D ON
t
t
t
0.85 VS
0.15 VS
VS
V
IN
V
OUT
V
V
(EN)H
(EN)L
S ON
V
t
V
DIAG
0.5 V
D
D
V
O U V
S OFF
0.85VS
tD E N O N
tD E N O F F
t
D
H -L D ia g
D OFF
Figure 4. OUTPUT SLOPE (Resistive load for testing)
L9346
9/13
&
&
Latch
Latch
L1 (L2)
L4 (L3)
OUT1
OUT4
V
Batt.
+
-
+
-
55%
VS
&
&
R
S
Q
R
S
Enable
Q
RIO
R IO
IN 1
V O UV1
( OU T 2)
(OU T 3)
I N 4
V O U V4
Figure 7. BLOCK DIAGRAM - Open Load Voltage Detection
IN
Open load current
DIOU
t
DOL
t
V
D
OUC
I
I
OOC
VON
Figure 6. TIMING (t
DOL
, t
DIOU
)
L9346
10/13
VO u
IO
o
V
E N
V
IN
IO
u
V
D
o
pen
l
o
a
d
c
u
r
r
e
n
t
op
en
l
o
ad
v
o
l
t
ag
e
o p e n lo a d
v o lta g e
o p en l oa d
c urrent
o
pen
l
o
a
d
c
u
r
r
e
n
t
O N
nor ma l
opera tion
latched o ve r.
load di agno stic
l
a
t
c
h
r
es
et
ON
nor ma l
ope ration
nor ma l
operation
O FF
Figure 8. Logic Diagram
Z VALVE
Z VALVE
Controller
+5V
P
Z VALVE
Z VALVE
I/O
I/O
KL 15
KL 30
+45V
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
+5V
+5V
+5V
V Batt
O U T 1
O U T 4
V S
C ha nne l 1
C ha nne l 4
O ut pu t
C o ntr ol
Ov er tem p
R
Q
S
D e la y
T im e r
O v erlo a d
O p enloa d
G N D
D 4
IN 4
E N
D 1
IN 1
R IO
D iagn o s tic
C o ntr ol
O U T 2
C ha nne l 2
D 2
IN 2
O U T 3
C ha nne l 3
D 3
IN 3
52 V
Figure 9. Application Circuit Diagram
L9346
11/13
JEDEC MO-166
PowerSO20
e
a2
A
E
a1
PSO20MEC
DETAIL A
T
D
1
11
20
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
R
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
b
c
N
N
H
BOTTOM VIEW
E3
D1
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.6
0.142
a1
0.1
0.3
0.004
0.012
a2
3.3
0.130
a3
0
0.1
0.000
0.004
b
0.4
0.53
0.016
0.021
c
0.23
0.32
0.009
0.013
D (1)
15.8
16
0.622
0.630
D1
9.4
9.8
0.370
0.386
E
13.9
14.5
0.547
0.570
e
1.27
0.050
e3
11.43
0.450
E1 (1)
10.9
11.1
0.429
0.437
E2
2.9
0.114
E3
5.8
6.2
0.228
0.244
G
0
0.1
0.000
0.004
H
15.5
15.9
0.610
0.626
h
1.1
0.043
L
0.8
1.1
0.031
0.043
N
10
(max.)
S
T
10
0.394
(1) "D and F" do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006").
- Critical dimensions: "E", "G" and "a3"
OUTLINE AND
MECHANICAL DATA
8
(max.)
10
L9346
12/13
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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L9346
13/13
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