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Электронный компонент: L9348-DIE1

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1/13
L9348
March 2002
s
SUPPLY VOLTAGE RANGE: 4.8 TO 18V
s
OUTPUT VOLTAGE UP TO 40V
s
OUTPUT VOLTAGE CLAMP DURING
RECIRCULATION OF INDUCTIVE LOADS
s
OUTPUT CURRENT CAPABILITY 2 X 5A AND
2 X 3A
s
LOW POWER DISSIPATION DURING
RECIRCULATION OF INDUCTIVE LOADS BY
INTEGRATED FREE WHEELING DIODES
(3A-DRIVERS ONLY)
s
LOW ON-RESISTANCE 2 X 0.2
, 2 X 0.35
(TYP.)
s
OUTPUT SHORT CIRCUIT CURRENT
PROTECTION
s
REAL TIME DIAGNOSTIC FUNCTIONS
s
OVERTEMPERATURE SHUTDOWN
s
SIGNAL- AND POWER-GROUND-LOSS
SHUTDOWN
s
3.3V CMOS COMPATIBLE INPUTS AND
STATUS
DESCRIPTION
The L9348 is a monolithic integrated quad low side
driver realized in advanced Multipower-BCD technol-
ogy. It is intended to drive inductive loads (relays,
electromagnetic valves) in automotive and industrial
applications.
PowerSO-36
BARE DIE
ORDERING NUMBERS:
L9348
L9348-DIE1
QUAD LOW SIDE DRIVER
Figure 1. Block Diagram
VS
+
VREG
=
Voltage Regulator
V
CC
V
DD
V
S
V
REG
GL
TSD
SCP
OL
V
S
FAIL
1
C 166kHz
PWRES
CHANNEL1
EN
PWRES
V
DD
PWRES
C 166kHz
V
S
EN
IN1
ST1
IN2
ST2
ENA
GND
99AT0073
PGND2
Q2
PGND1
Q1
V
DD
EN
Diagnostic
CHANNEL2
PWRES
C 166kHz
EN
V
REG
FB
GL
TSD
SCP
OL
V
S
FAIL
1
C 166kHz
PWRES
CHANNEL3
EN
IN3
ST3
PGND3
Q3
V
DD
EN
Diagnostic
D3
IN4
ST4
CHANNEL4
PWRES
C 166kHz
EN
PGND4
Q4
D4
5A - DRIVER
3A - DRIVER
L9348
2/13
Figure 2. Pin Connection
Table 1. Pin Description
N
Pin
Function
1, 18,
19, 36
N.C.
(GND)
2, 3
PGND3
Power Ground Channel 3
4, 5
Q3
Power Output Channel 3 (3A switch)
6, 7
D3
Recirculation Diode Channel 3
8, 9
Q1
Power Output Channel 1 (5A switch)
10, 11
Q2
Power Output Channel 2 (5A switch)
12, 13
D4
Recirculation Diode Channel 4
14, 15
Q4
Power Output Channel 4 (3A switch)
16, 17
PGND4
Power Ground Channel 4
20
ST4
Status Output Channel 4
21
IN2
Control Input Channel 2
22
IN4
Control Input Channel 4
23
ST2
Status Output Channel 2
24
ENA
Enable
25, 26
PGND2
Power Ground Channel 2
27
GND
Signal Ground
28
VS
Supply Voltage
29
N.C.
Not Connected
30, 31
PGND1
Power Output Channel 3
32
ST1
Status Output Channel 1
33
IN3
Control Input Channel 3
34
IN1
Control Input Channel 1
36
N.C.
35
ST3
IN1
34
IN3
33
32
ST1
31
30
29
N.C.
VS
28
GND
27
26
25
ENA
24
23
ST2
IN4
22
IN2
21
20
ST4
N.C.
19
N.C.
1
PGND3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
N.C.
99AT0074
Q3
D3
Q1
Q2
D4
Q4
PGND4
PGND1
PGND2
3/13
L9348
Table 2. Thermal Data
Table 3. Absolute Maximum Ratings
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is
subjected to conditions which are beyond these values.
Note: Human Body Model according to MIL883C. The device withstands ST1 class level.
Table 4. Operating Range
.
Symbol
Parameter
Test Conditions
Values
Unit
Min.
Typ.
Max.
T
j
Junction temperature
-40
150
C
T
jc
Junction temperature during
clamping (life time)
t = 30min
t = 15min
175
190
C
C
T
stg
Storage temperature
-55
150
C
R
th j-case
Thermal resistance junction to
case
2
C/W
Symbol
Parameter
Test Conditions
Value
Unit
Voltages
V
S
Supply voltage range
-0.3 to 40
V
V
Q
, V
D
max. static Output voltage
40
V
V
IN
, V
EN
Input voltage range
(IN1 to IN4, EN)
|I
I
| < 10mA
-1.5 to 6
V
V
ST
Status output voltage range
|I
I
| < 1mA
-0.3 to 6
V
V
DRmax
max. Reverse breakdown
voltage free wheeling diodes
D3, D4
I
R
= 100
A
55
V
Currents
I
Q 1/2
Output current at reversal
supply for Q1, Q2
-4
A
I
Q 3/4
Output current at reversal
supply for Q3, Q4
-2
A
I
ST
Status output current range
-1 to 1
mA
E
Q1/2
max. Discharging energy for
inductive loads per channel
Q1, Q2
T
j
= 25C
50
mJ
T
j
= 150C
30
mJ
I
FDmax
max. load current free
wheeling diodes
t < 5ms
3
A
ESD Protection
Supply and Signal pins
versus GND
2
kV
Output pins (Q
X
, D
X
)
versus common ground (=short of
SGND with all PGND)
4
kV
Symbol
Parameter
Test Conditions
Values
Unit
Min.
Typ.
Max.
V
S
Supply voltage
4.8
18
V
T
j
Junction temperature
-40
150
C
L9348
4/13
Table 5. Electrical Characteristcs
The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Power Supply
I
S
Supply current
V
IN1...IN4, ENA
= H
8
mA
I
Q
Quiescent current (outputs OFF)
V
ENA
= L
6
mA
I
D3/4
Quiescent current at pins D3/4
V
D3/4
18V;
V
IN3/4
= L
10
400
A
Diagnostic Functions
V
QU1 to 4
Output open load voltage
threshold
V
S
6.5V
V
EN
= X; V
IN
= L
0.3
0.33
0.36
x V
S
I
QU1 to 4
Output open load current
threshold
V
S
6.5V
V
EN
= H; V
IN
= H
50
140
mA
I
QO1/2
Overload current threshold Q 1, 2 V
S
6.5V
5
7.5
9
A
I
QO3/4
Overload current threshold Q 3, 4 V
S
6.5V
3
5
8
A
T
th
Overtemperature shutdown
threshold
2)
175
210
C
T
hy
Overtemperature hysteresis
10
C
V
thPGL
Power-GND-loss threshold
1.5
2.5
3.5
V
V
thSGL
Signal-GND-loss threshold
150
330
510
mV
Power Outputs (Q1 to Q4)
R
DSON1/2
Static drain-source ON-resistance
Q1, Q2
I
Q
= 1A; V
S
9.5V
T
j
= 25C
0.2
T
j
= 125C
3)
0.5
T
j
= 150C
4)
0.5
R
DSON3,4
Static drain-source ON-resistance
Q3, Q4
I
Q
= 1A; V
S
9.5V
T
j
= 25C
0.35
T
j
= 125C
3)
0.75
T
j
= 150C
4)
0.75
V
Z
Z-diode clamping voltage
= threshold of flyback detection
Q3/4
I
Q
100mA,
pos. supply V
D3/4
45
60
V
V
C
Clamping voltage
I
Q
100mA,
neg. supply V
D3/4
4
10
V
I
PD
Output pull down current
V
ENA
= H, V
IN
= L
10
20
50
A
5/13
L9348
(1).See chapter 2.0 Timing Diagrams; resistive load condition; V
S
9V
(2).This parameter will not be tested but assured by design
(3).Wafer-measurement
(4).Measured on P-SO36 devices
(5).Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
I
Qlk
Output leakage current
V
ENA
= L,T
j
= 25C
1
A
T
j
= 125C
5
A
V
FD3/4
Forward voltage of
free wheeling diodes D3, D4
I
D3/4
= -1.5A
0.5
1.75
V
R
PD0
Gate pull down resistor for
nonsupplied V
S
V
S
=
0V,
V
D3/4
6.5V
0.3
3
k
Timings
t
ON
Output ON delay time
I
Q
= 1A
1)
0
5
20
s
t
f
Output ON fall time
I
Q
= 1A
1)
0.5
1.5
8
s
t
OFF
Output OFF delay time
I
Q
= 1A
1)
0
10
30
s
t
r
Output OFF rise time
I
Q
= 1A
1)
0.5
1.5
5
s
t
DSO
Overload switch-OFF delay time
6
30
65
s
t
D
Output OFF status delay time
0.75
1.5
2.25
ms
t
filter
error detection filter time
2)
5.8
35
s
t
OLOFF
OLOFF error detection filter time
20
70
s
Digital Inputs (IN1 to IN4, ENA)
V
IL
Input low voltage
-1.5
1
V
V
IH
Input high voltage
2
6
V
V
IHy
Input voltage hysteresis
2)
50
100
mV
I
IN
Input pull down current
V
IN
= 5V, V
S
6.5V
8
20
40
A
Digital Outputs (ST1 to ST4)
V
STL
Status output voltage in low state
5)
I
ST
40
A
0
0.4
V
V
STH
Status output voltage in high state
5)
I
ST
-40
A
2.5
3.45
V
I
ST
-120
A
2
3.45
V
R
DIAGL
R
OUT
+ R
DSON
in low state
0.3
0.64
1.5
k
R
DIAGH
R
OUT
+ R
DSON
in high state
1.5
3.2
7
k
Table 5. Electrical Characteristcs
The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
L9348
6/13
1.0 FUNCTIONAL DESCRIPTION
1.1
Overview
The four low-side switches are designed to drive inductive loads (relays, electromagnetic valves). For the 3A
switches (Q3/4) integrated free-wheeling diodes (D3/4) are available and can be used as recirculation path for
inductive loads. If either integrated nor external free-wheeling diodes are used the output voltage is clamped
internally during discharge of inductive loads. The switches are controlled by CMOS compatible inputs (IN1-4)
if the enable input is set to "high". The status of each switch is monitored by the related status output (ST1-4).
1.2
Input Circuits
The control and enable inputs are active high, featuring switching thresholds with hysteresis and pull-down cur-
rent sources. Not connected inputs are interpreted as "LOW". If the enable input is set to "LOW" the outputs are
switched off independent of the control input state (IN1-4).
1.3
Switching Stages
The four power outputs consist of DMOS-power transistors. The output stages are protected against short circuit
to supply. Integrated output voltage clamp limits the output voltage in case of inductive load current flyback. In-
ternal pull down current sources are provided at the outputs to assure a defined conditon in OFF mode. They
will be disconnected in the disable mode (ENA=L). If the supply of the device gets lost but the loads and D3/4
are still supplied, an internal pull down resistor discharges the gate of the DMOS-power transistor to avoid
switch on due to capacitive coupling.
1.4
Status Outputs
The CMOS compatible status outputs indicate the state of the drivers (LOW-level indicates driver in OFF state,
HIGH-level indicates driver in ON state). If an error occurs the status output voltage changes like described in
chapter 1.6 Error Detection.
1.5
Protective Circuits
The outputs are protected against current overload, overtemperature, and Power-GND-loss.
1.6
Error Detection
Two main error types are distinguished in the diagnostic logic. If current overload, overtemperature, signal-
GND-loss or a power-GND-loss occurs, the status output signal is inverted, an internal register is set and the
driver is shutdown. The reset is done by switching off the corresponding control input or the enable input for at
least the time t
D
(defined to 1.5ms typ.). See also Figure 6 in chapter 2.0 Timing Diagrams.
All other errors (openload, active output voltage clamp) only cause an inverted status output signal but no shut-
down of the driver. An internal register is set too, but the reset is triggered automatically after the time t
D
, if the
error condition is no longer valid (see Figure 7 and Figure 8).
Excepting the detection of the active output voltage clamp all errors are digitally filtered before they are inter-
preted by the diagnostic logic.
The table 6 below shows the different failure conditions monitored in ON and OFF state:
Table 6.
ON State
ENA = HIGH,
IN = HIGH
OFF State
ENA = HIGH,
IN = LOW
typ. Filter
time
Reset done by
Overloading of output
(also shorted load to supply)
X
18
s
ENA or INx = "LOW"
for t
1.5ms (typ.)
Open load
(under voltage detection)
X
44
s
internal timer (1.5ms typ.)
7/13
L9348
1.7
Diagnostic Output at Pulse Width Operation (PWM)
If an input is operated with a pulsed signal (f
1/
t
D
= 667 Hz typ.), the status does not follow each single pulse.
An internal delay t
D
of typ. 1.5ms leads to a continuous status output signal (see Figure 4 in chapter 2.0 Timing
Diagrams).
1.8
Diagnostic Table
In general the diagnostic follows the input signal in normal operating conditions. If any error is detected the di-
agnostic is inverted.
Open load
(under current detection)
X
18
s
internal timer (1.5ms typ.)
Overtemperature
X
18
s
ENA or INx = "LOW"
for t
1.5ms (typ.)
Power-GND-loss
X
X
18
s
ENA or INx = "LOW"
for t
1.5ms (typ.)
Signal-GND-loss
X
X
18
s
ENA or INx = "LOW"
for t
1.5ms (typ.)
Output voltage clamp active
(Q3/4 only)
X
-
internal timer (1.5ms typ.)
Table 7.
Operating Condition
Enable
Input
ENA
Control
Input
IN
Power
Output
Q
Status
Output
ST
Normal function
L
L
H
H
L
H/PWM
L
H/PWM
OFF
OFF
OFF
ON
L
L
L
H
Open load or short to ground
L
L
H
H
L
H/PWM
L
H/PWM
OFF
OFF
OFF
ON
X
X
H
L
Overload or short to supply
Latched overload
Reset latch
H
H
H > L
H
H/PWM
H/PWM
X
H/PWM > L
OFF
OFF
OFF
OFF
L
L
L
L
Overtemperature
Latched overtemperature
Reset latch
H
H
H > L
H
H/PWM
H/PWM
X
H/PWM > L
OFF
OFF
OFF
OFF
L
L
L
L
Table 6.
ON State
ENA = HIGH,
IN = HIGH
OFF State
ENA = HIGH,
IN = LOW
typ. Filter
time
Reset done by
L9348
8/13
2.0 TIMING DIAGRAMS
Figure 3. Output slope with Resistive Load
Figure 4. Diagnostic Output at PWM operation
t
V
IN
t
V
Q
t
ON
t
f
100% V
Q
t
OFF
t
r
15% V
Q
85% V
Q
99AT0061
note: parameters are not shown proportionally
99AT0063
t
I
Q
I
QU
t
V
ST
t
D
note: parameters are not shown proportionally
t
V
IN
t
D
delayed status signal
9/13
L9348
Figure 5. Overload Detection
Figure 6. Driver Shut Down in Case of Overload
99AT0062
t
I
Q
I
QO
I
QU
t
V
ST
t
DSO
overload detected
driver shut down
t
filter
error condition
signalized
note: parameters are not shown proportionally
t
V
IN
99AT0064
t
I
Q
I
QO
t
V
ST
t
D
note: parameters are not shown proportionally
t
V
IN
t
D
driver is shuted
down and locked
driver is now free again
error is signalized
L9348
10/13
Figure 7. Under Current Condition
Figure 8. Open Load Condition in Off State
99AT0065
t
I
Q
I
QU
t
V
ST
note: parameters are not shown proportionally
t
V
IN
t
D
under current condition signalized
t
filter
under current condition detected
status signal is changed by internal reset
99AT0066
t
V
Q
V
QU
t
V
ST
note: parameters are not shown proportionally
t
V
IN
t
D
t
detection
openload condition detected
but not signalized due to:
t
detection
< t
OLOFF
t
OLOFF
t
detection
t
OLOFF
openload condition detected
and signalized due to:
t
detection
> t
OLOFF
11/13
L9348
Figure 9. Output Voltage Clamp Detection
3.0 PAD POSITIONS
Chip Size: 5.17 x 2.76 mm
2
Figure 10.
99AT0067
t
V
Q3/4
V
Z
t
V
ST3/4
note: parameters are not shown proportionally
t
V
IN3/4
t
D
time between two clamping periods is
shorter than internal delay time
-> status signal remains low
t
clamp
t
clamp
PGND4
Q4
D4
D3
Q2
Q1
Q3
PGND3
PGND1
PGND2
GND
VS
ST1
IN3
IN1
ST3
ENA
ST2
IN4
IN2
ST4
L9348
12/13
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.60
0.141
a1
0.10
0.30
0.004
0.012
a2
3.30
0.130
a3
0
0.10
0
0.004
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D (1)
15.80
16.00
0.622
0.630
D1
9.40
9.80
0.370
0.385
E
13.90
14.50
0.547
0.570
e
0.65
0.0256
e3
11.05
0.435
E1 (1)
10.90
11.10
0.429
0.437
E2
2.90
0.114
E3
5.80
6.20
0.228
0.244
E4
2.90
3.20
0.114
0.126
G
0
0.10
0
0.004
H
15.50
15.90
0.610
0.626
h
1.10
0.043
L
0.80
1.10
0.031
0.043
N
10
(max.)
S
8
(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
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13/13
L9348