1/17

L9362

May 2002

QUAD LOW-SIDE DRIVER FOR AUTOMO-
TIVE APPLICATION

CURRENT FEEDBACK OUTPUT FOR EACH
POWER STAGE

5V SUPPLY VOLTAGE

INTERNAL FAILURE DIAGNOSTIC

OUTPUT VOLTAGE SLOPE CONTROL FOR
LOW ELECTRO MAGNETIC EMISSIONS

INTERNAL SHORT CIRCUIT PROTECTION

OVERTEMPERATURE PROTECTION AND
OVERCURRENT PROTECTION AND DISABLE

SWITCHING FREQUENCY UP TO 2kHZ

INTERNAL ZENER CLAMP OF THE OUTPUT
VOLTAGE FOR INDUCTIVE LOADS

PARALLEL INPUT

SPI FOR DIAGNOSTIC INFORMATION EX-
CHANGE

RESET INPUT

TYPICAL INTERNAL OSCILLATOR FRE-
QUENCY 325kHZ

DESCRIPTION

The Quad Driver is an integrated quad low-side
power switch with power limitation, load interrupt
and shorted load detection, thermal shutdown, er-
ror detection via SPI interface and integrated Z-di-
odes for output clamping, free running diodes.

PowerSO36

ORDERING NUMBER: L9362

QUAD LOW SIDE DRIVER

BLOCK DIAGRAM

99AT0007

Driver

Trigger

dV/dt

Control

Overtemp.

I_SCB Filter

t_SCB

NON1

I_OL Filter

t_OL

NON1

SCG Filter

t_SCG

NON1

Failure

(FR)

Shift

RESET

Reset

IRES

RESET

Reset

Oscillator

OSC

Under

voltage
RESET

CFB1

CFB2

CFB3

CFB4

PGND4

PGND3

PGND2

PGND1

OUT4

OUT3

OUT2

OUT1

VCC

NON1

NON2

NON3

NON4

SDI

CLK

NSC

SDO

IRES

NRES

SGND

LGND

L9362

2/17

PIN CONNECTION

PIN FUNCTIONS

Pin No.

Pin Name

Pin Description

Notes

PGND1

Power Ground

N.C.

CFB1

Output Current feedback

Sinks current proportional to I

OUT1

Output Power Switch

OUT1

Output Power Switch

CLK

Input Clock

Digital input, Schmitt trigger, internal Pullup current

NCS

inverted Chip Select Input

Digital input, Schmitt trigger, internal Pullup current

N.C.

SGND

Signal Ground

LGND

Ground of digital part

N.C.

SDO

Serial Data Output

Digital tristate output

SDI

Serial Data Input

Digital input, Schmitt trigger, internal Pullup current

OUT4

Output Power Switch

OUT4

Output Power Switch

CFB4

Output Current feedback

Sinks current proportional to I

OUT4

N.C.

PGND4

Power Ground

PGND3

Power Ground

N.C.

CFB3

Output Current feedback

Sinks current proportional to I

OUT3

Output Power Switch

OUT3

Output Power Switch

NON4

Inverted Control Signal Input

Digital input, Schmitt trigger, internal Pullup current

99AT0012

PGND2
N.C.
CFB2
OUT2
OUT2
NON1
NON2
N.C.
VCC
N.C.
NRES
NON3
NON4
OUT3
OUT3
CFB3
N.C.
PGND3

Frame connected to PGND

PGND1

N.C.

CFB1

OUT1
OUT1

CLK

NCS

N.C.

SGND

LGND

N.C.

SDO

SDI

OUT4
OUT4

CFB4

N.C.

PGND4

3/17

L9362

THERMAL DATA

ABSOLUTE MAXIMUM RATINGS
For externally applied voltages or currents exceeding these limits damage of the circuit may occur

Note:

The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent
damage to the IC will result.

NON3

Inverted Control Signal Input

Digital input, Schmitt trigger, internal Pullup current

NRES

Inverted Reset Input

Digital input, Schmitt trigger, internal Pullup current

N.C.

VCC

5V Supply Voltage Input

N.C.

NON2

Inverted Control Signal Input

Digital input, Schmitt trigger, internal Pullup current

NON1

Inverted Control Signal Input

Digital input, Schmitt trigger, internal Pullup current

OUT2

Output Power Switch

OUT2

Output Power Switch

CFB2

Output Current feedback

Sinks current proportional to I

OUT2

N.C.

PGND2

Power Ground

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Thermal resistance

th j-case

Thermal resistance junction to case
(one powerstage in use)

Die must be
soldered on the
frame.

4.5

�C/W

thja

Thermal resistance junction-ambient

pad layout

�C/W

thja

Thermal resistance junction-ambient

pad layout + 6 cm

on board heat sink

�C/W

ESD

ESD

MIL 883C

�

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltages

Supply voltage

-0.3

Outputs (Out 1 ... 4)

Out

Continues output voltage

With no reverse
current.

-0.3

outc

Continues current

3.0

SCBpeak

Peak output current

-10

I_SCB

OFF

Clamped energy at the switching OFF

For 2ms, see fig. 8

Inputs (NONx; NCS; CLK; NRES; SDI)

Input voltage

-0.3

Outputs (SDO; CFB)

OUT

Output voltage

-0.3

+0.3

Operating junction temperature

Operating junction temperature

-40

150

�C

PIN FUNCTIONS (continued)

Pin No.

Pin Name

Pin Description

Notes

L9362

4/17

ELECTRICAL CHARACTERISTICS
4.5V

5.5V, -40�C

125�C, unless otherwise specified.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply current

CCRES

Standby current

Without load.
T

85�C

NRES = LOW

1.3

CCOPM

Operating mode

OUT 1 ... 4

= 2A

CCLV

Low voltage supply current

< 0,5V

�

Inputs (NONx; NCS; CLK; NRES; SDI)

INL

Low threshold

-0.3

0.2

�

INH

High threshold

0.7

�

+0.3

hyst

Hysteresis

0.85

Input leakage current

= V

�

Input current (NONx, NCS, CLK,
SDI)

0.8

�

100

�

IN NRES

Input current NRES

�

Serial Data Output

SDOH

High output level

SDO

= -2mA)

- 0.4

SDOL

Low output level

SDO

= 3.2mA)

0.4

SDOL

Tristate leakage current

(NCS = HIGH;
V

SDO

= 0V ... V

)

-10

�

Outputs (Out 1 ... 4)

OUTL1

Leakage current 1

(NON = HIGH;
V

OUT

= 14V;

= 5V)

�

clpa

Output clamp voltage

clpa

OUT

= 0.5A)

OFF

Clamped energy at the switching

OFF

For 2ms, see fig. 8

DSON

ON resistance

OUT

= 2A; T

= 150�C;

= 25�C

250

500
300

OVR

Positive output voltage ramp
(with inductive load)

OUT

= 30% ... 80% of

BAT

=16V 3)

OUT

BAT

... 0.9

�

clp

0.3

0.75

0.9

1.35

2.25

�

OVR

Negative output voltage ramp

80% ... 30% of V

BAT

= 16V

with inductive load

0.3

0.9

1.35

�

dON

Turn ON delay

NON = 50%;
V

OUT

= 0.8

�

BAT

�

dOFF

Turn OFF delay

NON = 50%;
V

OUT

= 0.3

�

BAT

�

Note 1:

Typical loads for the zener clamping and the output voltage ramps are:
a) 10

, 16mH at all outputs or

b) 25

, 160mH

Note 2:

At 150�C guaranteed by design and electrical characterisation

Note 3:

Tested with resistive load of R

load

= 50

5/17

L9362

Powerstage protection

SCB

Short current detection and switch
off threshold

With filter-time t_SCB.

3.0

5.0

t_SCB

Short circuit switch off delay time

�

ccmin

undervoltage

3.0

4.0

Current feedback

Ratio 1

CFB

/ I

OUT

for I

OUT

=0.4...2A

CFB

1.8V

1.45

1.65

mA/A

MPS1

Temperature stability
for 0.4A to < 2.0A, related to
25�C

�

CURS1

for I

OUT

= 0.4A to 2A

Current stability

gain/Gain at 2A

= -40�C

-12

= +25�C

-6

= +125�C

-5

CURlin1

CURlin2

for I

OUT

= 0.4A to 1.0A

for I

OUT

= 1.0A to 2.0A

Linearity Error
(within the calibration points
at 0.5A, 1A, 2A)

�

0.2

�

0.7

%
%

Note 4:

At 150�C guaranteed by design and electrical characterisation

Note 5:

Guaranteed by design and electrical characterisation

Note 6:

Values for T

MPS1

, CURlin1 and CURlin2 are typical values from testing results

Diagnostic

REF1

Short to GND threshold voltage

for I

OUT

0.390

�

0.435

�

t_SCG

Short to GND filter time

140

250

�

Open load threshold current

t_OL

Open load filter time

140

265

�

Pullup resistor at OUT1, OUT2,
OUT3 and OUT4 for OL detection

2.0

8.0

OFF

Temperature detection threshold

155

170

190

�C

Note 7:

Guaranteed by measurement and correlation

ELECTRICAL CHARACTERISTICS (continued)
4.5V

5.5V, -40�C

125�C, unless otherwise specified.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

L9362

6/17

Note: 8.

Input Pin Capacitance of SDI, CLK, NCS, NON1, NON2, NON3, NON4 6pF typical; Output Pin Capacitance of SDO 12pF typica

Serial diagnostic link (external Load capacitor at SDO = 100pF)

clk

Clock frequency

50% duty cycle.

MHz

clh

Minimum time CLK = HIGH

100

cll

Minimum time CLK = LOW

100

pcld

Propagation delay

CLK to data at SDO valid.

100

csdv

NCS = LOW

To data at SDO valid.

100

sclch

CLK low before NCS low

Setup time CLK to NCS
change H/L.

100

hclcl

CLK change L/H after
NCS = LOW

100

scld

SDI input setup time

CLK change H/L after SDI
data valid.

hcld

SDI input hold time

SDI data hold after CLK
change H/L.

sclcl

CLK low before NCS high

150

hclch

CLK high after NCS high

150

pchdz

NCS L/H to output data float

100

fNCS

NCS filter-time

Pulses

fNCS

will be

ignored.

ELECTRICAL CHARACTERISTICS (continued)
4.5V

5.5V, -40�C

125�C, unless otherwise specified.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

7/17

L9362

1.0 Diagnostic Register and SPI timing

Figure 1. Impulse diagram to read the Diagnostic Register

Note: FR_RESET means Reset failure storage (internal signal)

Figure 2. Diagnostic Failure Register Structure

FR_RESET

SDI

LSB

99AT0008

MSB

SDO

CLK

NCS

LSB

FSL

MSB

99AT0009/A

FSL

MSB

LSB

Failure indicator bit
(only valid during NCS = LOW
to the first L to H CLK change
1: failure stored
0: no failures

Status channel 4
D0 D1 Status

no failures

open circuit, channel on

short to battery or overtemperature

short to gnd, channel off

Status channel 3
D2 D3 corresponding to D0 D1

Status channel 2
D4 D5 corresponding to D0 D1

Status channel 1
D6 D7 corresponding to D0 D1

L9362

10/17

Figure 6. Different cases for an Open Load failure detection (case 1 to 10)

00AT0004

CASE 10

Failure Register
Status

Output
Current

CASE 9

Failure Register

Output
Current

Status

CASE 8

CASE 7

Current

Output

Failure Register
Status

CASE 6

Failure Register

Output
Current

Status

CASE 5

Failure Register

Output
Current

Status

Failure Register

Output
Current

CASE 4

Status

CASE 3

Current

Output

Failure Register
Status

Failure Register

CASE 2

Reset

Failure Register

Non Input

CASE 1

Status

IOL = OL filter time

IOL

Non Input

Output
Current

IOL

Output
Current

Failure Register
Status

IOL

Failure Register
Status

11/17

L9362

Figure 7. Different cases for an Open Load failure detection (case 11 to 20)

Output
Current

Status

Failure Register

Failure Register
Reset

Non Input

CASE 20

Failure Register
Status

Output
Current

CASE 19

Failure Register

Output
Current

Status

CASE 18

CASE 17

Current

Output

Failure Register
Status

CASE 16

Failure Register

Output
Current

Status

CASE 15

Failure Register

Output
Current

Status

Failure Register

Output
Current

CASE 14

Status

CASE 13

Current

Output

Failure Register
Status

Failure Register

Output
Current

CASE 12

Status

Failure Register

Output
Current

CASE 11

Status

IOL

00AT0005

IOL

13/17

L9362

Figure 10. TMPS1 vs. Temperature (4.5V

5.5V; 0.5A

out1...4

3A).

FUNCTIONAL DESCRIPTION

Introduction
The Quad Low Side Driver UF07 is built up of four identical channels (Low Side Drivers), controlled by four
CMOS input stages. Each Channel is protected against short to V

Bat

and by a zener clamp against overvoltage.

A diagnostic logic recognizes four failure types at the output stage: overcurrent, short to GND, open-load and
overtemperature.
The failures are stored individually for each channel in one byte which can be read out via a serial interface (SPI).
Each channel has a current feedback output which sinks a current proportional to the load current of the Low
Side Switch.

Output Stage Control
Each of the four output stages is switched ON and OFF by an individual control line (NON-Input). The logic level of
the control line is CMOS compatible. The output transistors are switched off when the inputs are not connected.

Power Transistors
Each of the four output stages has its own zener clamp. This causes a voltage limitation at the power transistors
when inductive loads are switched off. Output voltage ramp occurring when the output is switched on or off, is
within defined limits. Output transistors can be connected in parallel to increase the current capability. In this
case, the associated inputs, outputs and current feedback outputs should be connected together.

Diagnostics
Following failures at the output stage are recognized:
Short circuit to V

Bat

or overtemp................= SCB (Highest priority)

Short circuit to GND...................................=SCG
Open Load.................................................= OL (Lowest Priority)

-3

-2

-50

TMPS1/[%]

Temp./[�C]

100

150

200

-1

L9362

14/17

Short-Circuit and Overtemperature Protection (SCB)
If the output current increases above the short current limit for a longer time than t_SCB or if the temperature
increases above T

OFF

, then the power transistor is immediately switched off. It remains switched off until the

control signal at the NON-Input is switched off and on again. This filter time has the purpose to suppress wrong
detection on short spikes.
All four outputs have an independent overtemperature detection and shutdown. This measurement is active
while the powerstage is switched on.
The Short circuit detection and the overtemperature detection are using the same bit in the Diagnostic (one for
each channel).

A SCG failure will be recognized, when the drain voltage of the output stage is lower as the "Short Cut to Ground
threshold voltage", while the output stage is switched off (see Fig. 4). The SCG failure is filtered with a digital
filter (t_SCG) to suppress the storage of a failure at small SCG spikes, which are typical during the transition of
the power output. This filter is triggered by the NON input and the (analog) SCG detection.
If the current through the output stage is lower than the IOL-reference, then an OL failure will be recognized
after a filter time. This measurement is active while the powerstage is switched on.
The Open Load failure detection has 2 different modes, the statical failure detection and the sporadic failure
detection. One main difference is, that a statical failure is transferred to the Failure register with the next rising
edge of NON, whereas a sporadic failure is transferred immediately to the Failure register (see fig. 5, 6 and 7).
In both failure modes the OL detection is filtered (t_OL=t

) and is using together with the SCG detection the

same digital filter for suppression of spikes.
The failures are stored regarding to their priority (see above). A failure with a higher priority overwrites an even-
tually already detected failure with a lower priority.

Diagnostic interface
The communication between the microprocessor and the failure register runs via the SPI link. If there is a failure
stored in the failure register, the first bit of the shift register is set to a high level. With the H/L change at the NCS
pin the first bit of the diagnostic shift register will be transmitted to the SDO output. The SDO output is the serial
output from the diagnostic shift register and it is tristate when the NCS pin is high. The CLK pin clocks the diag-
nostic shift register. New SDO data will appear on every rising edge of the CLK pin and new SDI data will be
latched on every falling edge into the shift register. With the first positive pulse of the CLK the contents of the
failure register is copied to the SPI shift register and a internal reset (FR_RESET) is generated. This internal
reset clears the failure register and thus the failure register is capable of detecting failures also during the SPI
read cycle. There is no bus collision at a small spike at the NCS. The CLK has to be LOW, while the NCS signal
is changing.

Current feedback
Each channel has a current feedback output which sinks a current proportional to the load current of the Low
Side Switch. Using this output servo loop applications can be realized by applying a PWM signal to the NON
input. A typical diagram of the Current Feedback output at different temperatures is shown in figure 9.

15/17

L9362

Reset
There are two different reset functions realized:

Undervoltage reset

As long as the voltage of Vcc is lower than V

ccmin

, the powerstages are switched off, the failure register

is reset and the SDO output remains tristate.

External reset

As long as the NRES pin is low following circuits are reset:
Powerstages
Failure register
and the SDO output is tristate.

Undervoltage protection
At Vcc below V

ccmin

the device remains switched off even if there is a voltage ramp at the OUT pin.

Figure 11. Application Circuit

Reset

Under

voltage

RESET

99AT0011

Driver

Trigger

dV/dt

Control

Overtemp.

I_SCB Filter

t_SCB

NON1

I_OL Filter

t_OL

NON1

SCG Filter

t_SCG

NON1

Failure

(FR)

Shift

RESET

IRES

RESET

Oscillator

OSC

CFB1

CFB2

CFB3

CFB4

ADC

PGND4

PGND3

PGND2

PGND1

OUT4

OUT3

(optional
for all
channels)

OUT2

OUT1

VCC

NON1

NON2

NON3

NON4

�

SDI

CLK

NSC

SDO

IRES

NRES

SGND

LGND

L9362

16/17

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

3.60

0.141

0.10

0.30

0.004

0.012

3.30

0.130

0.10

0.004

0.22

0.38

0.008

0.015

0.23

0.32

0.009

0.012

D (1)

15.80

16.00

0.622

0.630

9.40

9.80

0.370

0.385

13.90

14.50

0.547

0.570

0.65

0.0256

11.05

0.435

E1 (1)

10.90

11.10

0.429

0.437

2.90

0.114

5.80

6.20

0.228

0.244

2.90

3.20

0.114

0.126

0.10

0.004

15.50

15.90

0.610

0.626

1.10

0.043

0.80

1.10

0.031

0.043

�

(max.)

�

(max.)

(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".

PowerSO36

PSO36MEC

DETAIL A

h x 45�

DETAIL A

lead

slug

Gage Plane

0.35

DETAIL B

(COPLANARITY)

- C -

SEATING PLANE

0.12

A B

BOTTOM VIEW

OUTLINE AND

MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

�

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L9362

Электронный компонент: L9362