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LIS2L01
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
s
THE SENSITIVITY IS ADJUSTED WITH A
TOTAL ACCURACY OF 2.5%
s
INTERNAL TWO POLES LOW PASS SC
FILTER WITH LINEAR OUTPUT, 30Hz
BANDWIDTH
s
THE OUTPUT VOLTAGE, OFFSET,
SENSITIVITY AND TEST VOLTAGE ARE
RATIOMETRIC TO THE SUPPLY VOLTAGE
s
DEVICE SENSITIVITY IS ON-CHIP FACTORY
TRIMMED
s
EMBEDDED SELF TEST
s
HIGH SHOCK SURVIVABILITY
DESCRIPTION
The LIS2L01 is a dual channel accelerometer that in-
cludes a sensor elements and an IC interface able to
take the information from the sensor and to provide
an analog signal to the external world.
The sensor element, capable to detect the accelera-
tion, is manufactured using a dedicated process
called ThELMA (Thick Epi-Poly layer for Microactua-
tors and Accelerometers) developed by ST to pro-
duce inertial sensor and actuator in silicon.
The IC interface instead is manufactured using a
CMOS process that allow high level of integration to
design a dedicated circuit which is trimmed to better
match the sensor element characteristics.
The LIS2L01 is capable of measuring acceleration in
the range of 1g with a bandwidth of 30Hz, set by a
2
nd
order low pass filter. A self-test capability verifies
the system providing to the user a signal on a dedi-
cated pin.
The LIS2L01 is available in plastic SMD package and
it is specified over a temperature range from 0C to
+80C.
The LIS2L01 is a part of family products suitable for
a variety of applications:
Virtual reality input devices
Computer hard disk drive protection
Computer mouse and joysticks
Vibration Monitoring, recording and compen-
sation
Appliance control
Robotics
SO-24
ORDERING NUMBER: LIS2L01
PRODUCT PREVIEW
INERTIAL SENSOR:
2Axis/1g LINEAR ACCELEROMETER
BLOCK DIAGRAM
MUX
TRIMMING CIRCUIT
& POLY FUSES
Sx
Sx
Sy
Sy
CHARGE
PREAMPLIFIER
MUX
VOUTx
VOUTy
SC
FILTER
&
CDS
VARIABLE GAIN
AMPLIFIER
SC
FILTER
&
CDS
VARIABLE GAIN
AMPLIFIER
D01IN1315
VOLTAGE &
CURRENT
REFERENCE
CLOCK &
PHASE
GENERATOR
LIS2L01
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PIN DESCRIPTION
PIN CONNECTION (Top view)
N
Pin
Function
1 to 5
NC
Internally not connected
6, 9, 10
Reserved
Leave unconnected or connect to GND
7, 8
Reserved
Leave unconnected or connect to Vdd
11, 12
NC
Internally not connected
13
Vdd
5V Supply
14
GND
0V Supply
15
VoutX
Voltage Output
16
ST
Self Test
17
VoutY
Voltage Output
18
Reserved
Leave unconnected or connect to GND
19
Reserved
Leave unconnected or connect to Vdd
20 to 24
NC
Internally not connected
N.C.
N.C.
N.C.
N.C.
N.C.
RESERVED
RESERVED
RESERVED
RESERVED
ST
VoutY
RESERVED
N.C.
RESERVED
N.C.
N.C.
N.C.
N.C.
1
3
2
4
5
6
7
8
9
22
21
20
19
18
16
17
15
23
10
24
RESERVED
VoutX
D01IN1314
N.C.
GND
11
14
13
12
N.C.
Vdd
DIRECTION OF THE
DETECTABLE
ACCELERATION
X
Y
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LIS2L01
ELECTRICAL CHARACTERISTCS (Temperature range 0C to 80C, supply voltage Vdd = 5V 5%.)
1
FUNCTIONALITY
1.1 Sensor element
The ThELMA process is utilized to create a surface micro-machined accelerometer. The technology allows car-
ry out silicon structure on suspension, the structure are attached to the substrate in few points called anchor
and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging tech-
niques a cap is placed on top the sensor element to avoid the molding goes between the elements making the
sensor useless.
The equivalent circuit for the sensor is shown in the below figure; when a linear acceleration is applied, the proof
mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is
measured using charge integration in response to a voltage pulse applied to the sense capacitor.
The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum
variation of the capacitive load is few tenth of pF.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vdd
Supply voltage
4.75
5
5.25
V
Idd
Supply current
10
mA
Voff
Zero-g level
T = 25C
ratiometric to Vdd
Vdd/2
0.1
Vdd/2
Vdd/2
+ 0.1
V
Ar
Acceleration range
TBD
1
TBD
g
So
Sensitivity ratiometric to Vdd
Vdd = 5V
T = 25C
1.8
2
2.2
V/g
fuc
Upper cutoff frequency low pass
filter
-3dB/2
nd
order filter
27
30
33
Hz
an
Equivalent noise acceleration
Bandwidth = 0.1...30Hz
1
mg
Vt
Self test output voltage
Ratiometric to Vdd
T = 25C
@ 5V
TBD
V
Vst
Self test input
Logic 1 voltage
Logic 0 voltage
3.75
Vss
Vdd
1.25
V
V
Cload
Capacitive load drive
100
pF
Rload
Resistive load output
50
k
LIS2L01
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Figure 1. Equivalent electrical circuit
1.2 IC Interface
The complete signal processing uses a fully differential structure, while the final stage converts the differential
signal into a single-ended to be compatible with the external world.
The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at the
output to cancel the offset and the 1/f noise.
The signal is processed through a 2
nd
order low pass filter in order to reject out of band noise, the filter cut off
frequency is set to be 30Hz.
This filter is implemented using SC technique, which allows to realize a fully integrated system that avoid the
use of any external component.
The low noise input amplifier operates at 100 kHz while the two SC filters operate at 50 kHz sampling frequency.
This allows a large oversampling ratio, able to reduce in-band noise and to obtain an accurate output waveform.
The signal at the output of the SC filter is sampled and held using a different clock to avoid that the filter output
value during the CDS phase reaches the output pin.
All the analog parameter (output offset voltage and sensitivity) are ratiometric to the supply voltage. Increasing
or decreasing the supply voltage, the sensitivity and the offset will increase or decrease linearly. The feature
provides the cancellation of the error related to the supply voltage in the analog to digital conversion chain.
1.3 Factory calibration
In the IC interface different calibrations take place at factory level to provide to final user a device ready to be
used, the trimmed parameters are: gain, offset and cut off frequency of the SC filter.
The trimmed value are stored in the device with a poly-fuse technique. Any time the device is turned on the
memorized bits are loaded into the registers to be utilized during the normal operation. The poly-fuse approach
allow the final user to use the device without any need for further calibration.
C
s1x
C
s2x
C
ps1
C
ps2
C
pr
R
s2
R
s1
R
r
S1x
rot
S2x
C
s1y
C
s2y
C
ps1
C
ps2
C
pr
R
s2
R
s1
R
r
S1y
S2y
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LIS2L01
SO24
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
A2
2.55
0.100
B
0.33
0.51
0.013
0.0200
C
0.23
0.32
0.009
0.013
D
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
0,050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
k
0 (min.), 8 (max.)
L
0.40
1.27
0.016
0.050
B
e
A2
A
1
13
24
D
L
H
A1
C
E
K
h x 45
SO24
Seating Plane
0.10mm
.004
A1
OUTLINE AND
MECHANICAL DATA
12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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LIS2L01
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