1/22

July 2004

COMPLETE INTERFACE BETWEEN LNB
AND I

BUS

BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION AND
HIGH EFFICIENCY (Typ. 94% @ 750mA)

TWO SELECTABLE OUTPUT CURRENT
LIMIT (450mA / 750mA)

ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED
STANDARDS

FAST OSCILLATOR START-UP FACILITATES
DiSEqC

ENCODING

BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqC

2.0

13/18V CONTROL WORD
COMMUNICATION

SEMI-LOWDROP POST REGULATOR AND
HIGH EFFICIENCY STEP-UP PWM FOR
LOW POWER LOSS: Typ. 0.56W @ 125mA

TWO OUTPUT PINS SUITABLE TO BYPASS
THE OUTPUT R-L FILTER AND AVOID ANY
TONE DISTORSION (R-L FILTER AS PER
DiSEqC 2.0 SPECs, SEE APPLICATION
CIRCUIT)

CABLE LENGTH DIGITAL COMPENSATION

OVERLOAD AND OVER-TEMPERATURE
INTERNAL PROTECTIONS I

C WITH

DIAGNOSTIC BITs

LNB SHORT CIRCUIT SOA PROTECTION
WITH I

C DIAGNOSTIC BIT

+/- 4KV ESD TOLERANT ON INPUT/
OUTPUT POWER PINS

DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBEH21 is
a monolithic voltage regulator and interface IC,
assembled in POWER SO-20, specifically
designed to provide the 13/18V power supply and
the 22KHz tone signalling to the LNB
downconverter in the antenna or to the multiswitch
box. The LNBEH21 supports both methods of
communication currently used, 13/18V Control
Word Communication Mode and DiSEqC

communication. In this application field, it offers a
complete solution with extremely low component
count, low power dissipation together with simple
design and I

standard interfacing.

LNBEH21

LNB SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I

C INTERFACE

TEN/VSEL

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Vup

VoRX

SDA

SCL

Vcc

Diagnostics

I睠 interf.

Tone

Detector

DSQOUT

VoTX

DETIN

LNBEH21

Byp

Gate

Sense

EXTM

ADDR

Vup-Feedback

Step-up PWM
Controller

ISEL

Oscill

13/18V control

Tone control

OM=low

OM=High

Echo-pulses control

RISE

= T

FALL

= 500祍

22KHz

BLOCK DIAGRAM

PowerSO-20

Rev. 1

LNBEH21

2/22

Table 1: Ordering Codes

Table 2: Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

Table 3: Thermal Data

Figure 1: Pin Configuration (top view)

TYPE

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

LNBEH21

LNBEH21PD

LNBEH21PD-TR

Symbol

Parameter

Value

Unit

DC Input Voltage

-0.3 to 16

DC Input Voltage

-03 to 25

Output Current

Internally Limited

TX/RX

DC Output Pins Voltage

-0.3 to 25

Logic Input Voltage (SDA, SCL, DSQIN, ISEL)

-0.3 to 7

DETIN

Detector Input Signal Amplitude

-0.3 to 2

Logic High Output Voltage (DSQOUT)

-0.3 to 7

GATE

Gate Current

� 400

SENSE

Current Sense Voltage

-0.3 to 1

ADDRESS

Address Pin Voltage

-0.3 to 7

stg

Storage Temperature Range

-40 to +150

癈

Operating Junction Temperature Range

-40 to +125

癈

Symbol

Parameter

Value

Unit

thj-case

Thermal Resistance Junction-case

癈/W

LNBEH21

3/22

Table 4: Pin Description

PIN N�

SYMBOL

NAME

FUNCTION

Supply Input

8V to 15V IC supply. A 220礔 bypass capacitor to GND with a 470nF
(ceramic) in parallel is recommended

GATE

External Switch Gate

External MOS switch Gate connection of the step-up converter

SENSE

Current Sense Input

DC/DC Current Sense comparator input. Connected to current
sensing resistor

Step-up Voltage

Input of the linear post-regulator. The voltage on this pin is monitored
by internal step-ut controller to keep a minimum dropout across the
linear pass transistor.

Output Port during
22KHz Tone RX

RX Output to the LNB in DiSEqC 2.0 application. See truth tables for
voltage selections and Communication Mode section for details.

SDA

Serial Data

Bidirectional data from/to I

C bus.

SCL

Serial Clock

Clock from I

C bus.

TEN/VSEL DiSEqC or 13/18V

TTL Logic Input

Depending on the value set for OM bit this pin enable/disable the
internal 22KHz tone generator (OM=0) or switch the output voltage
from 13V to 18V and vice versa (OM=1)

DETIN

Tone Detector Input

22kHz Tone Detector Input. Must be AC coupled to the DiSEqC 2.0
bus.

DSQOUT

DiSEqC Output

Open drain output of the tone Detector to the main

�

controller for

DiSEqC 2.0 data decoding. It is set LOW when a 22 KHz tone is
detected.

EXTM

External Modulator

External Modulation Input acts on V

TX. Needs DC decoupling to the

AC source. If not used, can be left open.

1, 6, 10,

11, 20

GND

GROUND

Pins connected to Ground. Also internally connected to the die frame
(exposed pad) for heat dissipation.

BYP

Bypass Capacitor

Needed for internal preregulator filtering

ISEL

Current Limit Select

Set high or floating for I

750mA, connect to ground for I

450mA.

Output Port during
22KHz Tone TX

Output of the linear post-regulator/modulator to the LNB. See truth
tables for voltage selections.

ADDR

Address Setting

Four I

C bus addresses available by setting the Address Pin level

voltage. See address pin characteristics table.

LNBEH21

4/22

TYPICAL APPLICATION CIRCUITS

Figure 2: Application Circuit for DiSEqC 1.x and Output Current < 450 mA

Figure 3: Full Application Circuit for Bi-directional DiSEqC 2.0 and Output Current up to 750mA

(*) R-L Filter to be used according to EUTELSAT recommendation to implement the DiSEqC

2.0, (see DiSEqC

implementation section).

If bidirectional DiSEqC

2.0 is not implemented the R-L filter can be removed and the above DiSEqC 1.x circuit can be used.

(**) Do not leave these pins floating if not used.
(***) To be soldered as close as possible to relative pins.
-C8 and D3,4 are needed only to protect the output pins from any negative voltage spikes during high speed voltage transitions.

LNBEH21

Vin

12V

L1=22礖

C10

(***)

10nF

VoTX

SDA

SCL

C5(***)
470nF

GND

0<V

ADDR

BYP

Rsc
0.1

(***)

470nF

Ceramic

D2 1N4001

C1
220礔

(***)

470nF
Ceramic

(***)

BAT43

IC1

STS4DNFS30L

IC2

C2
220礔

100礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

EXTM

DSQOUT

(**)

DETIN

VoRX

to LNB

ISEL

Byp

Set TTX=1

Tone Enable /
13/18 Selection

R1
3.3K

ADDRESS

VUP

VCC

GATE

SENSE

TEN/VSEL

LNBEH21

Vin

12V

L1=22礖

C10

(***)

10nF

VoTX

SDA

SCL

C5(***)
470nF

GND

0<V

ADDR

BYP

Rsc
0.1

(***)

470nF

Ceramic

D2 1N4001

C1
220礔

(***)

470nF
Ceramic

(***)

BAT43

IC1

STS4DNFS30L

IC2

C2
220礔

100礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

EXTM

DSQOUT

(**)

DETIN

VoRX

to LNB

ISEL

Byp

Set TTX=1

Tone Enable /
13/18 Selection

R1
3.3K

ADDRESS

VUP

VCC

GATE

SENSE

TEN/VSEL

C Bus

{

270礖

LNBEH21

Vup

Gate

Vin

12V

L1=22礖

Sense

Vcc

VoRX

VoTX

(**) DETIN

C7 (***)
100nF

to LNB

SDA

SCL

DSQOUT

TEN/VSEL

ADDRESS

Byp

C5 (***)
470nF

0<V

ADDR

BYP

0<V

ADDR

BYP

EXTM

C6
10nF

Rsc

0.05

GND

C3(***)
470nF
Ceramic

D2 1N4001

C1
220礔

C4 (***)
470nF
Ceramic

D3(***)
BAT43

D1
1N5821 or
STPS3L40A

IC1

MOS
STN4NF03L

D4 (***)
BAT43

C8 (***)
100nF

ISEL

C2
220礔

100礔

Iout<750mA

Iout<450mA

V>3.3V

(or floating)

Axial Ferrite Bead Filter

F1 suggested part number:

Murata BL01RN1-A62

Panasonic EXCELS-A35

(*) see note

Current Limit
Selection

Tone Enable /
13/18 Selection

R1
3.3K

Tone Enable /
13/18 Selection

R1
3.3K

LNBEH21

5/22

APPLICATION INFORMATION
This IC has a built in DC/DC Step-Up controller that, from a single supply source ranging from 8 to 15V,
generates the input voltages (V

) that let the linear post-regulator to work at a minimum dissipated power

of 1.65W typ. @ 750mA load (the linear regulator drop voltage is internally kept at: V

-V

OUT

=2.2V typ.).

An UnderVoltage Lockout circuit will disable the whole circuit when the supplied V

drops below a fixed

threshold (6.7V typically).
All the functions of this IC are controlled via I

bus by writing 6 bits on the System Register (SR, 8

bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put
in Stand-by (EN bit LOW), the power blocks are disabled.
The LNBEH21 is compliant both with the DiSEqC

2.0 specification and with the 13/18V Control Word

Communication Mode. The communication mode is selected by the "OM" I

bit and, depending on the

OM bit status, the TEN/VSEL pin function (see block diagram) is switched to control the 13/18V output
voltage level or to enable the internal 22KHz tone generator when in DiSEqC mode. (refer to
Communication Mode section for details).
When the regulator blocks are active (EN bit = 1) and in DiSEqC mode (OM=0), the LNB output voltage
can also be logic controlled to select 13V or 19.5V by mean of the V

bit. The control of the V

bit on

the V

voltage level depends on the OM bit status in order to allow the 13/18V Control Word

Communication (see Communication Mode section). Additionally, it is possible to increment by 1V (Typ.)
the selected output voltage value to compensate the excess voltage drop along the coaxial cable using
the LLC SR bit (LLC=1).
In order to improve design flexibility and to allow implementation of newcoming LNB remote control
standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor
must be used to couple the modulating signal source to the EXTM pin. Also in this case, the V

TX output

must be set ON during the tone transmission by setting the TTX bit High. When the external modulation
is not used, the relevant pin can be left open.
The current limitation block is SOA type and it is possible to select two current limit thresholds, by the
dedicated ISEL pin. The higher threshold is in the range of 750mA to 1A if the ISEL is left floating or
connected a voltage >3.3V. The lower threshold is in the range of 450mA to 700mA when the ISEL pin is
connected to ground. When the output port is shorted to ground, the SOA current limitation block limits the
short circuit current (I

) at typically 300mA, to reduce the power dissipation. Moreover, it is possible to

set the Short Circuit Current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I

C SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection

circuit works dynamically, as soon as an overload is detected, the output is shut-down for a time T

OFF

typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has
elapsed, the output is resumed for a time T

=1/10T

OFF

(typ.). At the end of Ton, if the overload is still

detected, the protection circuit will cycle again through T

OFF

and T

. At the end of a full T

in which no

overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical T

OFF

time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions.
However, there could be some cases in which an highly capacitive load on the output may cause a difficult
start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in
static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of
time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns
LOW when the overload condition is cleared.
This IC is also protected against overheating: when the junction temperature exceeds 150癈 (typ.), the
step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal
operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135癈 (typ.).

(*): External components are needed to comply to bi-directional DiSEqC

bus hardware requirements. Full compliance of the whole appli-

cation with DiSEqC

specifications is not implied by the use of this IC.

C BUS INTERFACE

Data transmission from main 礟 to the LNBEH21 and vice versa takes place through the 2 wires I

C bus

interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
externally connected).

LNBEH21

6/22

DATA VALIDITY
As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

START AND STOP CONDITIONS
As shown in fig. 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must
be sent before each START condition.

BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.

ACKNOWLEDGE
The master (礟) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
6). The peripheral (LNBEH21) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBEH21 won't generate the
acknowledge if the V

supply is below the Undervoltage Lockout threshold (6.7V typ.)

TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the LNBEH21, the 礟 can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.

Figure 4: Data Validity On The I

C Bus

Figure 5: Timing Diagram On I

C Bus

LNBEH21

7/22

Figure 6: Acknowledge On I

C Bus

LNBEH21 SOFTWARE DESCRIPTION

INTERFACE PROTOCOL
The interface protocol comprises:
- A start condition (S)
- A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)

ACK= Acknowledge; S = Start; P = Stop; R/W = Read/Write

SYSTEM REGISTER (SR, 1 BYTE)

R,W = read and write bit; R = Read-only bit
All bits reset to 0 at Power-On

TRANSMITTED DATA (I

C BUS WRITE MODE)

When the R/W bit in the chip address is set to 0, the main 礟 can write on the System Register (SR) of the
LNBEH21 via I

C bus. Only 6 bits out of the 8 available can be written by the 礟, since the remaining 2 are

left to the diagnostic flags, and are read-only.

CHIP ADDRESS

DATA

MSB

LSB

MSB

LSB

R/W ACK

ACK

MSB

LSB

R, W

PCL

TTX

LLC

VOM

OTF

OLF

LNBEH21

8/22

RECEIVED DATA (I

C bus READ MODE)

The LNBEH21 can provide to the Master a copy of the SYSTEM REGISTER information via I

C bus in

read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the
following master generated clocks bits, the LNBEH21 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBEH21;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the 礟, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBEH21

Values are typical unless otherwise specified

POWER-ON I

C INTERFACE RESET

The I

C interface built in the LNBEH21 is automatically reset at power-on. As long as the V

stays below

the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I

C command and

the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
V

rises above 7.3V typ, the I

C interface becomes operative and the SR can be configured by the main

礟. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.

ADDRESS PIN
Connecting this pin to GND the Chip I

C interface address is 0001000, but, it is possible to choice among

4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 11).

COMMUNICATION MODE SELECTION

C OM bit (Operating Mode selection bit)

The LNBEH21 can work either in DiSEqC

mode or in 13/18V Control Word mode; the selection of the

communication mode is achieved through the dedicated I

C OM bit that must be respectively set to LOW

or to HIGH. Depending on the communication mode selection (OM bit state) the I

C VOM bit and the TEN/

VSEL pin (#14) operation are switched between two different functions:

VOM bit and TEN/VSEL pin functions with OM=0 (DiSEqC

mode).

- The TEN/VSEL pin controls the 22KHz bursting code, by enabling the internal 22KHz tone generator, to
allow immediate DiSEqC

data encoding.

- In DiSEqC

mode, the VOM I

C bit controls simultaneously the post-regulator output voltage (V

OUT

)

and the DC/DC converter output voltage (V

). The VOM bit function is to select the LNB output voltage

to 13.25V or 19.5V respectively if VOM=0 or VOM=1 (14.25V or 20.5V if LLC=1) and V

is set to

OUT

+2.2V typ., according to DiSEqC section in the Truth Table on page 11;

PCL

TTX

LLC

VOM

OTF

OLF

Function

These bits are read exactly the same as

they were left after last write operation

<135癈, normal operation

>150癈, power block disabled

OUT

OMAX

, normal operation

OUT

OMAX

, overload protection triggered

LNBEH21

9/22

VOM bit and TEN/VSEL pin functions with OM=1 (13/18V Control Word mode).
- When OM=1, the TEN/VSEL controls the 13/18V output voltage level. The usage of the TEN/VSEL
pin in combination with the VOM bit allows the 13/18V Control Word Communication (see block diagram
on page 1). The TEN/VSEL is a TTL control logic pin.
- in 13/18V Control Word Communication mode, the VOM bit does not control the LNB output voltage but
only forces the DC/DC Converter output voltage (V

) in a steady state (V

=21.7V typ. if LLC=0 and

=22.7V typ. if LLC=1). When OM=VOM=1, the LNB output voltage is controlled only by the TEN/VSEL

pin.

COMMUNICATION MODE IMPLEMENTATION

DiSEqC

2.0 and 1.x mode, OM=0

When OM=0, the LNBEH21 is suitable both for DiSEqC 2.0 and for unidirectional DiSEqC 1.x
applications.
The bi-directional DiSEqC 2.0 protocol implementation is allowed by an easy PWK modulation/
demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBEH21 and the main
礟, using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is
made through two dedicated pins, TEN/VSEL (when OM=0) and DSQOUT, in order to maintain the timing
relationships between the PWK data and the PWK modulation as accurate as possible. These two pins
should be directly connected to two I/O pins of the 礟, thus leaving to the resident firmware the task of
encoding and decoding the PWK data in accordance to the DiSEqC protocol. The fully bi-directional
DiSEqC

2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin (DETIN) must be

AC coupled to the DiSEqC TM bus and the extracted PWK data are available on the DSQOUT pin biased
with a pull-up resistor to a fixed voltage (see Fig. 7 and 8).
Full compliance of the system to the specification is not implied by the bare use of the LNBEH21; the
system designer should also take in consideration that, to comply to the bi-directional DiSEqC TM 2.0 bus
hardware requirements, an output R-L filter is needed. In order to help the system designer to avoid any
distortion during the 22KHz tone transmission, due to the output R-L impedance, the LNBEH21 is
provided with two output pins: the V

TX, to be used during the 22KHz tone transmission; and the V

RX,

to be used when the tone is received (see DiSEqC 2.0 typical application circuit). This allows the 22KHz
tone to pass without any losses due to the R-L filter.
During the 22KHz transmission, activated by TEN/VSEL pin, the V

TX pin must be preventively activated

by the TTX I

C bit, so that, both the power supply and the 22KHz tone, are provided by mean of V

output. As soon as the tone transmission is expired, the V

TX must can set to OFF by setting the TTX I

bit to zero, and the power supply is provided to the LNB by the V

RX pin through the R-L filter.

Unidirectional DiSEqC 1.x and non-DiSEqC systems normally don't need the output R-L termination, and
the V

TX pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x typical

application circuit). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left
connected to ground; both the 22KHz tone and the power supply, are provided by the V

TX by setting

always TTX=1.
When In DiSEqC mode, the Output Voltage level (13.1V,14.1V,19.5V,20.5V) is selected only by the VOM
and LLC I

C bits combinations (refer to DiSEqC section in the Complete Truth Table on page 10 for

detailed logic combination and corresponding function description).

LNBEH21

10/22

Figure 7: DETIN/DSQOUT Circuit

Figure 8: DETIN/DSQOUT Waveform

13/18V Control Word mode, OM=1

When OM=1 the VOM is used to force the DC/DC Converter output voltage (V

) in a steady state and to

control the TEN/VSEL pin function. According to the VOM selection TEN/VSEL will absolve two different
functions:
1)VOM=0 - TEN/VSEL pin controls both the post regulator output voltage (V

OUT

) and the DC/DC

Converter output voltage (V

2)VOM=1 - TEN/VSEL pin controls only the post regulator output voltage while the DC/DC Converter
output voltage is forced in a steady state, at the high level, 22.7V typ. with LLC=1 and 21.7V typ. if LLC=0.
During normal operation, when no 13/18V control word is transmitted, the device must work with VOM=0
and TEN/VSEL pin is used to select the odd or even numbered transponder setting up the post regulator
output voltage in a steady state (13.25 or 19.5V); the V

voltage is selected by the IC according to the

OUT

value in order to minimize the power dissipation.

Before the beginning of the 13/18V Control Word Communication, it is mandatory to set VOM at HIGH
level forcing the V

at 21.7V typ.; after a certain setup time the 礟 can start to send the 13/18V pulses

command to the TEN/VSEL pin. During the 13/18V pulses, the V

OUT

rise and fall time between 13.25V

and 19.5V of are fully controlled by the internal voltage reference and they are maintained on a typical
value of 575祍, this time is guaranteed with a maximum output capacitance of 330nF and a load current
in the range of 6 to 450mA. As soon as the communication has expired VOM bit must be set LOW to avoid
any additional power dissipation (See Thermal Design Note). Refer to 13/18V Control Word section in the
complete truth table on page 11 for detailed logic combination and corresponding function description.

Tone

Detector

DSQOUT

DETIN

C6
100nF

to DiSEqC bus

(LNB)

VDD
(5V)

PWK data out

R1
2.5K

LNBEH21

CH1=22KHz Tone to DETIN, CH2=PWK data at DSQOUT

LNBEH21

11/22

DiSEqC COMMUNICATION TRUTH TABLE (TEN/VSEL pin controls the internal 22KHz Tone)

13/18V CONTROL WORD COMMUNICATION TRUTH TABLE (TEN/VSEL pin function depends on
VOM bit state)

GENERAL FEATURES TRUTH TABLE

X = don't care; values are typical unless otherwise specified.

PCL

TTX

LLC

VOM

OTF

OLF

Function

= 13.25 V and V

= 15.45 V

TEN/VSEL = HIGH 22KHz Enabled
TEN/VSEL = LOW 22KHz Disabled

= 19.5V and V

= 21.7 V

TEN/VSEL = HIGH 22KHz Enabled
TEN/VSEL = LOW 22KHz Disabled

= 14.25 V and V

= 16.45 V

TEN/VSEL = HIGH 22KHz Enabled
TEN/VSEL = LOW 22KHz Disabled

= 20.5 V and V

= 22.7 V

TEN/VSEL = HIGH 22KHz Enabled
TEN/VSEL = LOW 22KHz Disabled

PCL

TTX

LLC

VOM

OTF

OLF

Function

TEN/VSEL pin controls both the LNB output voltage and
the DC/DC Converter Voltage (V

)

TEN/VSEL = LOW, V

= 13.25 V and V

= 15.45 V

TEN/VSEL = HIGH, V

= 19.5V and V

= 21.7 V

TEN/VSEL pin controls only the LNB output voltage and the
DC/DC Converter output is forced always at 21.7 V
TEN/VSEL = LOW, V

= 13.25 V and V

= 21.7 V

TEN/VSEL = HIGH, V

= 19.5V and V

= 21.7 V

TEN/VSEL pin controls both the LNB output voltage and
the DC/DC Converter Voltage (V

)

TEN/VSEL = LOW, V

= 14.25 V and V

= 16.45 V

TEN/VSEL = HIGH, V

= 20.5V and V

= 22.7 V

TEN/VSEL pin used to set only the LNB output voltage.
DC/DC Converter output voltage forced always at 22.7 V
TEN/VSEL = LOW, V

= 14.25 V and V

= 22.7 V

TEN/VSEL = HIGH, V

= 20.5V and V

= 22.7 V

PCL

TTX

LLC

VOM

OTF

OLF

Function

When TTX = 0 the device is set in receiving mode, the TX
output is partially OFF the V

RX pin is ON:

TX = OFF, V

RX = ON

When TTX = 1 the device is set in receiving mode, the RX
output is partially OFF the V

TX pin is ON:

TX = ON, V

RX = OFF

Pulsed (dynamic) current limiting is selected

Static current limiting is selected

Power blocks disabled

LNBEH21

12/22

Table 5: Electrical Characteristics T

= 0 to 85癈, EN=1, LLC=PCL=OM=VOM=0, 22KHz Tone

Disabled, TTX=0/1, ISEL=High, V

=12V, I

=50mA, unless otherwise specified. See software description

section for I

C access to the system register.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltage

= 20.5V, I

= 750 mA Tone enabled

Supply Current

= 20.5V, Tone Enabled,

NO LOAD

EN=1

EN=0

3.5

Output Voltage

OM=0, VOM=1
(or OM=1, VOM=0),
I

=750mA, TEN/VSEL=High

LLC=0

18.7

19.5

20.3

LLC=1

20.5

Output Voltage

OM=0, VOM=1
(or OM=1, VOM=0),
I

=750 mA, TEN/VSEL=Low

LLC=0

12.75

13.25

13.75

LLC=1

14.25

Line Regulation

= 8 to 15V,

OM=0, VOM=0

= 8 to 15V,

OM=0, VOM=1

Load Regulation

OM=0, VOM=0/1, I

= 50 to 750mA

200

13/18V

- t

13/18V Rise and Fall
transition Time (to be
measured at the 90% and
10% voltage range)

OM=VOM=1, TEN/VSEL from low to high,
I

= 6 to 450 mA, C

= 10 to 330 nF

575

�

MAX

Output Current Limiting

ISEL

3.3V or Floating

750

1000

ISEL = GND

450

700

Output Short Circuit Current

300

OFF

Dynamic Overload
protection OFF Time

PCL=0

Output Shorted

900

Dynamic Overload
protection ON Time

PCL=0

Output Shorted

OFF

/10

TONE

Tone Frequency

OM=0, TEN/VSEL=High

KHz

TONE

Tone Amplitude

OM=0, TEN/VSEL=High

0.55

0.72

0.9

TONE

Tone Duty Cycle

OM=0, TEN/VSEL=High

, t

Tone Rise and Fall Time

OM=0, TEN/VSEL=High

�

EXTM

External Modulation Gain

OUT

EXTM

f = 10Hz to 50KHz

EXTM

External Input Voltage

AC Coupling

400

EXTM

External Modulation
Impedance

f = 10Hz to 50KHz

260

DC/DC Converter Switching
Frequency

220

kHz

DETIN

Tone Detector Frequency
Capture Range

0.4Vpp sinewave

kHz

DETIN

Tone Detector Input
Amplitude

=22kHz sinewave

0.2

1.5

DETIN

Tone Detector Input
Impedance

150

DSQOUT Pin Logic LOW

Tone present

=2mA

0.3

0.5

DSQOUT Pin Leakage
Current

Tone absent

= 6V

�

TEN/VSEL Input Pin Logic
LOW

0.8

TEN/VSEL Input Pin Logic
HIGH

TEN/VSEL Pin Input
Current

= 5V

�

LNBEH21

13/22

Table 6: Gate And Sense Electrical Characteristics (T

= 0 to 85癈, V

= 12V)

Table 7: I

C Electrical Characteristics (T

= 0 to 85癈, V

= 12V)

Table 8: Address Pin Characteristics (T

= 0 to 85癈, V

=12V)

OBK

Output Backward Current

EN=0

OBK

= 18V

-6

-15

SHDN

Temperature Shutdown
Threshold

150

癈

SHDN

Temperature Shutdown
Hysteresis

癈

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DSON-L

Gate LOW R

DSON

GATE

= -100mA

4.5

DSON-H

Gate HIGH R

DSON

GATE

= 100mA

4.5

SENSE

Current Limit Sense Voltage

200

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LOW Level Input Voltage

SDA, SCL

0.8

HIGH Level Input Voltage

SDA, SCL

Input Current

SDA, SCL, V

= 0.4 to 4.5V

-10

�

Low Level Output Voltage

SDA (open drain), I

= 6mA

0.6

MAX

Maximum Clock Frequency SCL

500

KHz

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

ADDR-1

"0001000" Addr Pin Voltage

0.7

ADDR-2

"0001001" Addr Pin Voltage

1.3

1.7

ADDR-3

"0001010" Addr Pin Voltage

2.3

2.7

ADDR-4

"0001011" Addr Pin Voltage

3.3

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LNBEH21

14/22

THERMAL DESIGN NOTES

During normal operation, this device dissipates some power. The power dissipation depends on the
selected communication mode (DiSEqC or 13/18 control word communication).
When the device is used in DiSEqC mode, at maximum rated output current (750mA), the voltage drop on
the linear regulator lead to a total dissipated power that is about 1.65W.
If the control word communication mode is selected, at maximum rated current of 450mA, the total power
dissipated is about 1W. By the way, during the 13/18V pulses code transmission (OM=VOM=1) the
average power dissipation is higher than 1W because, in this case, before to start sending the 13/18V
pulses code, the V

voltage must be forced in steady state at 21.7V by VOM=1, (22.7V if LLC=1) in order

to ensure the proper code transition rise and fall timing while the V

OUT

voltage is continuously switched

between 13V and 18V; this means that, in the 13V half period the peak of power dissipation is about 3.8W
typ. (@ Iout=450mA max.). Obviously this is the peak power dissipation as the average value during the
code transmission has to be calculated taking into account the 0/1 bits combination.
The heat generated requires a suitable heatsink to keep the junction temperature below the
overtemperature protection threshold. Assuming a 45癈 temperature inside the Set-Top-Box case and a
max continuos power dissipation of 1.65W, the total R

thj-amb

has to be less than 48癈/W.

While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the pcb ground layer to dissipate the heat coming from the IC body by mean the ground
exposed pad present on the bottom side of the PSO-20 package.
Given for the PSO-20 an R

thj-case

equal to 2癈/W, a maximum of 46癈/W are left to the PCB heatsink.

This figure is achieved if a minimum of 6.5cm

copper area is placed just below the IC body. This area can

be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the
opposite side where the IC is placed. In figure 9, is shown a suggested layout for the PSO-20 package
with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are
thermally connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves
an R

thc-a

of about 32癈/W.

Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground
exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to
design a dissipating area having a shape as square as possible and not interrupted by other copper
traces.

Figure 9: PowerSO-20 Suggested Pcb Heatsink Layout

LNBEH21

22/22

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.

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协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: LNBEH21

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: LNBEH21

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: LNBEH21