1/18

April 2004

ALL THE FEATURES ARE THE SAME FOR
BOTH SECTION

COMPLETE AND INDEPENDENT
INTERFACE BETWEEN LNBs AND
RELEVANT I

BUS

BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION AND
HIGH EFFICIENCY (Typ. 93% @ 500mA)

LNB OUTPUT CURRENT GUARANTEED UP
TO 500mA

BOTH COMPLIANT WITH EUTELSAT AND
DIRECTV OUTPUT VOLTAGE
SPECIFICATION

ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED
STANDARDS

FAST OSCILLATOR START-UP FACILITATES
DiSEqC

ENCODING

BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqC

2.0

SEMI-LOWDROP POST REGULATOR AND
HIGH EFFICIENCY STEP-UP PWM FOR
LOW POWER LOSS: Typ. 0.56W @ 125mA

TWO OUTPUT PINS SUITABLE TO BYPASS
THE OUTPUT R-L FILTER AND AVOID ANY
TONE DISTORSION (R-L FILTER AS PER
DiSEqC 2.0 SPECs, see application circuit on
pag. 4)

OVERLOAD AND OVER-TEMPERATURE
INTERNAL PROTECTIONS

OVERLOAD AND OVER-TEMPERATURE I

DIAGNOSTIC BITs

LNB SHORT CIRCUIT SOA PROTECTION
WITH I

C DIAGNOSTIC BIT

+/- 4KV ESD TOLERANT ON INPUT/
OUTPUT POWER PINS

DESCRIPTION
Intended for analog and digital DUAL Satellite
STB

receivers/SatTV,

sets/PC

cards,

the

LNBH221 is a voltage regulator and interface IC,
assembled

POWER

SO-36,

specifically

designed to provide the power 13/18V, and the
22KHz tone signalling for two independent LNB
down converters or to a multiswitch box that could
be independently powered and set. In this applica-
tion field, it offers a complete solution with ex-

tremely low component count, low power dissipa-
tion together with simple design and I

stan-

dard interfacing.

LNBH221

DUAL LNB SUPPLY AND CONTROL IC

WITH STEP-UP CONVERTER AND I

C INTERFACE

This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

PowerSO-36

PRELIMINARY DATA

BLOCK DIAGRAM

LNBH221- section A

LNBH221- section B

DSQIN

Vup

VoRX

SDA

SCL

Vcc

DSQOUT

VoTX

DETIN

Byp

Gate

Sense

EXTM

ADDR

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

DSQIN

Vup

VoRX

SDA

SCL

Vcc

DSQOUT

VoTX

DETIN

Byp

Gate

Sense

EXTM

ADDR

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

LNBH221- section A

LNBH221- section B

DSQIN

Vup

VoRX

SDA

SCL

Vcc

DSQOUT

VoTX

DETIN

Byp

Gate

Sense

EXTM

ADDR

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

DSQIN

Vup

VoRX

SDA

SCL

Vcc

DSQOUT

VoTX

DETIN

Byp

Gate

Sense

EXTM

ADDR

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

Enable

Preregul.+
U.V.lockout

+P.ON res.

V Select

Linear Post-reg

+Modulator

+Protections

Diagn.

I睠

Tone

Detector

22KHz
Oscill.

TEN

Step-up
Controller

LNBH221

3/18

TABLE A: PIN CONFIGURATIONS

SYMBOL

NAME

FUNCTION

PIN NUMBER

SECT:

Supply Input

8V to 15V supply. A 220礔 bypass capacitor to GND with a
470nF (ceramic) in parallel is recommended.

GATE

External Switch Gate

External MOS switch Gate connection of the step-up
converter.

SENSE

Current Sense (Input)

Current Sense comparator input. Connected to current
sensing resistor.

Step-up Voltage

Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a
minimum dropout across the linear pass transistor.

Output Port during
22KHz Tone RX

RX Output to the LNB in DiSEqC 2.0 application. See truth
table for voltage selections and description on page 5.

SDA

Serial Data

Bidirectional data from/to I

C bus.

SCL

Serial Clock

Clock from I

C bus.

DSQIN

DiSEqC Input

When the TEN bit of the System Register is LOW, this pin
will accept the DiSEqC code from the main

�

controller.

Each section of the LNBH221 will use this code to
modulate the internally generated 22kHz carrier. Set to
GND this pin if not used.

DETIN

Detector In

22kHz Tone Detector Input. Must be AC coupled to the
DiSEqC bus.

DSQOUT DiSEqC Output

Open drain output of the Tone Detector to the main

�

controller for DiSEqC data decoding. It is LOW when

tone is detected on the DETIN.

EXTM

External Modulation

External Modulation Input. Needs DC decoupling to the
AC source. If not used, can be left open.

GND

Ground

Circuit Ground. It is internally connected to the die frame
for heat dissipation.

1, 14, 18,

19, 32, 36

1, 14, 18,

19, 32, 36

BYP

Bypass Capacitor pin

Needed for internal pre regulator filtering.

Output Port during
22KHz Tone TX

Output of the linear post regulator/modulator to the LNB.
See truth table for voltage selections.

GND

Ground

To be connected to ground.

ADDR

Address Setting

Four I

C bus addresses available by setting the Address

Pin level voltage.

LNBH221

4/18

TYPICAL APPLICATION CIRCUITS FOR EACH SECTION : A and B

APPLICATION CIRCUIT FOR DiSEqC 1.x AND OUTPUT CURRENT UP TO 500mA

APPLICATION CIRCUIT FOR Bi-directional DiSEqC 2.0 AND OUTPUT CURRENT UP TO 500mA

C8, D3 and D4 are needed to protect the output pins from any negative voltage spikes during high speed voltage transitions.
(*): R-L filter to be used according to EUTELSAT recommendation to implement the DiSEqC

2.0, (see DiSEqC

implementation on

page 8). If bidirectional DiSEqC

2.0 is not implemented it can be removed both with C8 and D4.

(**) Do not leave these pins floating if not used.
(***) To be soldered as close as possible to relative pins.

LNBH221

Vup

Gate

Vin

12V

L1=22礖

Sense

Vcc

C5
10nF

oTX

SDA

SCL

DSQIN

Address

C5
470nF

GND

0<V

ADDR

BYP

Rsc
0.1

C3
470nF

Ceramic

D1 1N4001

C1
220礔

C4
470nF
Ceramic

D2
BAT43

IC1

STN4NF03L

IC2

C9
220礔

220礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

EXTM

DSQOUT

(**) DETIN

VoRX

to LNB

Byp

Tone Enable

Set TTX=1

Section A and B

LNBH221

Vup

Gate

Vin

12V

L1=22礖

Sense

Vcc

C5
10nF

oTX

SDA

SCL

DSQIN

Address

C5
470nF

GND

0<V

ADDR

BYP

Rsc
0.1

C3
470nF

Ceramic

D1 1N4001

C1
220礔

C4
470nF
Ceramic

D2
BAT43

IC1

STN4NF03L

IC2

STN4NF03L

IC2

C9
220礔

220礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

EXTM

DSQOUT

(**) DETIN

VoRX

to LNB

Byp

Tone Enable

Set TTX=1

Section A and B

22KHz Tone Enable

270礖

15 ohm

(*) see note

LNBH221

Vup

Gate

Vin

12V

L1=22礖

Sense

Vcc

VoRX

VoTX

(**) DETIN

C7(***)
100nF

to LNB

SDA

SCL

DSQOUT

DSQIN (**)

ADDRESS

Byp

C5
470nF

GND

0<V

ADDR

BYP

EXTM

C6
10nF

Rsc
0.1

C3(***)
470nF
Ceramic

D2 1N4001

C1
220礔

C4(***)
470nF
Ceramic

D3(***)
BAT43

IC1

D4(***)
BAT43

C8(***)
100nF

C9
220礔

220礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

Section A and B

STN4NF03L

IC2

22KHz Tone Enable

270礖

15 ohm

(*) see note

LNBH221

Vup

Gate

Vin

12V

L1=22礖

Sense

Vcc

VoRX

VoTX

(**) DETIN

C7(***)
100nF

to LNB

SDA

SCL

DSQOUT

DSQIN (**)

ADDRESS

Byp

C5
470nF

GND

0<V

ADDR

BYP

0<V

ADDR

BYP

EXTM

C6
10nF

Rsc
0.1

C3(***)
470nF
Ceramic

D2 1N4001

C1
220礔

C4(***)
470nF
Ceramic

D3(***)
BAT43

IC1

D4(***)
BAT43

C8(***)
100nF

C9
220礔

220礔

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

Axial Ferrite Bead Filter

suggested part number:

MURATA BL01RN1-A62
Panasonic EXCELS A35

Section A and B

STN4NF03L

IC2

STN4NF03L

IC2

LNBH221

5/18

APPLICATION INFORMATION

Basically, the LNBH221 includes two circuits that are completely independent. Each circuit can be
separately controlled and must have its independent external components. All the below specification
must be considered equal for each section.

This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V,
generates the voltages (V

) that let the linear post-regulator to work at a minimum dissipated power of

1W typ. @ 500mA load (the linear regulator drop voltage is internally kept at: V

-V

OUT

=2V typ.). An

UnderVoltage Lockout circuit will disable the whole circuit when the supplied V

drops below a fixed

threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the
standards, and can be controlled either by the I

interface or by a dedicated pin (DSQIN) that allows

immediate DiSEqC

data encoding (*). When the TEN (Tone ENable) I

C bit it is set to HIGH, a

continuous 22KHz tone is generated on the output regardless of the DSQIN pin logic status.
The TEN bit must be set LOW when the DSQIN pin is used for DiSEqC

encoding. The fully

bi-directional DiSEqC

2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin

(DETIN) must be AC coupled to the DiSEqC

bus, and the extracted PWK data are available on the

DSQOUT pin (*). To comply to the bi-directional DiSEqC

2.0 bus hardware requirements an output R-L

filter is needed. The LNBH221 is provided with two output pins: the V

TX to be used during the tone

transmission and the V

RX to be used when the tone is received. This allows the 22KHz Tone to pass

without any losses due to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 5). In
DiSeqC 2.0 applications during the 22KHz transmission activated by DSQIN pin (or TEN I

C bit), the

TX pin must be preventively set ON by the TTX I

C bit and, both the 13/18V power supply and the

22KHz tone, are provided by mean of V

TX output. As soon as the tone transmission is expired, the

TX must be set to OFF by setting the TTX I

C bit to zero and the 13/18V power supply is provided to

the LNB by the V

RX pin through the R-L filter. When the LNBH221 is used in DiSeqC 1.x applications the

R-L filter is not required (see DiSeqC 1.x application circuit on pag.5), the TTX I

C bit must be kept always

to HIGH so that, the V

TX output pin can provide both the 13/18V power supply and the 22KHz tone,

enabled by DSQIN pin or by TEN I

C bit. All the functions of this IC are controlled via I

bus by writing

6 bits on the System Register (SR, 8 bits). The same register can be read back, and two bits will report the
diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by
mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the
LNBH221 is provided with the LLC I

C bit that increase the selected voltage value (+1V when VSEL=0

and +1.5V when VSEL=1) to compensate for the excess voltage drop along the coaxial cable (LLC bit
HIGH). By mean of the LLC bit, the LNBH221 is also compliant to the American LNB power supply
standards that require the higher output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the
LLC=1 when VSEL=1. In order to improve design flexibility and to allow implementation of newcoming
LNB remote control standards, an analogic modulation input pin is available (EXTM).
An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM
pin. Also in this case, the V

TX output must be set ON during the tone transmission by setting the TTX bit

high. When external modulation is not used, the relevant pin can be left open. The current limitation block
is SOA type: if the output port is shorted to ground, the SOA current limitation block limits the short circuit
current (I

) at typically 300mA or 200mA respectively for V

OUT

13V or 18V, to reduce the power

dissipation. Moreover, it is possible to set the Short Circuit Current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I

C SR; when the PCL (Pulsed Current Limiting) bit is

set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the
output is shut-down for a time T

OFF

, typically 900ms. Simultaneously the OLF bit of the System Register

is set to HIGH. After this time has elapsed, the output is resumed for a time T

=1/10T

OFF

(typ.). At the

end of T

, if the overload is still detected, the protection circuit will cycle again through T

OFF

and T

. At

the end of a full T

in which no overload is detected, normal operation is resumed and the OLF bit is

reset to LOW. Typical T

OFF

time is 990ms and it is determined by an internal timer. This dynamic

operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent
power-on start up in most conditions. However, there could be some cases in which an highly capacitive
load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be
solved by initiating any power start-up in static mode (PCL=HIGH) and then switching to the dynamic
mode (PCL=LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the
current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also

LNBH221

6/18

protected against overheating: when the junction temperature exceeds 150癈 (typ.), the step-up
converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal operation is
resumed and the OTF bit is reset to LOW when the junction is cooled down to 140癈 (typ.).

(*): External components are needed to comply to bi-directional DiSEqC

bus hardware requirements. Full compliance of the whole

application to DiSEqC

specifications is not implied by the use of this IC.

NOTICE: DiSEqC is a trademark of EUTELSAT. I

C is a trademark of Philips Semiconductors.

C BUS INTERFACE (one for each section)

Data transmission from main 礟 to the LNBH221 and viceversa takes place through the 2 wires I

C bus

interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
externally connected).

DATA VALIDITY
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions
must be sent before each START condition.

BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

ACKNOWLEDGE
The master (礟) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (LNBH221) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH221 won't generate the
acknowledge if the V

supply is below the Undervoltage Lockout threshold (6.7V typ.).

TRANSMISSION WITHOUT ACKNOWLEDGEMENT
Avoiding to detect the acknowledge of the LNBH221, the 礟 can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.

Figure 1 : DATA VALIDITY ON THE I

C BUS

LNBH221

8/18

TRANSMITTED DATA (I

C BUS WRITE MODE)

When the R/W bit in the chip address is set to 0, the main 礟 can write on the System Register (SR) of the
LNBH221 via I

C bus. Only 6 bits out of the 8 available can be written by the 礟, since the remaining 2 are

left to the diagnostic flags, and are read-only.

X= don't care.
Values are typical unless otherwise specified

RECEIVED DATA (I

C bus READ MODE)

The LNBH221 can provide to the Master a copy of the SYSTEM REGISTER information via I

C bus in

read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1.
At the following master generated clocks bits, the LNBH221 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBH221;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the 礟, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBH221.

Values are typical unless otherwise specified

POWER-ON I

C INTERFACE RESET

The I

C interface built in the LNBH221 is automatically reset at power-on. As long as the V

stays below

the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I

C command and

the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
V

rises above 7.3V typ, the I

C interface becomes operative and the SR can be configured by the main

礟. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.

ADDRESS Pin
Connecting this pin to GND the Chip I

C interface address is 0001000, but, it is possible to choice among

4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10).

PCL

TTX

TEN

LLC

VSEL

OTF

OLF

Function

OUT

=13.25V, V

=15.25V

OUT

=18V, V

=20V

OUT

=14.25V, V

=16.25V

OUT

=19.5V, V

=21.5V

22KHz tone is controlled by DSQIN pin

22KHz tone is ON, DSQIN pin disabled

RX output is ON, output voltage controlled by VSEL and

LLC

TX output is ON, 22KHz controlled by DSQIN or TEN,

output voltage level controlled by VSEL and LLC

Pulsed (dynamic) current limiting is selected

Static current limiting is selected

Power blocks disabled

PCL

ISEL

TEN

LLC

VSEL

OTF

OLF

Function

These bits are read exactly the same as

they were left after last write operation

<140癈, normal operation

>150癈, power block disabled

OUT

OMAX

, normal operation

OUT

OMAX

, overload protection triggered

LNBH221

9/18

DiSEqC

IMPLEMENTATION

The LNBH221 helps the system designer to implement the bi-directional DiSEqC 2.0 protocol by allowing
an easy PWK modulation/demodulation of the 22KHz carrier. The PWK data are exchanged between the
LNBH221 and the main 礟 using logic levels that are compatible with both 3.3 and 5V microcontrollers.
This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the
timing relationships between the PWK data and the PWK modulation as accurate as possible. These two
pins should be directly connected to two I/O pins of the 礟, thus leaving to the resident firmware the task
of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the
system to the specification is thus not implied by the bare use of the LNBH221. The system designer
should also take in consideration the bus hardware requirements; that can be simply accomplished by the
R-L termination connected on the V

OUT

pins of the LNBH221, as shown in the Typical Application Circuit

on page 4. To avoid any losses due to the R-L impedance during the tone transmission, the LNBH221 has
dedicated output (V

TX) that, in a DiSEqC 2.0 application, is connected after the filter and must be

enabled by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.O operation
description on page 5).
Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the V

pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x application circuit on
pag.4). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left unconnected
and the Tone is provided by the V

TX.

ELECTRICAL CHARACTERISTICS OF EACH SECTION (A and B)
T

= 0 to 85癈, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, V

=12V, I

OUT

=50mA, unless

otherwise specified. See software description section for I

C access to the system register)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltage

OUT

= 500 mA TEN=VSEL=LLC=1

Supply Current

EN=TEN=VSEL=LLC=1, No Load

EN=0

3.5

OUT

Output Voltage

OUT

= 500 mA VSEL=1

LLC=0

17.3

18.7

LLC=1

18.7

19.5

20.3

OUT

Output Voltage

= 500 mA VSEL=0

LLC=0

12.75

13.25

13.75

LLC=1

13.75

14.25

14.75

OUT

Line Regulation

=8 to 15V

VSEL=0

VSEL=1

OUT

Load Regulation

VSEL = 0 or 1 I

OUT

= 50 to 500mA

200

MAX

Output Current Limiting

500

750

Output Short Circuit Current VSEL = 0

300

VSEL = 1

200

OFF

Dynamic Overload
protection OFF Time

PCL=0

Output Shorted

900

Dynamic Overload
protection ON Time

PCL=0

Output Shorted

OFF

/10

TONE

Tone Frequency

TEN=1

KHz

TONE

Tone Amplitude

TEN=1

0.55

0.72

0.9

Vpp

TONE

Tone Duty Cycle

TEN=1

, t

Tone Rise and Fall Time

TEN=1

�

EXTM

External Modulation Gain

OUT

EXTM

, f = 10Hz to 50KHz, TTX=1

EXTM

External Modulation Input
Voltage

AC Coupling, TTX=1

400

mVpp

EXTM

External Modulation
Impedance

f = 10Hz to 50KHz

260

DC/DC Converter Switch
Frequency

220

kHz

LNBH221

10/18

GATE AND SENSE ELECTRICAL CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

C ELECTRICAL CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

ADDRESS PIN CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

DETIN

Tone Detector Frequency
Capture Range

0.4Vpp sinewave

kHz

DETIN

Tone Detector Input
Amplitude

=22kHz sinewave

0.2

1.5

Vpp

DETIN

Tone Detector Input
Impedance

150

DSQOUT Pin Logic LOW

Tone present

=2mA

0.3

0.5

DSQOUT Pin Leakage
Current

Tone absent

= 6V

�

DSQIN Input Pin Logic
LOW

0.8

DSQIN Input Pin Logic
HIGH

DSQIN Pin Input Current

= 5V

�

OBK

Output Backward Current

EN=0

OBK

= 18V

-6

-15

SHDN

Thermal Shutdown
Threshold

150

癈

SHDN

Thermal Shutdown
Hysteresis

癈

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DSON-L

Gate LOW R

DSON

GATE

=-100mA

4.5

DSON-H

Gate LOW R

DSON

GATE

=100mA

4.5

SENSE

Current Limit Sense Voltage

200

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LOW Level Input Voltage

SDA, SCL

0.8

HIGH Level Input Voltage

SDA, SCL

Input Current

SDA, SCL, V

= 0.4 to 4.5V

-10

�

Low Level Output Voltage

SDA (open drain), I

= 6mA

0.6

MAX

Maximum Clock Frequency SCL

500

KHz

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

ADDR-1

"0001000" Addr Pin Voltage

0.7

ADDR-2

"0001001" Addr Pin Voltage

1.3

1.7

ADDR-3

"0001010" Addr Pin Voltage

2.3

2.7

ADDR-4

"0001011" Addr Pin Voltage

3.3

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LNBH221

11/18

THERMAL DESIGN NOTES

During normal operation, the LNBH221 device dissipates some power. At rated output current of 500mA
on each section output, the voltage drop on both linear regulators lead to a total dissipated power that is
typically 2W. The heat generated requires a suitable heatsink to keep the junction temperature below the
over-temperature protection threshold. Assuming a 45癈 temperature inside the Set-Top-Box case, the
total R

thj-amb

has to be less than 40癈/W.

While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the GND layer to dissipate the heat coming from the IC body.

Given for the PSO-20 package an R

thj-c

equal to 2癈/W, a maximum of 38癈/W are left to the PCB

heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken
GND area even on the opposite side where the IC is placed. In figure 4, it is shown a suggested layout for
the PSO-20 package with a dual layer PCB, where the IC exposed pad connected to GND and the square
dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when
L=40mm, achieves an R

thc-a

of about 28癈/W.

Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground
exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to
design a dissipating area having a shape as square as possible and not interrupted by other copper
traces.

Figure 4 : PowerSO-36 SUGGESTED PCB HEATSINK LAYOUT

LNBH221

18/18

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: LNBH221

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: LNBH221