1/20

October 2002

COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS

BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION

ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR

SUITS WIDELY ACCEPTED STANDARDS

FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING

BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM

LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION

LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC

CABLE LENGTH DIGITAL COMPENSATION

INTERNAL OVER TEMPERATURE
PROTECTION

ESD RATING 4KV ON POWER
INPUT-OUTPUT PINS

DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBP21 is a
monolithic voltage regulator and interface IC,
assembled

SO-20

and

PowerSO-20,

specifically designed to provide the power and the
13/18V, 22KHz tone signalling to the LNB

LNBP21

LNBP SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I

C INTERFACE

Enable

I Select

Preregul.+

U.V.lockout

+P.ON res.

Feedback

Step-up

Controller

V Select

Linear Post-reg

+Modulator

+Protections

22KHz
Oscill.

Vup

LT1

OUT

SDA

SCL

DSQIN

Vcc

Diagnostics

I睠
interf.

Tone

Detector

DSQOUT

LT2

DETIN

LNBP21

Byp

Gate

Sense

EXTM

ADDR

SCHEMATIC DIAGRAM

SO-20

PowerSO-20

LNBP21

2/20

downconverter in the antenna or to the multiswitch
box. In this application field, it offers a complete
solution with extremely low component count, low
power dissipation together with simple design and
I

CTM standard interfac-ing.

This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit

will

disable the whole circuit when the supplied V

drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I

interface or by a

dedicated pin (DSQIN) that allows immediate
DiSEqC

data encoding (*). All the functions of

this IC are controlled via I

bus by writing 6

bits on the System Register (SR, 8 bits) . The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled

and the loop-through switch between

LT1 and LT2 pins is closed, thus leaving all LNB
powering and control

functions to the Master

Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typ.) the selected voltage
value to compensate for the excess voltage drop
along the coaxial cable (LLC bit HIGH). In order to
minimise the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless
of the DSQIN pin logic status. The TEN bit must
be set LOW when the DSQIN pin is used for
DiSEqC

encoding. The fully bi-directional

DiSEqC

interfacing is completed by the built-in

22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC

bus, and the

extracted

PWK

data

are

available

the

DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking

capaci-tor must be used to couple the modulating
signal source to the EXTM pin. When external
modulation is not used, the relevant pin can be left
open.
The current limitation block has two thresholds
that can be selected by the I

SEL

bit of the SR; the

lower threshold is between 400 and 550mA
(I

SEL

=HIGH),

while

the

higher

threshold

between 500 and 650mA (I

SEL

=LOW).

The current protection block is SOA type. This
limits the short circuit current (Isc) typically at
200mA with I

SEL

=HIGH and at 300mA with

SEL

=LOW when the output port is connected to

ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dy-namically by the PCL bit of the SR; when
the PCL (Pulsed Current Limiting) bit is set to
LOW, the overcurrent protection circuit works
dynamically: as soon as an overload is detected,
the output is shut-down for a time t

off

, typically

900ms. Simultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t

=1/

10t

off

(typ.). At the end of t

, if the overload is still

detected, the protection circuit will cycle again
through Toff and Ton. At the end of a full Ton in
which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
Ton+Toff time is 990ms and it is determined by an
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**) .
However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in

static mode (PCL=HIGH) and then

switching to the dynamic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
This IC is also protected against overheating:
when the junction temperature exceeds 150癈
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140癈 (typ.).

(*): External components are needed to comply to bi-directional DiSEqC

bus hardware require-ments. Full compliance of the whole appli-

cation to DiSEqC

specifications is not implied by the use of this IC.

(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must
be externally limited.

LNBP21

3/20

ORDERING CODES

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

THERMAL DATA

PIN CONFIGUARATION (top view)

TYPE

SO-20

(Tube)

SO-20

(Tape & Reel)

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

LNBP21

LNBP21D2

LNBP21D2-TR

LNBP21PD

LNBP21PD-TR

Symbol

Parameter

Value

Unit

DC Input Voltage

LT1

, V

LT2

DC Input Voltage

Output Current

Internally Limited

DC Output Pin Voltage

-0.3 to 22

Logic Input Voltage (SDA, SCL, DSQIN)

-0.3 to 7

DETIN

Detector Input Signal Amplitude

Logic High Output Voltage (DSQOUT)

Bypass Switch ON Current

900

Bypass Switch OFF Voltage

�20

GATE

Gate Current

�400

SENSE

Current Sense Voltage

-0.3 to 1

ADDRESS

Address Pin Voltage

-0.3 to 7

stg

Storage Temperature Range

-40 to +150

癈

Operating Junction Temperature Range

-40 to +125

癈

Symbol

Parameter

SO-20

PowerSO-20

Unit

thj-case

Thermal Resistance Junction-case

癈/W

PowerSO-20

SO-20

LNBP21

4/20

TABLE A: PIN CONFIGURATIONS

SYMBOL

NAME

FUNCTION

PIN NUMBER
vs PACKAGE

SO-20

PowerSO-20

Supply Input

8V to 15V supply. A 220礔 bypass capacitor to
GND with a 470nF (ceramic) in parallel is
recommended

GATE

Exrernal Switch Gate

External MOS switch Gate connection of the
step-up converter

SENSE

Current Sense Input

Current Sense comparator input. Connected to
current sensing resistor

Step-up Voltage

Input of the linear post-regulator. The voltage on this
pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor

OUT

Output Port

Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.

SDA

Serial Data

Bidirectional data from/to I

C bus.

SCL

Serial Clock

Clock from I

C bus.

DSQIN

DiSEqC Input

When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main

�

controller. The LNBP21 will use this code to

modulate the internally generated 22kHz carrier. Set
to GND thi pin if not used.

DETIN

Detector In

22kHz Tone Detector Input. Must be AC coupled to
the DiSEcQ bus.

DSQOUT DiSEqC Output

Open collector output of the tone Detector to the
main

�

controller for DiSEcQ data decoding. It is

LOW when tone is detected.

EXTM

Extrernal Modulator

External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.

GND

Ground

Circuit Ground. It is internally connected to the die
frame for heat dissipation.

5, 6, 15, 16

1, 10, 11, 20

BYP

Bypass Capacitor

Needed for internal preregulator filtering

LT1

Loop Through Switch

In standby mode the power switch between LT1
and LT2 is closed. Max allowed current is 900mA.
this pin can be left open if loopthrough function is
not needed.

LT2

Loop Through Switch

Same as above

ADDR

Address Setting

Four I

C bus addresses available by setting the

Address Pin level voltage

LNBP21

5/20

TYPICAL APPLICATION CIRCUIT

(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqC

2.x, not needed if bidirectional DiSEqC

2.x is

not implemented (see DiSEqC implementation note)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel Mos-Fet, needed for the DC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel Mos-Fet (STN4NF03L or similar)

C BUS INTERFACE

Data transmission from main 礟 to the LNBP21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).

DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.

START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.

BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.

ACKNOWLEDGE

The master (礟) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig.

3).

The

peripheral

(LNBP21)

that

acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBP21 won't gen-erate the acknowledge if
the Vcc supply is below the Undervoltage Lockout
threshold (6.7V typ.).

TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the
LNBP21, the 礟 can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.

This approach of course is less protected from
misworking and decreases the noise immunity.

270礖

15 ohm

see Note 2

LNBP21

Vup

Gate

Vin

12V

L1=22礖

Sense

C2
220礔

Vcc

LT1

Master STB

LT2

DETIN
(Note 1)

C8
10nF

to LNB

SDA

SCL

DSQOUT

DSQIN(Note 1)

ADDRESS

Byp

C5
470nF

GND

0<Vaddr<V

Byp

EXTM

C6
10nF

0.1

C3
470nF

Ceramic

D1 1N4001

C1
220礔

C4
470nF

Ceramic

D2
BAT43

C7
10nF

STS4DNFS30L

IC2

(Note 3)

IC1

(Note 4)

LNBP21

7/20

LNBP1 SOFTWARE DESCRIPTION

INTERFACE PROTOCOL

The interface protocol comprises:

- A start condition (S)

- A chip address byte = hex 10 / 11 (the LSB bit
determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)

ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write

SYSTEM REGISTER (SR, 1 BYTE)

R,W= read and write bit
R= Read-only bit
All bits reset to 0 at Power-On

TRANSMITTED DATA (I

C BUS WRITE MODE)

When the R/W bit in the chip address is set to 0,
the main 礟 can write on the System Register
(SR) of the LNBP21 via I

C bus. Only 6 bits out of

the 8 available can be written by the 礟, since the
re-maining 2 are left to the diagnostic flags, and
are read-only.

X= don't care.
Values are typical unless otherwise specified

RECEIVED DATA (I

C bus READ MODE)

The LNBP21 can provide to the Master a copy of
the SYSTEM REGISTER information via I2C bus
in read mode. The read mode is Master activated
by sending the chip address with R/W bit set to 1.
At the following master generated clocks bits, the

LNBP21 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way
the

transmission

another

byte

from

the

LNBP21;

CHIP ADDRESS

DATA

MSB

LSB

MSB

LSB

R/W ACK

ACK

MSB

LSB

R, W

PCL

ISEL

TEN

LLC

VSEL

OTF

OLF

PCL

ISEL

TEN

LLC

VSEL

OTF

OLF

Function

OUT

=13V, V

=16V Loopthrough switch open

OUT

=18V, V

=21V Loopthrough switch open

OUT

=14V, V

=17V Loopthrough switch open

OUT

=19V, V

=22V Loopthrough switch open

22KHz tone is controlled by DSQIN pin

22KHz tone is ON, DSQIN pin disabled

OUT(min)

=500mA, I

OUT(max)

=650mA I

=300mA

OUT(min)

=400mA, I

OUT(max)

=550mA I

=300mA

Pulsed (dynamic) current limiting is selected

Static current limiting is selected

Power blocks disabled, Loopthrough switch closed

LNBP21

8/20

- no acknowledge, stopping the read mode
communication.

While the whole register is read back by the 礟,
only the two read-only bits OLF and OTF convey
di-agnostic informations about the LNBP21.

Values are typical unless otherwise specified

POWER-ON I2C INTERFACE RESET
The

I2C

interface

built

the

LNBP21

automatically reset at power-on. As long as the
Vcc stays be-low the UnderVoltage Lockout
threshold (6.7V typ.), the interface will not respond
to any I2C com-mand and the System Register
(SR) is initialised to all zeroes, thus keeping the
power blocks disabled. Once the Vcc rises above
7.3V, the I2C interface becomes operative and the
SR can be configured by the main 礟. This is due
to About 500mV of hysteresis provided in the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.

DiSEqCTM IMPLEMENTATION
The LNBP21 helps the system designer to
implement the bi-directional (2.x) DiSEqC protocol
by

al-lowing

easy

PWK

modulation/

demodulation of the 22KHz carrier. The PWK data
are exchanged between the LNBP21 and the
main 礟 using logic levels that are compatible with
both 3.3 and 5V mi-crocontrollers. This data
exchange is made through two dedicated pins,
DSQIN and DSQOUT, in or-der to maintain the
timing relationships between the PWK data and
the PWK modulation as accurate as possible.
These two pins should be directly connected to
two I/O pins of the 礟, thus leaving to the resident
firmware the task of encoding and decoding the

PWK data in accordance to the DiSEqC pro-tocol.
Full compliance of the system to the specification
is thus not implied by the bare use of the LNBP21.

The

system

designer

should

also

take

consideration the bus hardware requirements,
that include the source impedance of the Master
Transmitter measured at 22KHz. To limit the
attenuation at car-rier frequency, this impedance
has to be 15ohm at 22KHz, dropping to zero ohm
at DC to allow the power flow towards the
peripherals. This can be simply accomplished by
the LR

termination put on the OUT pin of the

LNBP, as shown in the Typical Application Circuit
on page 5.

Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin can be directly connected to the LNB
supply port of the Tuner. There is also no need of
Tone Decoding, thus, it is recommended to
connect the DETIN and DSQOUT pins to ground
to avoid EMI.

ADDRESS PIN

Connecting this pin to GND the Chip I2C interface
address is 0001000, but, it is possible to choice
among 4 different addresses simply setting this
pin at 4 fixed voltage levels (see table on page
10).

ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (T

= 0 to 85癈, EN=1, LLC=0, TEN=0, ISEL=0,

PCL=0, DSQIN=0, V

=12V, I

OUT

=50mA, unless otherwise specified. See software description section

for I

C access to the system register)

PCL

ISEL

TEN

LLC

VSEL

OTF

OLF

Function

These bits are read exactly the same as

they were left after last write operation

<140癈, normal operation

>150癈, power block disabled, Loothrough switch open

OUT

OMAX

, normal operation

OUT

OMAX

, overload protection triggered

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltage

= 500 mA TEN=VSEL=LLC=1

LT1

LT1 Input Voltage

Supply Current

= 0mA TEN=VSEL=LLC=1

EN=1

EN=0

2.5

Output Voltage

= 500 mA VSEL=1

LLC=0

17.3

18.7

LLC=1

LNBP21

9/20

Output Voltage

= 500 mA VSEL=0

LLC=0

12.5

13.5

LLC=1

Line Regulation

IN1

=15 to 18V

VSEL=0

VSEL=1

Load Regulation

VSEL=0 or 1 I

OUT

= 50 to 500mA

200

MAX

Output Current Limiting

ISEL=1

400

550

ISEL=0

500

650

Output Short Circuit Current

ISEL=1

200

ISEL=0

300

OFF

Dynamic Overload
protection OFF Time

PCL=0

Output Shorted

900

Dynamic Overload
protection ON Time

PCL=0

Output Shorted

OFF

/10

TONE

Tone Frequency

TEN=1

KHz

TONE

Tone Amplitude

TEN=1

0.55

0.72

0.9

Vpp

TONE

Tone Duty Cycle

TEN=1

, t

Tone Rise and Fall Time

TEN=1

�

EXTM

External Modulation Gain

OUT

EXTM

f = 10Hz to 40KHz

EXTM

External Modulation Input
Voltage

AC Coupling

400

mVpp

EXTM

External Modulation
Impedance

f = 10Hz to 50KHz

260

Loopthrough Switch Voltage
Drop (lt1 to LT2)

EN=0,

=300mA,

=12 or 19V

0.35

0.6

DC/DC Converter Switch
Frequency

220

kHz

DETIN

Tone Detector Frequency
Capture Range

0.4Vpp sinewave

kHz

DETIN

Tone Detector Input
Amplitude

=22kHz sinewave

0.2

1.5

Vpp

DETIN

Tone Detector Input
Impedance

150

Overload Flag Pin Logic
LOW

Tone present

=2mA

0.3

0.5

Overload Flag Pin OFF
State Leakage Current

Tone absent

= 6V

�

DSQIN Input Pin Logic
LOW

0.8

DSQIN Input Pin Logic
HIGH

DSQIN Pins Input Current

= 5V

�

OBK

Output Backward Current

EN=0

OBK

= 18V

-4

-10

SHDN

Temperature Shutdown
Threshold

150

癈

SHDN

Temperature Shutdown
Hysteresis

癈

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LNBP21

10/20

GATE AND SENSE ELECTRICAL CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

C ELECTRICAL CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

ADDRESS PIN CHARACTERISTICS (T

= 0 to 85癈, V

=12V)

TEST CIRCUIT

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DSON-L

Gate LOW R

DSON

GATE

=-100mA

4.5

DSON-H

Gate LOW R

DSON

GATE

=100mA

4.5

SENSE

Current Limit Sense Voltage

200

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LOW Level Input Voltage

SDA, SCL

0.8

HIGH Level Input Voltage

SDA, SCL

Input Current

SDA, SCL, V

= 0.4 to 4.5v

-10

�

DSQIN Input Pin Logic
LOW

SDA (open drain), I

= 6mA

0.6

MAX

Maximum Clock Frequency SCL

500

KHz

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

ADDR-1

"0001000" Addr Pin Voltage

0.7

ADDR-2

"0001001" Addr Pin Voltage

1.3

1.7

ADDR-3

"0001010" Addr Pin Voltage

2.3

2.7

ADDR-4

"0001011" Addr Pin Voltage

3.3

Gate

Vup

LT1

OUT

Vcc

EXTM

DSQOUT

10nF

LT2

DETIN

10nF

Scope Probe

MI,

OBK

LNBP21

470nF

BYP

, I

OBK

Vin

OUT

Load

20礔

/ I

SDA

SCL

SDA

{

From I

Master

DSQIN

Pulse Gen.

EXTM,

DETIN

Sense

STN4NF03L

0.1

220礔

470nF

STPS2L30A

220礔

470nF

L1=22礖

ADDRESS

1N4001

10nF

LNBP21

16/20

Figure 34 :

Output Voltage Transient Response

from 13V to 18V

Figure 35 :

Output Voltage Transient Response

from 13V to 18V

TERMAL DESIGN NOTES

During normal operation, this device dissipates
some power. At maximum rated output current
(500mA), the voltage drop on the linear regulator
lead to a total dissipated power that is of about
1.7W. The heat generated requires a suitable
heatsink to keep the junction temperature below
the

overtemperature

protection

threshold.

Assuming

40癈

temperature

inside

the

Set-Top-Box case, the total Rthj-amb has to be
less than 50癈/W.

While this

can be easily

achieved using a

through-hole power package that can be attached
to a small heatsink or to the metallic frame of the
receiver, a surface mount power package must
rely on PCB solutions whose thermal efficiency is
often limited. The simplest solution is to use a
large, con-tinuous copper area of the GND layer to
dissipate the heat coming from the IC body.

The SO-20 package of this IC has 4 GND pins that
are

not

just

intended

for

electrical

GND

connec-tion, but also to provide a low thermal
resistance path between the silicon chip and the
PCB heatsink. Given an Rthj-c equal to 15癈/W,
a maximum of

35癈/W

are left to the PCB

heatsink. This figure is achieved if a minimum of
25cm2 copper area is placed just below the IC

body. This area can be the inner GND layer of a
multi-layer PCB, or, in a dual layer PCB, an
unbroken GND area even on the opposite side
where the IC is placed. In both cases, the thermal
path between the IC GND pins and the dissipating
copper area must exhibit a low thermal resistance.

In figure 4 , it is shown a suggested layout for the
SO-20 package with a dual layer PCB, where the
IC Ground pins and the square dissipating area
are thermally connected through 32 vias holes,
filled

solder.

This

arrangement,

when

L=50mm, achieves an Rthc-a of about 25癈/W.

Different

layouts

are

possible,

too.

Basic

principles, however, suggest to keep the IC and its
ground pins approximately in the middle of the
dissipating area; to provide as many vias as
possible; to de-sign a dissipating area having a
shape as square as possible and not interrupted
by other copper traces.

Due to presence of an exposed pad connected to
GND below the IC body, the PowerSO-20
package has a Rthj-c much lower than the SO-20,
only 2癈/W. As a result, much lower copper area
must be provided to dissipate the same power and
minimum of 12cm2 copper area is enough, see
figure 5.

=12V, I

=50mA, VSEL=from 0 to 1, EN=1

=12V, I

=50mA, VSEL=from 1 to 0, EN=1

LNBP21

20/20

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协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: LNBP21D2-TR

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: LNBP21D2-TR