1/19
November 2002
s
COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
s
BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
s
ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
s
SUITS WIDELY ACCEPTED STANDARDS
s
FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING
s
BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM
s
LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
s
LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
s
CABLE LENGTH DIGITAL COMPENSATION
s
INTERNAL OVER TEMPERATURE
PROTECTION
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBS21 is a
monolithic voltage regulator and interface IC,
assembled in PowerSO-20, specifically designed
to provide the power and the 13/18V, 22KHz tone
signalling to the LNB downconverter in the
antenna or to the multiswitch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I
2
C
TM
standard interfacing.
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
LNBS21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I
2
C INTERFACE
Enable
I Select
Preregul.+
U.V.lockout
+P.ON res.
Feedback
Step-up
Controller
V Select
Linear Post-reg
+Modulator
+Protections
22KHz
Oscill.
Vup
LT1
OUT
SDA
SCL
DSQIN
Vcc
Diagnostics
IC
interf.
Tone
Detector
DSQOUT
LT2
DETIN
LNBS21
Byp
Gate
Sense
EXTM
ADDR
SCHEMATIC DIAGRAM
PowerSO-20
LNBS21
2/19
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit
will
disable the whole circuit when the supplied V
CC
drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I
2
C
TM
interface or by a
dedicated pin (DSQIN) that allows immediate
DiSEqC
TM
data encoding (*). All the functions of
this IC are controlled via I
2
C
TM
bus by writing 6
bits on the System Register (SR, 8 bits) . The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled
and the loop-through switch between
LT1 and LT2 pins is closed, thus leaving all LNB
powering and control
functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typ.) the selected voltage
value to compensate for the excess voltage drop
along the coaxial cable (LLC bit HIGH). In order to
minimise the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless
of the DSQIN pin logic status. The TEN bit must
be set LOW when the DSQIN pin is used for
DiSEqC
TM
encoding. The fully bi-directional
DiSEqC
TM
interfacing is completed by the built-in
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC
TM
bus, and the
extracted
PWK
data
are
available
on
the
DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking
capaci-tor must be used to couple the modulating
signal source to the EXTM pin. When external
modulation is not used, the relevant pin can be left
open.
The current limitation block has two thresholds
that can be selected by the I
SEL
bit of the SR; the
lower threshold is between 650 and 900mA
(I
SEL
=HIGH),
while
the
higher
threshold
is
between 750 and 1000mA (I
SEL
=LOW).
The current protection block is SOA type. This
limits the short circuit current (Isc) typically at
300mA with I
SEL
=HIGH and at 400mA with
I
SEL
=LOW when the output port is connected to
ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dy-namically by the PCL bit of the SR; when
the PCL (Pulsed Current Limiting) bit is set to
LOW, the overcurrent protection circuit works
dynamically: as soon as an overload is detected,
the output is shut-down for a time t
off
, typically
900ms. Simultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
on
=1/
10t
off
(typ.). At the end of t
on
, if the overload is still
detected, the protection circuit will cycle again
through Toff and Ton. At the end of a full Ton in
which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
Ton+Toff time is 990ms and it is determined by an
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**) .
However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in
static mode (PCL=HIGH) and then
switching to the dynamic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
This IC is also protected against overheating:
when the junction temperature exceeds 150C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140C (typ.).
(*): External components are needed to comply to bi-directional DiSEqC
TM
bus hardware require-ments. Full compliance of the whole appli-
cation to DiSEqC
TM
specifications is not implied by the use of this IC.
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must
be externally limited.
LNBS21
3/19
ORDERING CODES
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
THERMAL DATA
PIN CONFIGUARATION (top view)
TYPE
PowerSO-20
(Tube)
PowerSO-20
(Tape & Reel)
LNBS21
LNBS21PD
LNBS21PD-TR
Symbol
Parameter
Value
Unit
V
CC
DC Input Voltage
16
V
V
UP
DC Input Voltage
25
V
V
LT1
, V
LT2
DC Input Voltage
20
V
I
O
Output Current
Internally Limited
mA
V
O
DC Output Pin Voltage
-0.3 to 22
V
V
I
Logic Input Voltage (SDA, SCL, DSQIN)
-0.3 to 7
V
V
DETIN
Detector Input Signal Amplitude
2
V
PP
V
OH
Logic High Output Voltage (DSQOUT)
7
V
I
LT
Bypass Switch ON Current
900
mA
V
LT
Bypass Switch OFF Voltage
20
V
I
GATE
Gate Current
400
mA
V
SENSE
Current Sense Voltage
-0.3 to 1
V
V
ADDRESS
Address Pin Voltage
-0.3 to 7
V
T
stg
Storage Temperature Range
-40 to +150
C
T
op
Operating Junction Temperature Range
-40 to +125
C
Symbol
Parameter
PowerSO-20
Unit
R
thj-case
Thermal Resistance Junction-case
2
C/W
PowerSO-20
LNBS21
4/19
TABLE A: PIN CONFIGURATIONS
SYMBOL
NAME
FUNCTION
PIN NUMBER
vs PACKAGE
V
CC
Supply Input
8V to 15V supply. A 220F bypass capacitor to
GND with a 470nF (ceramic) in parallel is
recommended
18
GATE
Exrernal Switch Gate
External MOS switch Gate connection of the
step-up converter
17
SENSE
Current Sense Input
Current Sense comparator input. Connected to
current sensing resistor
16
V
up
Step-up Voltage
Input of the linear post-regulator. The voltage on this
pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor
19
OUT
Output Port
Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.
2
SDA
Serial Data
Bidirectional data from/to I
2
C bus.
12
SCL
Serial Clock
Clock from I
2
C bus.
13
DSQIN
DiSEqC Input
When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main
controller. The LNBS21 will use this code to
modulate the internally generated 22kHz carrier. Set
to GND thi pin if not used.
14
DETIN
Detector In
22kHz Tone Detector Input. Must be AC coupled to
the DiSEcQ bus.
9
DSQOUT DiSEqC Output
Open collector output of the tone Detector to the
main
controller for DiSEcQ data decoding. It is
LOW when tone is detected.
15
EXTM
Extrernal Modulator
External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.
5
GND
Ground
Circuit Ground. It is internally connected to the die
frame for heat dissipation.
1, 10, 11, 20
BYP
Bypass Capacitor
Needed for internal preregulator filtering
8
LT1
Loop Through Switch
In standby mode the power switch between LT1
and LT2 is closed. Max allowed current is 900mA.
this pin can be left open if loopthrough function is
not needed.
4
LT2
Loop Through Switch
Same as above
3
ADDR
Address Setting
Four I
2
C bus addresses available by setting the
Address Pin level voltage
7
LNBS21
5/19
TYPICAL APPLICATION CIRCUIT
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqC
TM
2.0, not needed if bidirectional DiSEqC
TM
2.0 is
not implemented (see DiSEqC implementation note)
I
2
C BUS INTERFACE
Data transmission from main P to the LNBS21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig.
3).
The
peripheral
(LNBS21)
that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBS21 won't gen-erate the acknowledge if
the Vcc supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBS21, the P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
270H
15 ohm
(**) see note
LNBS21
Vup
Gate
Vin
12V
L1=22H
Sense
C2
220F
Vcc
LT1
Master STB
Vout
LT2
DETIN(*)
C8
10nF
to LNB
SDA
SCL
DSQOUT
DSQIN(*)
ADDRESS
Byp
C5
470nF
GND
0<Vaddr<V
Byp
EXTM
C6
10nF
R
sc
0.05
C3
470nF
Ceramic
D1 1N4001
C1
220F
C4
470nF
Ceramic
D2
BAT43
C7
10nF
MOSFET
STN4NF03L
Schottky
diode
STPS3L40S
or 1N5821
IC1
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