PRELIMINARY DATA
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev. 1
November 2005
1/26
1
M39P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory
128 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
Features summary
Multi-chip package
1die of 512 Mbit (32Mb x 16, Multiple Bank,
Multi-Level, Burst) Flash memory
1 die of 128 Mbit (4 Banks of 2Mb x16)
Low
Power Synchronous Dynamic RAM
Supply voltage
V
DDF
= V
CCP
= V
DDQ
= 1.7 to 1.95V
V
PPF
= 9V for fast program (12V tolerant)
Electronic signature
Manufacturer Code: 20h
Device Code: 8819
Package
ECOPACK (RoHS compliant)
Flash memory
Synchronous / asynchronous read
Synchronous Burst Read mode:
108MHz, 66MHz
Asynchronous Page Read mode
Random Access: 93ns
Programming time
4s typical Word program time using Buffer
Enhanced Factory Program command
Memory organization
Multiple Bank Memory Array: 64 Mbit
Banks
Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
program/erase in one Bank while read in
others
No delay between read and write
operations
Security
64-bit unique device number
2112-bit user programmable OTP Cells
100,000 program/erase cycles per block
Block locking
All Blocks locked at power-up
Any combination of Blocks can be locked
with zero latency
WP
F
for Block Lock-Down
Absolute Write Protection with V
PPF
= V
SS
Common Flash Interface (CFI)
LPSDRAM
128Mbit synchronous dynamic RAM
Organized as 4 Banks of 2 MWords, each
16 bits wide
Synchronous burst read and write
Fixed Burst Lengths: 1, 2, 4, 8 words or Full
Page
Burst Types: Sequential and Interleaved.
Maximum Clock Frequency: 104MHz
CAS Latency 2, 3
Automatic precharge
Low power features:
PASR (Partial Array Self Refresh),
Automatic TCSR (Temperature
Compensated Self Refresh)
Driver Strength (DS)
Deep Power-Down Mode
Auto Refresh and Self Refresh
TFBGA105 (ZAD)
9 x 11mm
FBGA
www.st.com
M39P0R9070E0
2/26
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Flash Memory Chip Enable Input (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Flash Memory Output Enable (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Flash Memory Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Flash Memory Write Protect Input (WP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Flash Memory Reset (RP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Deep Power-Down (DPD
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Flash Memory Latch Enable (L
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11
Flash Memory Clock (K
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
Flash Memory Wait (WAIT
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
LPSDRAM Chip Select (E
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
LPSDRAM Column Address Strobe (CAS
S
) . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
LPSDRAM Row Address Strobe (RAS
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16
LPSDRAM Write Enable (W
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.17
LPSDRAM Clock Input (K
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18
LPSDRAM Clock Enable (KE
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.19
LPSDRAM Lower/Upper Data Input/Output Mask (LDQM
S
/UDQM
S
) . . . . . 12
2.20
Flash Memory V
DDF
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21
LPSDRAM V
DDS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.22
V
DDQ
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.23
Flash Memory V
PPF
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 13
2.24
V
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M39P0R9070E0
3/26
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M39P0R9070E0
4/26
List of tables
Table 1.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2.
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4.
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5.
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6.
Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7.
Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8.
LPSDRAM DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9.
LPSDRAM DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10.
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data . . . . . . . . . . 23
Table 11.
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M39P0R9070E0
5/26
List of figures
Figure 1.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4.
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5.
AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6.
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 22
PDF 
ZIP