1/14
December 1999
M48T512Y
M48T512V
3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, and CRYSTAL
s
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
M48T512Y: 4.2V
V
PFD
4.5V
M48T512V: 2.7V
V
PFD
3.0V
s
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
s
10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE OF POWER
s
PIN and FUNCTION COMPATIBLE with
INDUSTRY STANDARD 512K X 8 SRAMS
s
SELF-CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
DESCRIPTION
The M48T512Y/V TIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock or-
ganized as 524,288 words by 8 bits. The special
DIP package provides a fully integrated battery
back-up memory and real time clock solution.
Figure 1. Logic Diagram
AI02262
19
A0-A18
DQ0-DQ7
VCC
M48T512Y
M48T512V
G
VSS
8
E
W
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
Write Enable Input
V
CC
Supply Voltage
V
SS
Ground
32
1
PMDIP32 (PM)
Module
M48T512Y, M48T512V
2/14
Figure 2. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A16
A18
VCC
AI02263
10
1
2
5
6
7
8
9
11
12
13
14
15
16
30
29
26
25
24
23
22
21
20
19
18
17
A12
A14
W
A17
3
4
28
27
32
31
M48T512Y
M48T512V
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
M48T512Y
0.3 to 7.0
V
M48T512V
0.3 to 4.6
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
The M48T512Y/V directly replaces industry stan-
dard 512Kb x 8 SRAMs. It also provides the non-
volatility of Flash without any requirement for spe-
cial write timing or limitations on the number of
writes that can be performed.
The 32 pin 600 mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package. Figure 3 illustrates
the static memory array and the quartz controlled
clock oscillator. The clock locations contain the
year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29
(leap year - compliant until the year 2100), 30, and
31 day months are made automatically. Byte
7FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. The seven
clock bytes (7FFFFh-7FFF9h) are not the actual
clock counters, they are memory locations consist-
ing of BiPORTTM read/write memory cells within
the static RAM array. The M48T512Y/V includes a
clock control circuit which updates the clock bytes
with current information once per second. The in-
formation can be accessed by the user in the
same manner as any other location in the static
memory array. The M48T512Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V
CC
is out of toler-
ance, the circuit write protects the TIMEKEEPER
register data and external SRAM, providing data
security in the midst of unpredictable system oper-
ation. As V
CC
falls, the control circuitry automati-
cally switches to the battery, maintaining data and
clock operation until valid power is restored.
READ MODE
The M48T512Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 19 Ad-
dress Inputs defines which one of the 524,288
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Ac-
3/14
M48T512Y, M48T512V
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
.
2. See Table 7 for details.
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
(2)
X
X
X
High Z
Battery Back-up Mode
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 3. AC Testing Load Circuit
AI01803C
CL = 100pF
CL includes JIG capacitance
650
DEVICE
UNDER
TEST
1.75V
cess Time (t
AVQV
) after the last address input sig-
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access Times (t
ELQV
) or Output
Enable Access Time (t
GLQV
). The state of the eight
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t
AVQV
, the
data lines will be driven to an indeterminate state
until t
AVQV
. If the Address Inputs are changed
while E and G remain active, output data will re-
main valid for Output Data Hold Time (t
AXQX
) but
will go indeterminate until the next Address Ac-
cess.
WRITE MODE
The M48T512Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of t
EHAX
from Chip Enable
or t
WHAX
from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
t
DVWH
prior to the end of write and remain valid for
t
WHDX
afterward. G should be kept high during
write cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
WLQZ
af-
ter W falls.
M48T512Y, M48T512V
4/14
DATA RETENTION MODE
With valid V
CC
applied, the M48T512Y/V operates
as a conventional BYTEWIDETM static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
V
CC
falls between V
PFD
(max), V
PFD
(min) win-
dow. All outputs become high impedance and all
inputs are treated as "don't care".
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below V
PFD
(min), the memory will be
in a write protected state, provided the V
CC
fall
time is not less than t
F
. The M48T512Y/V may re-
spond to transient noise spikes on V
CC
that cross
into the deselect window during the time the de-
vice is sampling V
CC
.Therefore, decoupling of the
power supply lines is recommended. When V
CC
drops below V
SO
, the control circuit switches pow-
er to the internal battery, preserving data and pow-
ering the clock. The internal energy source will
maintain data in the M48T512Y/V for an accumu-
lated period of at least 10 years at room tempera-
ture. As system power rises above V
SO
, the
battery is disconnected, and the power supply is
Figure 4. Block Diagram
AI02384
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8
TIMEKEEPER
REGISTERS
524,280 x 8
SRAM ARRAY
A0-A18
DQ0-DQ7
E
W
G
POWER
switched to external V
CC
. Write protection contin-
ues until V
CC
reaches V
PFD
(min) plus t
ER
(min).
Normal RAM operation can resume t
ER
after V
CC
exceeds V
PFD
(max). Refer to Application Note
(AN1012) on the ST Web Site for more information
on battery life.
CLOCK OPERATIONS
Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPORT TIMEKEEPER cells in the RAM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself. Updating is halt-
ed when a '1' is written to the READ bit, D6 in the
Control Register (7FFF8h). As long as a '1' re-
mains in that position, updating is halted. After a
halt is issued, the registers reflect the count; that
is, the day, date, and time that were current at the
moment the halt command was issued. All of the
TIMEKEEPER registers are updated simulta-
neously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a '0'.
5/14
M48T512Y, M48T512V
Table 5. Capacitance
(1)
(T
A
= 25 C, f = 1 MHz)
Note: 1. Effective capacitance measured with power supply at 5V (M48T512Y) or 3.3V (M48T512V). Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics
(T
A
= 0 to 70 C; V
CC
= 4.5V to 5.5V)
Note: 1. Outputs deselected.
Table 6B. DC Characteristics
(T
A
= 0 to 70 C; V
CC
= 3.0V to 3.6V)
Note: 1. Outputs deselected.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
20
pF
C
IO
(2)
Input / Output Capacitance
V
OUT
= 0V
20
pF
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
2
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
2
A
I
CC
Supply Current
Outputs open
115
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
8
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
4
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
2
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
2
A
I
CC
Supply Current
Outputs open
60
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
4
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
3
mA
V
IL
Input Low Voltage
0.3
0.4
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.2
V
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