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PRELIMINARY DATA
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M48T59
M48T59Y/M48T59V
64 Kbit (8Kb x8) TIMEKEEPER
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
s
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48T59: 4.5V
V
PFD
4.75V
M48T59Y: 4.2V
V
PFD
4.5V
M48T59V: 2.7V
V
PFD
3.0V
s
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
s
PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT
TOP
(to be Ordered Separately)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
s
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
s
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
s
BATTERY LOW FLAG
Figure 1. Logic Diagram
AI01380E
13
A0-A12
W
DQ0-DQ7
VCC
M48T59
M48T59Y
M48T59V
G
VSS
8
E
RST
IRQ/FT
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
IRQ/FT
Interrupt / Frequency Test
Output (Open Drain)
RST
Power Fail Reset Output
(Open Drain)
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
28
1
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery/Crytstal
PCDIP28 (PC)
Battery/Crystal
CAPHAT
M48T59, M48T59Y, M48T59V
2/21
Figure 2A. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
IRQ/FT
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
RST
VCC
AI01381D
M48T59
M48T59Y
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 1
0 to 70
C
Grade 6
40 to 85
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
M48T59/M48T59Y
0.3 to 7
V
M48T59V
0.3 to 4.6
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Mode
V
CC
E
G
W
DQ7-DQ0
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
or
3.0V to 3.6V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Figure 2B. SOIC Connections
AI01382E
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
IRQ/FT
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
RST
VCC
M48T59Y
M48T59V
3/21
M48T59, M48T59Y, M48T59V
DESCRIPTION
The M48T59/59Y/59V TIMEKEEPER
RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The 28 pin 600mil DIP CAPHATTM houses the
M48T59/59Y/59V silicon with a quartz crystal and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 3. Block Diagram
AI01383D
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
RST
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
16 x 8 BiPORT
SRAM ARRAY
8176 x 8
SRAM ARRAY
A0-A12
DQ0-DQ7
E
W
G
POWER
IRQ/FT
Figure 4. AC Testing Load Circuit
Note: Excluding open-drain output pins.
AI02325
CL = 100pF
CL includes JIG capacitance
645
DEVICE
UNDER
TEST
1.75V
M48T59, M48T59Y, M48T59V
4/21
Table 5. Capacitance
(1, 2)
(T
A
= 25 C)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
Note: 1. Outputs deselected.
2. Negative spikes of 1V allowed for up to 10ns once per cycle.
3. The IRQ/FT and RST pins are Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C)
Note: 1. All voltages referenced to V
SS
.
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Symbol
Parameter
Test Condition
M48T59/Y
M48T59V
Unit
Min
Max
Min
Max
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
1
1
A
I
CC
Supply Current
Outputs open
50
30
mA
I
CC1
Supply Current (Standby)
TTL
E = V
IH
3
2
mA
I
CC2
Supply Current (Standby)
CMOS
E = V
CC
0.2V
3
1
mA
V
IL
(2)
Input Low Voltage
0.3
0.8
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
0.4
V
Output Low Voltage (IRQ/FT
and RST)
(3)
I
OL
= 10mA
0.4
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
2.4
V
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
M48T59
4.5
4.6
4.75
V
M48T59Y
4.2
4.35
4.5
V
M48T59V
2.7
2.9
3.0
V
V
SO
Battery Back-up Switchover Voltage
M48T59/Y
3.0
V
M48T59V
V
PFD
100mV
V
t
DR
Expected Data Retention Time (at 25 C)
Grade 1
7
YEARS
Grade 6
10
(2)
YEARS
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M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(T
A
= 0 to 70 C or 40 to 85 C)
Note: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200s after V
CC
pass-
es V
PFD
(min).
2. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
3. t
REC
(min) = 20ms for industrial temperature grade 6 device.
Symbol
Parameter
Min
Max
Unit
t
PD
E or W at V
IH
before Power Down
0
s
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SS
V
CC
Fall Time
M48T59/Y
10
s
M48T59V
150
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
10
s
t
RB
V
SS
to V
PFD
(min) V
CC
Rise Time
1
s
t
REC
(3)
V
PFD
(max) to RST High
40
200
ms
Figure 5. Power Down/Up Mode AC Waveforms
AI03258
VCC
INPUTS
RST
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tREC
tRB
tDR
VALID
VALID
VPFD (max)
VPFD (min)
VSO
tPD
RECOGNIZED
RECOGNIZED
(PER CONTROL INPUT)
(PER CONTROL INPUT)
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or "M4T32-BR12SH".
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDETM clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
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