TDA7310
SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER:
- 4 STEREO INPUTS
- ONE DIFFERENTIAL STEREO INPUT FOR
REMOTE SOURCES
SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTION TO DIFFERENT SOURCES
INPUT
AND
OUTPUT
FOR
EXTERNAL
EQUALIZER OR NOISE REDUCTION SYS-
TEM
VOLUME CONTROL IN 1.25dB STEPS
LOUDNESS FUNCTION
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
SELECTABLE CHIP ADDRESS DEDICATED
PIN
DESCRIPTION
The TDA7310 is a volume, tone (bass and treble)
and fader (front/rear) processor for high quality audio
applications in car radio and Hi-Fi systems.
Loudness and selectable input gain are provided.
The control of all fuctions is accomplished by serial
bus microprocessor interface.
The AC signal setting is obtained by resistor networks
andswitches combined with operationalamplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and DC stepping are ob-
tained.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
November 1999
PQFP44 (10 x 10)
ORDERING NUMBER: TDA7310
PIN CONNECTION (Top view)
1/15
THERMAL DATA
Symbol
Description
Value
Unit
R
th j-pins
Thermal Resistance Junction-pins
max
85
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
103
dB
Volume Control
1.25dB step
-78.75
0
dB
Bass and Treble Control
2dB step
-14
+14
dB
Fader and Balance Control
1.25dB step
-38.75
0
dB
Input Gain
6.25dB step
0
18.75
dB
Mute Attenuation
100
dB
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.2
V
T
amb
Ambient Temperature
-40 to 85
C
T
stg
Storage Temperature Range
-55 to +150
C
TEST CIRCUIT
TDA7310
2/15
L1
28
L1
L2
27
L2
L3
26
L3
L4
25
L4
L5
16
L5
INPUT
SELECTOR
+
GAIN
C1
C2
C3
C4
C5
LEFT
INPUTS
CD
4x
2.2
F
4.7
F
R5
17
SUPPLY
SGND
10
F
C6
18
R5
R4
19
R4
R3
20
R3
R2
21
R2
24
R1
C7
C8
C9
C10
C11
4x
2.2
F
R1
4.7
F
RIGHT
INPUTS
897
V
CC
AGND
CREF
C14
2.2
F
OUT(L)
IN(L)
30
29
VOL
+
LOUD
LOUDSW
38
39
C16
100nF
100nF
BASS
LOUD(L)
C19
32
5.6K
R2
BOUT(L)
31
BIN(L)
C20
100nF
RB
TREBLE
C22
2.7nF
TREBLE(L)
10
MUTE
D94AU170
MUTE
SERIAL
BUS
DECODER
+
LATCHES
SPKR
ATT
SPKR
ATT
2
42
VOL
+
LOUD
BASS
TREBLE
OUT(R)
IN(R)
C13
2.2
F
15
14
40
C15
LOUD(R)
100nF
100nF
100nF
C17
C18
5.6K
R1
BOUT(R)
BIN(R)
36
35
RB
C21
2.7nF
TREBLE(R)
MUTE
SPKR
ATT
MUTE
SPKR
ATT
50K
37
6
5
4
3
43
41
ADDR
SCL
SEN
SDA
DIGGND
BUS
OUT
RIGHT
FRONT
OUT
RIGHT
REAR
+V
CC
OUT
LEFT
REAR
OUT
LEFT
FRONT
13
22
F
C12
BLOCK DIAGRAM
TDA7310
3/15
ELECTRICAL CHARACTERISTICS (T
amb
= 25
C, V
S
= 9V, R
L
= 10K
, R
G
= 600
, G
V
=0dB, f = 1KHz
unless otherwise specified) (refer to the test circuit)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
6
9
10
V
I
S
Supply Current
4
8
11
mA
SVR
Ripple Rejection
60
85
dB
INPUT SELECTORS
R
II
Input Resistance
Input 1, 2, 3, 4
50
K
Differential Input
10
K
V
CL
Clipping Level
2
2.5
Vrms
CMRR
Common Mode Rejection
Differential Input
65
dB
INS
Input Separation (2)
80
100
dB
R
L
Output Load resistance
2
K
G
INmin
Min. Input Gain
-1
0
1
dB
G
INmax
Max. Input Gain
18.75
dB
G
STEP
Step Resolution
6.25
dB
e
IN
Input Noise
G = 18.75dB
2
V
V
DC
DC Steps
adjacent gain steps
4
mV
G = 18.75 to Mute
4
mV
VOLUME CONTROL
R
IN
Input Resistance
33
k
C
RANGE
Control Range
75
dB
A
VMIN
Min. Attenuation
-1
0
1
dB
A
VMAX
Max. Attenuation
75
dB
A
STEP
Step Resolution
1.25
dB
E
A
Attenuation Set Error
A
V
= 0 to -20dB
A
V
= -20 to -60dB
-1.25
-3
0
1.25
2
dB
dB
E
T
Tracking Error
2
dB
V
DC
DC Steps
adjacent attenuation steps
From 0dB to A
Vmax
0.1
0.5
mV
mV
SPEAKER ATTENUATORS
Control Range
37.5
dB
Step Resolution
1.25
dB
Attenuation set error
1.5
dB
Output Mute Attenuation
80
100
dB
DC Steps
adjacent att. steps
from 0 to mute
0
1
mV
mV
BASS CONTROL (1)
Control Range
+14
dB
Step Resolution
2
dB
R
B
Internal Feedback Resistance
50
K
V
DC
DC Steps
adjacent control steps
0.1
mV
TDA7310
4/15
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
TREBLE CONTROL (1)
Control Range
+14
dB
Step Resolution
2
dB
V
DC
DC Steps
adjacent control steps
0.1
mV
AUDIO OUTPUTS
Clipping Level
d = 0.3%
2.5
Vrms
Output Load Resistance
2
K
Output Load Capacitance
10
nF
Output resistance
75
120
DC Voltage Level
4.2
4.5
4.8
V
GENERAL
e
NO
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB
2.5
5
15
V
V
S/N
Signal to Noise Ratio
all gains = 0dB; V
O
= 1Vrms
106
dB
d
Distortion
V
IN
= 1Vrms
0.01
%
Sc
Channel Separation left/right
80
103
dB
Total Tracking error
A
V
= 0 to -20dB
-20 to -60 dB
0
0
1
2
dB
dB
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
V
LOUDNESS SWITCH
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
I
IN
Input Current
-5
+5
A
DC Step
ON
OFF position
0.1
mV
Loudness OFF = pin38 Open;
Loudness ON = pin 38 Closed to GND
ADDRESS PIN (Internal 50K
pull down resistor)
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
V
CC
-1V
V
I
IN
Input Current
A
Notes:
(1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2
F capacitor.
TDA7310
5/15
APPLICATION SUGGESTION (see to Test circuit)
Component
Recc. Value
Purpose
Smaller than Recc. Value
Larger than
C1 to C4,
C8 to C11
2.2
F
THD optimization at low
frequencies
Worse THD at very low
frequencies
C5, C7
C6
4.7
F
10
F
CMRR optimization
differential input
Worse CMRR for ratio not equal to
1
/
2
C12
22
F
C
REF
SVR optimization
< -66 dB
Better SVR at low
frequencies
Worse SVR at low
frequencies
C13, C14
2.2
F
Decoupling Input-Output
if external equalizer is
not used
C15, C16
100nF
Loudness characteristic
C17, C18
R1
C!9, C20
R2
100nF
5.6k
100nF
5.6k
Bass Filter
(standard T - type)
cut freq. = 100Hz
C21
C22
2.7nF
Treble Filter
Higher cut frequency
Lower cut frequency
Figure 1: Loudness versus Volume Attenuation
Figure 2: Loudnessversus Frequency
(C
LOUD
= 100nF)
TDA7310
6/15
Figure 3: Loudness versus External Capacitors
LOUDNESS
V
S
= 9V
Volume = -40dB
All other control flat
C
in
= 2.2
F
Figure 4: Noise vs. Volume/Gain Settings
Figure 5: Signal to Noise Ratio vs. Volume
Setting
Figure 6: Distortion vs. Load Resistance
TDA7310
7/15
Figure 8 : Input Separation (L1
L2, L3, L4) vs.
Frequency
Figure 7 : Channel Separation (L
R) vs.
Frequency
Figure 9 : Supply Voltage Rejection vs.
Frequency
Figure 10: Output Clipping Level vs. Supply
Voltage
TDA7310
8/15
Figure 12: Supply Current vs. Temperature
Figure 14: Typical Tone Response (with the ext.
components indicated in the test
circuit)
Figure 11: Quiescent Current vs. Supply Voltage
Figure 13: Bass Resistance vs. Temperature
TDA7310
9/15
Figure 15: Data Validity on the I
2
CBUS
Figure 17: Acknowledge on the I
2
CBUS
APPLICATION INFORMATION (continued)
SERIAL BUS INTERFACE
S-BUS Interface and I
2
CBUS Compability
Data transmission from microprocessor to the
TDA7310 and viceversa takes place thru the 3-
wire S-BUS interface, consisting of the three lines
SDA, SCL, SEN. If SDA and SEN inputs are
short-circuited together, then the TDA7310 ap-
pears as a standard I
2
CBUS slave.
According to I
2
CBUS specification the S-BUS
lines are connected to a positive supply voltage
via pull-up resistors.
Data Validity
As shown in fig. 15, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop Conditions
I
2
CBUS:
as shown in fig. 16 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
S-bus:
the start/stop conditions (points 1 and 6) are de-
tected exclusively by a transition of the SEN line
(1
0 / 0
1)wile the SCL line is at the HIGH
level.
The SDA line is only allowed to change during the
time the SCL line is low (points 2, 3, 4, 5). after
the start information (point 1) the SEN line returns
to the HIGH level and remains uncharged for all
the time the transmission is performed.
Byte Fornat
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse
(see fig. 17). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock.
Figure 16: Timing Diagram of S-BUS and I
2
CBUS
TDA7310
10/15
APPLICATION INFORMATION (continued)
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7310
address (the 8th bit of the byte must be 0). The
TDA7310 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
SOFTWARE SPECIFICATION
Chip address
1
MSB
0
0
0
1
0
A
0
LSB
A = LOGIC LEVEL ON PIN ADDR
DATA BYTES
MSB
LSB
FUNCTION
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
B2
0
1
0
1
0
1
1
B1
B1
B1
B1
B1
G1
0
1
B0
B0
B0
B0
B0
G0
C3
C3
A2
A2
A2
A2
A2
S2
C2
C2
A1
A1
A1
A1
A1
S1
C1
C1
A0
A0
A0
A0
A0
S0
C0
C0
Volume control
Speaker ATT LR
Speaker ATT RR
Speaker ATT LF
Speaker ATT RF
Audio switch
Bass control
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
STATUS AFTER POWER ON RESET
Volume
speaker
audio Switch
bass
treble
gain
-77.5dB
-37.5dB
Stereo 5
+2dB
+2dB
0dB
TDA7310 ADDRESS
MSB
first byte
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
1
0
A
0
ACK
DATA
ACK
DATA
ACK
P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
TDA7310
11/15
SOFTWARE SPECIFICATION (continued)
DATA BYTES (detailed description)
Volume
MSB
LSB
FUNCTION
0
0
B2
B1
B0
A2
A1
A0
Volume 1.25dB steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
0
B2
B1
B0
A2
A1
A0
Volume 10dB steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-10
-20
-30
-40
-50
-60
-70
For example a volume of -45dB is given by:
0 0 1 0 0 1 0 0
Speaker Attenuators
MSB
LSB
FUNCTION
1
1
1
1
0
0
1
1
0
1
0
1
B1
B1
B1
B1
B0
B0
B0
B0
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
Speaker LF
Speaker RF
Speaker LR
Speaker RR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
0
1
1
0
1
0
1
0
-10
-20
-30
1
1
1
1
1
Mute
For example attenuation of 25dB on speaker RF is given by:
1 0 1 1 0 1 0 0
TDA7310
12/15
Audio Switch
MSB
LSB
FUNCTION
0
1
0
G1
G0
S2
S1
S0
Audio Switch
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Stereo 1
Stereo 2
Stereo 3
Stereo 4
Stereo 5
Not allowed
Not allowed
Not allowed
0
0
1
1
0
1
0
1
+18.75dB
+12.5dB
+6.25dB
0dB
For example to select the stereo 2 input with a gain of +12.5dB the 8bit string is:
0 1 0 0 1 0 0 1
Bass and Treble
0
0
1
1
1
1
0
1
C3
C3
C2
C2
C1
C1
C0
C0
Bass
Treble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string:
0 1 1 0 0 0 1 0
Purchase of I
2
C Components from STMicroelectronics, conveys a license under the Philips I
2
C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C
Standard Specifications as defined by Philips.
TDA7310
13/15
PQFP44 (10 x 10)
A
A2
A1
B
Seating Plane
C
11
12
22
23
33
34
44
E3
D3
E1
E
D1
D
e
1
K
B
PQFP44
L
L1
0.10mm
.004
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.45
0.096
A1
0.25
0.010
A2
1.95
2.00
2.10
0.077
0.079
0.083
B
0.30
0.45
0.012
0.018
c
0.13
0.23
0.005
0.009
D
12.95
13.20
13.45
0.51
0.52
0.53
D1
9.90
10.00
10.10
0.390
0.394
0.398
D3
8.00
0.315
e
0.80
0.031
E
12.95
13.20
13.45
0.510
0.520
0.530
E1
9.90
10.00
10.10
0.390
0.394
0.398
E3
8.00
0.315
L
0.65
0.80
0.95
0.026
0.031
0.037
L1
1.60
0.063
K
0
(min.), 7
(max.)
OUTLINE AND
MECHANICAL DATA
TDA7310
14/15
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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TDA7310
15/15
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