TDA7311
SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
TWO STEREO DIFFERENTIAL INPUTS
TWO STEREO SINGLE ENDED INPUTS
ONE MONO DIFFERENTIAL INPUT
INPUT
AND
OUTPUT
FOR
EXTERNAL
EQUALIZER OR NOISE REDUCTION SYS-
TEM
VOLUME CONTROL IN 1.25dB STEPS
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SPI
COMPATIBLE SERIAL BUS
DESCRIPTION
The TDA7311 is a volume, tone (bass and treble)
and fader (front/rear) processor for high quality
audio applications in car radio and Hi-Fi systems.
Control is accomplished by serial bus microproc-
essor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS technology,
low distortion, low noise and DC stepping are ob-
tained.
July 1999
PINS CONNECTION (Top view)
ORDERING NUMBER: TDA7311
DIP40
1/11
TEST CIRCUIT
THERMAL DATA
Symbol
Description
DIP40
Unit
R
th j-pins
Thermal Resistance Junction-pins
max
85
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
8
10
11
V
V
CL
Max. input signal handling
2.3
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
95
dB
Volume Control
1.25dB step
-78.75
+11.25
dB
Treble Control
2dB step
-14
+14
dB
BR
SS
Bass Control 2dB step
20
+20
dB
Fader and Balance Control
1.25dB step
-38.75
0
dB
Mute Attenuation
92
dB
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
11.2
V
T
op
Operating Temperature Range
-40 to 85
C
T
stg
Storage Temperature Range
-55 to +150
C
TDA7311
2/11
9
8
4
5
IN4
IN3
DIFF
STEREO
1
LEFT
INPUTS
SUPPLY
SECMUTE
34
35
RIGHT
INPUTS
14
0
2
V
CC
AN-GND
CREF
10
11
VOL
BASS
12
13
TREBLE
14
MUTE
D94AU178
MUTE
SPI
BUS
DECODER
+
LATCHES
SPKR
ATT
SPKR
ATT
15
16
VOL
BASS
TREBLE
31
30
29
28
MUTE
SPKR
ATT
MUTE
SPKR
ATT
20
19
18
21
26
25
CL
DA
CE
DIG
GND
OUT
RIGHT
FRONT
OUT
RIGHT
REAR
OUT
LEFT
REAR
OUT
LEFT
FRONT
27
7
6
DIFF
STEREO
2
38
3
DIFF
MONO
SECMUTE
37
36
33
32
DIFF
STEREO
2
DIFF
STEREO
1
IN3
IN4
BLOCK DIAGRAM
TDA7311
3/11
ELECTRICAL CHARACTERISTICS (T
amb
= 25
C, V
CC
= 10V, R
L
= 10K
, R
G
= 600
, G
V
=0dB,
f = 1KHz unless otherwise specified) (refer to the test circuit)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
8
10
11
V
I
S
Supply Current
15
20
mA
SVR
Ripple Rejection
55
80
dB
INPUT SELECTORS
R
II
Input Resistance
Single Ended inputs
30
50
70
K
Differential Inputs
10
20
K
V
CL
Clipping Level
Single Ended Inputs
2.3
2.8
Vrms
Differential Inputs
4.6
5.6
Vrms
CMRR
Common Mode Rejection
Differential Inputs
65
dB
INS
Input Separation (2)
70
90
dB
R
L
Output Load resistance
2
K
C
L
Output Load capacitance
1
nF
R
O
Output Impedance
15
50
G
IN
Input Gain
Single Ended Inputs
-1
0
1
dB
differential Inputs
-7
-6
-5
dB
VOLUME CONTROL
R
IN
Input Resistance
15
30
k
G
R
Control Range
Max. Attenuation
75
dB
Max. Gain
+11.25
dB
A
STEP
Step Resolution
1.25
dB
E
A
Attenuation Set Error
A
V
= +11.25 to -20dB
A
V
= -20 to -60dB
-1.25
-3
0
1.25
2
dB
dB
E
T
Tracking Error
2
dB
V
DC
DC Steps
adjacent attenuation steps
From 0dB to A
Vmax
0
1
3.0
10.0
mV
mV
Vimax.
Max. Input Voltage
2.3
2.8
Vrms
SPEAKER ATTENUATORS
A
R
Control Range
37.5
dB
A
step
Step Resolution
1.25
dB
E
A
Attenuation set error
1.5
dB
V
DC
DC Steps
adjacent att. steps
from 0 to mute
0
1
mV
mV
BASS CONTROL (1)
Control Range
+20
dB
Step Resolution
2
dB
Attenuation / Gain set error
2.0
2.0
dB
TREBLE CONTROL (1)
Control Range
+14
dB
Step Resolution
2.0
dB
Attenuation / Gain set error
1.0
0
1.0
dB
TDA7311
4/11
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUDIO OUTPUTS
Output Voltage
d = 0.3%
2.3
2.8
Vrms
Output Load Resistance
2
K
Output Load Capacitance
10
nF
Output resistance
25
75
DC Voltage Level
4.6
5.0
5.4
V
GENERAL
e
NO
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB Single Ended
all gains = 0dB Diff. Inputs
4
5
10
15
30
V
V
V
S/N
Signal to Noise Ratio
all gains = 0dB; V
O
= 1Vrms
Single Ended
Differential Inputs
106
100
dB
dB
d
Distortion
V
IN
= 1Vrms
0.01
%
Sc
Channel Separation left/right
70
95
dB
Total Tracking error
A
V
= 0 to -20dB
A
V
= -20 to -60 dB
A
V
= 0dB to 11.25dB
0
0
0
1
2
1
dB
dB
dB
Output Attenuation
Mute Condition (3)
80
90
dB
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
Notes:
(1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2
F capacitor.
(3) Condition obtained programming: mute on speaker attenuators (1X111111) followed by selection of SECMUTE (1XXXX111).
TDA7311
5/11
APPLICATION INFORMATION
SERIAL BUS INTERFACE
The serial bus interface is compatible to SPI bus
systems.
During the LOW state of the chip enable signal
(CE) the data on pin DA are clocked into the shift
register at the LOW to HIGH transition of the
clock signal CL.
At the LOW to HIGH transition of the CE signal
the content of the internal shift register is stored
into the addressed latches.
The transmission is separated into bytes with 8 bit
according to the data specification of the audio-
processor. After every byte a positive slope of the
CE signal has to be generated in order to store
the data byte.
A special clock counter enables the latch of the
data byte only, if exactly 8 clocks were present
during the LOW state of the CE signal. This re-
sults in a high immunity against spikes on the
clock line and avoids a storage of wrong databy-
tes.
Figure 1: BUS Timing
Nr.
Parameter
Min.
Max.
Units
Clock Frequency
250
KHz
1
CE Lead time
4
s
2
Clock High Time
2
s
3
Clock Low Time
2
s
4
Data Hold Time
1.8
s
5
Data Setup Time
1.8
s
6
Clock Setup Time
0
s
7
CE lagtime
0
s
8
Clock Hold Time
6
s
9
CE High TIme
6
s
TDA7311
6/11
SECOND BYTE
VOLUME ATTENUATION
MSB
LSB
1
X
B2
B1
B0
A2
A1
A0
Volume 1.25dB Steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5.00
-6.25
-7.50
-8.75
1
X
B2
B1
B0
Volume 10dB Steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-10
-20
-30
-40
-50
-60
-70
SOFTWARE SPECIFICATION
Data Bytes
FIRST BYTE
MSB
LSB
Function
0
0
0
0
X
X
X
X
VOL ATTENUATION
0
1
0
0
X
X
X
X
VOL GAIN
0
0
1
0
X
X
X
X
BASS
0
1
1
0
X
X
X
X
TREBLE
0
0
0
1
X
X
X
X
ATT RF (speaker)
0
1
0
1
X
X
X
X
ATT RR (speaker)
0
0
1
1
X
X
X
X
ATT LF (speaker)
0
1
1
1
0
X
X
X
ATT LR (speaker)
0
1
1
1
1
X
X
X
AUDIO SWITCH
STATUS AFTER POWER-ON RESET
Volume
78.75dB
Speaker
Mute
Audio Switch
Mute
Bass
20dB
Treble
14dB
TDA7311
7/11
SOFTWARE SPECIFICATION (continued)
VOLUME GAIN
MSB
LSB
1.25dB STEPS
1
X
X
X
0
0
0
0
0.00
1
X
X
X
0
0
0
1
1.25
1
X
X
X
0
0
1
0
2.50
1
X
X
X
0
0
1
1
3.75
1
X
X
X
0
1
0
0
5.00
1
X
X
X
0
1
0
1
6.25
1
X
X
X
0
1
1
0
7.50
1
X
X
X
0
1
1
1
8.75
1
X
X
X
1
0
0
0
10.00
1
X
X
X
1
0
0
1
11.25
SPEAKER ATTENUATION
MSB
LSB
1.25dB STEPS
1
0
0
0
0
1
0
0
1
-1.25
1
0
1
0
-2.50
1
0
1
1
-3.75
1
1
0
0
-5.00
1
1
0
1
-6.25
1
1
1
0
-7.50
1
1
1
1
-8.75
10dB STEPS
1
X
0
0
0
0
1
X
0
0
1
-10
1
X
0
1
0
-20
1
X
0
1
1
-30
1
X
1
1
1
1
1
1
MUTE
AUDIO SWITCH
MSB
LSB
INPUT
1
X
X
X
X
0
0
0
MONO
1
X
X
X
X
0
0
1
DIFF1
1
X
X
X
X
0
1
0
DIFF2
1
X
X
X
X
0
1
1
IN3
1
X
X
X
X
1
0
0
IN4
1
X
X
X
X
1
1
1
SECMUTE
TDA7311
8/11
SOFTWARE SPECIFICATION (continued)
TREBLE
MSB
LSB
2dB STEPS
1
X
X
X
0
1
1
1
14
1
X
X
X
0
1
1
0
12
1
X
X
X
0
1
0
1
10
1
X
X
X
0
1
0
0
8
1
X
X
X
0
0
1
1
6
1
X
X
X
0
0
1
0
4
1
X
X
X
0
0
0
1
2
1
X
X
X
0
0
0
0
0
1
X
X
X
1
0
0
0
-0
1
X
X
X
1
0
0
1
-2
1
X
X
X
1
0
1
0
-4
1
X
X
X
1
0
1
1
-6
1
X
X
X
1
1
0
0
-8
1
X
X
X
1
1
0
1
-10
1
X
X
X
1
1
1
0
-12
1
X
X
X
1
1
1
1
-14
BASS
MSB
LSB
2dB STEPS
1
X
X
1
1
1
1
1
-20
1
X
X
1
1
0
0
1
-18
1
X
X
1
1
0
0
0
-16
1
X
X
1
0
1
1
1
-14
1
X
X
1
0
1
1
0
-12
1
X
X
1
0
1
0
1
-10
1
X
X
1
0
1
0
0
-8
1
X
X
1
0
0
1
1
-6
1
X
X
1
0
0
1
0
-4
1
X
X
1
0
0
0
1
-2
1
X
X
1
0
0
0
0
0
1
X
X
0
0
0
0
0
0
1
X
X
0
0
0
0
1
2
1
X
X
0
0
0
1
0
4
1
X
X
0
0
0
1
1
6
1
X
X
0
0
1
0
0
8
1
X
X
0
0
1
0
1
10
1
X
X
0
0
1
1
0
12
1
X
X
0
0
1
1
1
14
1
X
X
0
1
0
0
0
16
1
X
X
0
1
0
0
1
18
1
X
X
0
1
1
1
1
20
TDA7311
9/11
DIM.
mm
inch
MIN
TYP
MAX
MIN
TYP
MAX
a1
0.63
0.025
b
0.45
0.018
b1
0.23
0.31
0.009
0.012
b2
1.27
0.050
D
52.58
2.070
E
15.2
16.68
0.598
0.657
e
2.54
0.100
e3
48.26
1.900
F
14.1
0.555
I
4.445
0.175
L
3.3
0.130
DIP40
OUTLINE AND
MECHANICAL DATA
TDA7311
10/11
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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TDA7311
11/11
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