TDA7312
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
INPUT MULTIPLEXER:
- 4 STEREO INPUTS
FOUR SELECTABLE ADDRESSES
TWO DIGITAL CONTROL OUTPUTS
INPUT
AND
OUTPUT
FOR
EXTERNAL
EQUALIZER OR NOISE REDUCTION SYS-
TEM
VOLUME CONTROL IN 1.25dB STEPS
TREBLE AND BASS CONTROL
TWO SPEAKER ATTENUATORS:
- INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I
2
C BUS
DESCRIPTION
The TDA7312 is a volume, tone (bass and treble)
balance (Left/Right) processor for quality audio appli-
cations.
Control is accomplished by serial I
2
C bus microproc-
essor interface.
The AC signal setting is obtained by resistor networks
andswitches combined with operationalamplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and Low DC stepping are
obtained.
November 1999
SDIP30
ORDERING NUMBER: TDA7312
PIN CONNECTION (Top view)
1/13
THERMAL DATA
Symbol
Description
SDIP30
Unit
R
th j-pins
Thermal Resistance Junction-pins
m ax
85
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.1
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
103
dB
Volume Control
1.25dB step
-78.75
0
dB
Bass and Treble Control
2db step
-14
+14
dB
Fader and Balance Control
1.25dB step
-38.75
0
dB
Mute Attenuation
100
dB
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.2
V
T
amb
Operating Ambient Temperature
0 to 70
C
T
stg
Storage Temperature Range
-40 to 150
C
TEST CIRCUIT
TDA7312
2/13
BLOCK DIAGRAM
TDA7312
3/13
ELECTRICAL CHARACTERISTICS (refer to the test circuit T
amb
= 25
C, V
S
= 9V, R
L
= 10K
,
R
G
= 600
, all controls flat (G = 0), f = 1KHz unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
6
9
10
V
I
S
Supply Current
8
11
mA
SVR
Ripple Rejection
60
80
dB
INPUT SELECTORS
R
II
Input Resistance
Input 1, 2, 3
35
50
70
K
V
CL
Clipping Level
2
2.5
Vrms
S
IN
Input Separation (2)
80
100
dB
R
L
Output Load resistance
2
K
e
IN
Input Noise
2
V
VOLUME CONTROL
R
IV
Input Resistance
20
33
50
k
C
RANGE
Control Range
70
75
80
dB
A
VMIN
Min. Attenuation
-1
0
1
dB
A
VMAX
Max. Attenuation
70
75
80
dB
A
STEP
Step Resolution
0.5
1.25
1.75
dB
E
A
Attenuation Set Error
Av = 0 to -20dB
Av = -20 to -60dB
-1.25
-3
0
1.25
2
dB
dB
E
T
Tracking Error
2
dB
V
DC
DC Steps
adjacent attenuation steps
From 0dB to Av max
0
0.5
3
7.5
mV
mV
SPEAKER ATTENUATORS
C
range
Control Range
35
37.5
40
dB
S
STEP
Step Resolution
0.5
1.25
1.75
dB
E
A
Attenuation set error
1.5
dB
A
MUTE
Output Mute Attenuation
80
100
dB
V
DC
DC Steps
adjacent att. steps
from 0 to mute
0
1
3
10
mV
mV
BASS CONTROL (1)
Gb
Control Range
Max. Boost/cut
+12
+14
+16
dB
B
STEP
Step Resolution
1
2
3
dB
R
B
Internal Feedback Resistance
34
44
58
K
TREBLE CONTROL (1)
Gt
Control Range
Max. Boost/cut
+13
+14
+15
dB
T
STEP
Step Resolution
1
2
3
dB
DIGITAL OUTPUTS
V
CESAT
V
OUT
= Low I
C
=1mA
0.2
0.3
V
I
leak
I leakage
V
OUT
= V
S
10
A
TDA7312
4/13
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUDIO OUTPUTS
V
OCL
Clipping Level
d = 0.3%
2
2.5
Vrms
R
L
Output Load Resistance
2
K
C
L
Output Load Capacitance
10
nF
R
OUT
Output resistance
30
75
120
V
OUT
DC Voltage Level
4.2
4.5
4.8
V
GENERAL
e
NO
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB
2.5
5
15
V
V
A curve all gains = 0dB
3
V
S/N
Signal to Noise Ratio
all gains = 0dB; V
O
= 1Vrms
106
dB
d
Distortion
A
V
= 0, V
IN
= 1Vrms
A
V
= -20dB V
IN
= 1Vrms
V
IN
= 0.3Vrms
0.01
0.09
0.04
0.1
0.3
%
%
%
Sc
Channel Separation left/right
80
103
dB
Total Tracking error
A
V
= 0 to -20dB
-20 to -60 dB
0
0
1
2
dB
dB
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
I
IN
Input Current
-5
+5
A
V
O
Output Voltage SDA Acknowledge
I
O
= 1.6mA
0.4
V
ADDRESS PIN (Internal 50K
pull down resistor).
Notes:
SDA, SCL, DIG OUT 1, DIG OUT 2 Pins are high impedance when V
S = 0
(1) Bass and Treble response see attached diagram (fig.16). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2
F capacitor.
Figure 2: Signal to Noise Ratio vs. Volume
Setting
Figure 1: Noise vs. Volume/Gain Settings
TDA7312
5/13
Figure 3: Distortion & Noise vs. Frequency
Figure 4: Distortion & Noise vs. Frequency
Figure 5: Distortion vs. Load Resistance
Figure 7: Input Separation (L1
L2, L3, L4) vs.
Frequency
Figure 6: Channel Separation (L
R) vs.
Frequency
Figure 8: Supply Voltage Rejection vs.
Frequency
TDA7312
6/13
Figure 9: Output Clipping Level vs. Supply
Voltage
Figure 11: Supply Current vs. Temperature
Figure 10: Quiescent Current vs. Supply Voltage
Figure 13: Typical Tone Response (with the ext.
components indicated in the test
circuit)
Figure 12: Bass Resistance vs. Temperature
TDA7312
7/13
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7312 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 14, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop Conditions
As shown in fig.15 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 16). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 14: Data Validity on the I
2
CBUS
Figure 15: Timing Diagram of I
2
CBUS
Figure 16: Acknowledge on the I
2
CBUS
TDA7312
8/13
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7312
address (the 8th bit of the byte must be 0). The
TDA7312 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7312 ADDRESS
MSB
first byte
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
1 ADDR
2
ADDR
1
0
ACK
DATA
ACK
DATA
ACK
P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
SOFTWARE SPECIFICATION
Chip address
1
MSB
0
0
0
1
ADDR
2
ADDR
1
0
LSB
DATA BYTES
MSB
LSB
FUNCTION
0
1
1
0
0
0
0
0
0
1
1
1
B2
0
1
0
1
1
B1
B1
B1
D2
0
1
B0
B0
B0
D1
C3
C3
A2
A2
A2
S2
C2
C2
A1
A1
A1
S1
C1
C1
A0
A0
A0
S0
C0
C0
Volume control
Speaker ATT L
Speaker ATT R
Audio switch
Bass control
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Sx = Input Selector; D
X
= Dig Out Pins
ADDR2 ADDR1
CHIP ADDRESS
0
0
88 HEX
0
1
8A HEX
1
0
8C HEX
1
1
8E HEX
TDA7312
9/13
SOFTWARE SPECIFICATION (continued)
DATA BYTES (detailed description)
Volume
MSB
LSB
FUNCTION
0
0
B2
B1
B0
A2
A1
A0
Volume 1.25dB steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
0
B2
B1
B0
A2
A1
A0
Volume 10dB steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-10
-20
-30
-40
-50
-60
-70
For example a volume of -45dB is given by:
0 0 1 0 0 1 0 0
Speaker Attenuators
MSB
LSB
FUNCTION
1
1
0
0
0
1
B1
B1
B0
B0
A2
A2
A1
A1
A0
A0
Speaker L
Speaker R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
0
1
1
0
1
0
1
0
-10
-20
-30
1
1
1
1
1
Mute
For example attenuation of 25dB on speaker R is given by:
1 0 1 1 0 1 0 0
TDA7312
10/13
Audio Switch
MSB
LSB
FUNCTION
0
1
0
D2
D1
S2
S1
S0
Audio Switch
1
1
1
1
0
0
1
1
0
1
0
1
Stereo 1
Stereo 2
Stereo 3
Stereo 4
0
1
0
1
DIG. OUT 1 = 0
DIG. OUT 1 = 1
DIG. OUT 2 = 0
DIG. OUT 2 = 1
Bass and Treble
0
0
1
1
1
1
0
1
C3
C3
C2
C2
C1
C1
C0
C0
Bass
Treble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string:
0 1 1 0 0 0 1 0
Status at Power on Reset
Volume = 78.75dB
Treble = Bass = +2dB
Spkrs Attenuators = Mute
Input = Stereo 1
Dig. OUT 1 = Dig. OUT 2 = 1
TDA7312
11/13
SDIP30 (0.400")
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
5.08
0.20
A1
0.51
0.020
A2
3.05
3.81
4.57
0.12
0.15
0.18
B
0.36
0.46
0.56
0.014
0.018
0.022
B1
0.76
0.99
1.40
0.030
0.039
0.055
C
0.20
0.25
0.36
0.008
0.01
0.014
D
27.43
27.94
28.45
1.08
1.10
1.12
E
10.16
10.41
11.05
0.400
0.410
0.435
E1
8.38
8.64
9.40
0.330
0.340
0.370
e
1.778
0.070
e1
10.16
0.400
L
2.54
3.30
3.81
0.10
0.13
0.15
M
0
(min.), 15
(max.)
S
0.31
0.012
OUTLINE AND
MECHANICAL DATA
TDA7312
12/13
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
Purchase of I
2
C Components of STMicroelectronics, conveys a license under the Philips I
2
C Patent Rights to use these components in an
I
2
C system, provided that the system conforms to the I
2
C Standard Specifications as defined by Philips.
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TDA7312
13/13
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