TDA7330B
SINGLE CHIP RDS DEMODULATOR + FILTER
HIGH PERFORMANCE, 57KHz BANDPASS
FILTER (8th ORDER)
FILTER ADJUSTMENT FREE AND WITHOUT
EXTERNAL COMPONENTS
PURELY DIGITAL RDS DEMODULATION
WITHOUT EXTERNAL COMPONENTS
ARI (SK INDICATION) AND RDS SIGNAL
QUALITY OUTPUT
4.332MHz CRYSTAL OSCILLATOR
(8.664MHz OPTIONAL)
LOW NOISE MIXED BIPOLAR/CMOS TECH-
NOLOGY
DESCRIPTION
The TDA7330B is a RDS demodulator. It recov-
ers the additional inaudible RDS information
which is transmitted by FM radio broadcasting
stations.
The output data signal (RDDA) and clock signal
(RDCL) can be further processed by a suitable
RDS decoder (microprocessor).
The device operates in accordance with the EBU
(European Broadcasting Union) specifications.
The IC includes a 2nd order antialiasing input fil-
ter, a 57KHz switched capacitor band pass filter,
a smoothing filter and cross detector, a bit rate
clock recovery circuit, a 57KHz PLL, BI-PHASE
PSK decoder, differential decoding circuit, ARI in-
dication and RDS signal quality output.
November 1999
BLOCK DIAGRAM
DIP20
SO20
ORDERING NUMBERS:
TDA7330B
TDA7330BD
1/9
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
7
V
T
op
Operating Temperature Range
-40 to 85
C
T
stg
Storage Temperature
-40 to 150
C
THERMAL DATA
Symbol
Description
DIP20
SO20
Unit
R
th j-case
Thermal Resistance Junction-case
Typ.
100
200
C/W
PIN CONNECTION (Top view)
Nr.
Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MUXIN
V
ref
COMP
FIL OUT
GND
T1
T3
T4
OSC OUT
OSC IN
T57
RDCL
RDDA
QUAL
ARI
V
CC
T2
FSEL
TM
POR
RDS input signal.
Reference voltage
Not inverting comparator input (smoothing filter)
Filter Output
Ground
Testing output pin (not to be used)
Testing output pin (not to be used)
Testing output pin (not to be used)
Oscillator output
Oscillator Input
Testing output pin: 57KHz clock output
RDS clock output (1187.5Hz)
RDS data output
Output for signal quality indication (High = good)
Output for ARI indication (High when RDS + ARI signals are present)
(High when only ARI is present)
(Low when only RDS is present)
(indefined when no signal is present)
Supply Voltage
Testing output pin (not to be used)
Frequency selector pin: open = 4.332MHz, closed to V
CC
= 8.664MHz
Test mode pin (open = normal RUN)
(closed to V
CC
= Test mode)
Reset Input for testing (active high)
PIN FUNCTION
TDA7330B
2/9
ELECTRICAL CHARACTERISTICS (V
CC
= 5V, Tamb = 25
C; R
g
= 600
; fosc = 4.332MHz;
V
IN
= 20mVrms unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
CC
Supply Voltage
4.5
5
5.5
V
I
S
Supply Current
9
mA
R
POR
POR Pull Down Resistor
pin 20
40
K
POR
ON
POR Threshold
2.5
V
FILTER(measured an pin 4 FILOUT)
F
C
Center Frequency
56.5
57
57.5
KHz
BW
3dB Bandwidth
2.5
3
3.5
KHz
G
Gain
f = 57KHz
18
20
22
dB
A
Attenuation
f = +4KHz
f = 38KHz; V
i
= 500mVrms
f = 67KHz; V
i
= 250mVrms
18
50
35
22
80
50
dB
dB
dB
Ph
Phase non linearity
A (see note1)
B (see note1)
C (see note1)
0.5
1
2
5
7.5
10
DEG
DEG
DEG
R
i
Input Impedance
100
160
200
K
S/N
Signal to Noise Ratio
V
i
= 3mVrms
30
40
dB
V
i
Maximum Input Signal Capability
f = 19KHz; T3 < 40dB (see note2)
f = 57KHz (RDS + ARI)
1
50
Vrms
mVrms
R
L
Load Impedance
Pin 4
100
K
CROSS DETECTOR
RA
Resistance pin 3-4
15
21
28
K
OSCILLATOR
F
OSC
Oscillator Frequency
F
SEL
= Open (*)
F
SEL
= Closed to V
CC
(**)
4.332
8.664
MHz
MHz
VCLL
Clock Input level LOW (pin 10)
1
V
VCLH
Clock Input Level HIGH (pin 10)
4
V
Output Amplitude (pin 9)
4.5
V
PP
(*) FSEL pin has an internal 40K
pull down resistor A 4.332MHz QUARTZ must be used (**) A 8.664MHz QUARTZ must be used.
DEMODULATOR
f
O
Max Oscillator Deviation
F
SEL
= Open
+ 1.2
KHz
S
RDS
RDS Detection Sensitivity
1
mVrms
S
ARI
ARI Detection Sensitivity
3
mVrms
T
lock
RDS Lockup Time
100
ms
V
OH
Output HIGH Voltage
I
L
= 0.5mA; pins 12, 13, 14, 15
4
V
V
OL
Output LOW Voltage
I
L
= 0.5mA; pins 12, 13, 14, 15
1
V
f
RDS
Data Rate for RDS
RDCL pin
1187.5
Hz
t
D
RDDA Transition versus RDCL
(see figure 2)
4.3
sec
Note(1):
The phase non linearity is defined as:
Ph = | -2
f2 +
f1 +
f3 |
where
fx is the input-output phase difference at the frequency fx (x = 1,2,3)
TDA7330B
3/9
OUTPUT TIMING
The generated 1187.5Hz output clock (RDCL
line) is synchronized to the incoming data.
According to the internal PLL lock condition this
data change can results on the falling or on the
rising clock edge.
Whichever clock edge is used by the decoder (ris-
ing or falling edge) the data will remain valid for
416.7
sec after the clock transition.
Figure 2: RDS timing diagram
Figure 3: Test Circuit
Measure
f1 (KHz)
f2 (KHz)
f3 (KHz)
Ph max
A
56.5
57
57.5
<5
B
56
57
58
<7.5
C
55.5
57
58.5
<10
Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain.
ELECTRICAL CHARACTERISTICS (continued)
TDA7330B
4/9
APPLICATION SUGGESTION
A good DC decoupling between V
CC
and
GROUND is necessary: a 100nF ceramic ca-
pacitor, with low resistance and low inductance
at high frequency, directly connected on pin 16
(V
CC
)and 5 (GND) is recommended.
A small series inductance (100
H) or resistor
(27
) may be used for supply line filtering.
The Layout path pin2 - C2 - pin5 must be as
short as possible.
If the supply line, after the power on has a soft
and disturbed (spikes) slope, a capacitor of
100nF, between POR and V
CC
, is racom-
mended.
The various testing pins have no sense for the
customer.
Figure 4: P.C. board and component layout of fig. 3 (1:1 scale)
TDA7330B
5/9
Figure 5: Gain vs. Frequency
Figure 6: Group Delay vs. Frequency
TDA7330B
6/9
DIP20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.254
0.010
B
1.39
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
0.130
Z
1.34
0.053
OUTLINE AND
MECHANICAL DATA
TDA7330B
7/9
1
1
0
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
SO20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0
(min.)8
(max.)
OUTLINE AND
MECHANICAL DATA
TDA7330B
8/9
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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1999 STMicroelectronics Printed in Italy All Rights Reserved
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9/9
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