TDA7339
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
THREE STEREO INPUT
ONE RECORD OUTPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I
2
CBUS
DESCRIPTION
The TDA7339 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I
2
C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
This is preliminary information on a new product now in development. Details are subject to change without notice.
July 1999
1st VOL
1st VOL
TREBLE
TREBLE
SERIAL BUS DECODE & LATCHES
MIDDLE
BASS
2nd VOL
2nd VOL
MIDDLE
BASS
OUT L
SCL
ADDR
DIG.GND
OUT R
TREBLE(R)
M OUT(R)
M IN(R)
B OUT(R)
B IN(R)
V
S
BUS
M OUT(L)
TREBLE(L)
M IN(L)
B OUT(L)
B IN(L)
D94AU067C
IN1(L)
3 x
2.2
F
3 x
2.2
F
C7
5.6nF
C9
18nF
C10
22nF
C13
100nF
C14
100nF
R3
2.7K
R1
2.7K
C16
100nF
C15
100nF
C12
22nF
C11
18nF
C8
5.6nF
C
REF
10
F
R4
5.6K
R2
2.7K
SUPPLY
CREF
ANAL.GND
REC OUT(R)
REC OUT(L)
IN2(L)
MULTIPLEXER
MUTE
MUTE
SOFTMUTE
SDA
SOFTMUTE
CMUTE
IN3(L)
IN1(R)
IN2(R)
IN3(R)
2
4
5
27
25
24
1
16
28
21
26
23
22
20
19
17
11
15
18
13
14
12
10
9
7
6
3
8
C1
C2
C3
C4
C5
C6
C
SM
22nF
BLOCK DIAGRAM
ORDERING NUMBER: TDA7339
DIP28
1/12
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
-40 to 85
C
T
stg
Storage Temperature Range
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-pins
65
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.08
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
100
dB
1st and 2nd Volume Control 1dB step
-47
0
dB
Bass, Middle and Treble Control 1dB step
-14
+14
dB
Mute Attenuation
100
dB
M IN L
M OUT L
REC OUT L
B IN L
B OUT L
OUT L
CMUTE
SDA
SCL
1
3
2
4
5
6
7
8
9
DIG GND
AGND
OUT R
B OUT R
ADDR
B IN R
REC OUT R
M OUT R
M IN R
23
22
21
20
19
17
18
16
15
D95AU217A
10
11
12
13
14
28
27
26
25
24
VS
IN1L
TREBLE L
IN2L
IN3L
IN3R
IN2R
TREBLE R
IN1R
CREF
PIN CONNECTION
TDA7339
2/12
ELECTRICAL CHARACTERISTICS (V
S
= 9V; R
L
= 10K
; f = 1KHz; all control = flat (G = 0); T
amb
=
25
C Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INPUTS
R
in
Input Resistance
35
50
65
K
1st VOLUME CONTROL
C
RANGE
Control Range
45
47
49
dB
A
VMAX
Maximum Attenuation
45
47
49
dB
A
step
Step Resolution
0.5
1.0
1.5
dB
E
A
Attenuation Set Error
G = 0 to -24dB
-1.0
1.0
dB
G = -24 to -47dB
-1.5
1.5
dB
E
t
Tracking Error
G = 0 to -24dB
1
dB
G = 24 to -47dB
2
dB
A
mute
Mute Attenuation
80
100
dB
V
DC
DC Steps
Adiacent Attenuation Steps
0
3
mV
From 0dB to A
VMAX
0.5
5
mV
2nd VOLUME CONTROL
C
RANGE
Control Range
45
47
49
dB
A
VMAX
Maximum Attenuation
45
47
49
dB
A
step
Step Resolution
0.5
1.0
1.5
dB
E
A
Attenuation Set Error
G = 0 to -24dB
-1.0
1.0
dB
G = -24 to -47dB
-1.5
1.5
dB
E
t
Tracking Error
G = 0 to -24dB
1
dB
G = 24 to -47dB
2
dB
A
MUTE
Mute Attenuation
80
100
dB
V
DC
DC Steps
Adiacent Attenuation Steps
0
3
mV
From 0dB to A
VMAX
0.5
5
mV
BASS
R
b
Internal Feedback Resistance
32
44
56
K
C
RANGE
Control Range
11.5
14
16
dB
A
step
Step Resolution
0.5
1
1.5
dB
MIDDLE
R
b
Internal Feedback Resistance
18
25
32
K
C
RANGE
Control Range
11.5
14
16
dB
A
step
Step Resolution
0.5
1
1.5
dB
TREBLE
C
RANGE
Control Range
13
14
15
dB
A
step
Step Resolution
0.5
1
1.5
dB
SUPPLY
V
S
Supply Voltage (note1)
6
9
10.5
V
I
S
Supply Current
4
7
10
mA
SVR
Ripple Rejection
60
90
dB
SOFT MUTE
A
MUTE
Mute Attenuation
45
60
dB
t
D
Delay Time
C
SM
= 22
F; 0 to 20dB; I = I
MAX
0.8
1.5
2
ms
C
SM
= 22
F; 0 to 20dB; I = I
MIN
15
25
45
ms
TDA7339
3/12
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUDIO OUTPUT
V
clip
Clipping Level
d = 0.3%
2
2.6
Vrms
R
Ol
Output Load Resistance
2
K
R
O
Output Impedance
100
180
300
V
DC
DC Voltage Level
3.8
V
GENERAL
e
NO
Output Noise
All Gains 0dB (B = 20 to 20kHz flat)
5
15
V
E
t
Total Tracking Error
A
V
= 0 to -24dB
0
1
dB
A
V
= -24 to -47dB
0
2
dB
S/N
Signal to Noise Ratio
All Gains = 0dB; V
O
= 1V
rms
106
dB
S
C
Channel Separation
80
100
dB
d
Distortion
A
V
= 0; V
in
= 1V
rms
0.01
0.08
%
BUS INPUTS
V
il
Input Low Voltage
1
V
V
ih
Input High Voltage
3
V
I
in
Input Current
V
in
= 0.4V
-5
5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
0.8
V
NOTE 1: the device is functionally good at Vs = 5V. A step down, on V
S
, to 4V does't reset the device.
TDA7339
4/12
Timing Diagram of I
2
CBUS
Data Validity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Acknowledge on the I
2
CBUS
TDA7339
5/12
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