TDA7342
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- TWO STEREO AND ONE MONO INPUTS
- ONE QUASI DIFFERENTIAL INPUT
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
FULLY
PROGRAMMABLE
LOUDNESS
FUNCTION
VOLUME CONTROL IN 0.3dB STEPS IN-
CLUDING GAIN UP TO 20dB
ZERO CROSSING MUTE, SOFT MUTE AND
DIRECT MUTE
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1.25dB STEPS FOR
BALANCE AND FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I
2
CBUS
DESCRIPTION
The audioprocessor TDA7342 is an upgrade of
the TDA731X audioprocessor family.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are imple-
mented.
The soft Mute function can be activated in two
ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 21 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
November 1999
ORDERING NUMBER: TDA7342
TQFP 32
1/14
13
12
10
11
L1
L2
L3
L1
L2
L3
M
7
8
5
R1
R2
R3
R1
R2
R3
M
M
CD
GND
6
INPUT
SELECTOR
+
GAIN
LEFT
INPUTS
CD
RIGHT
INPUTS
SUPPLY
30
31
29
ZERO
CROSS
+
MUTE
SOFT
MUTE
OUT(L)
IN(L)
16
15
LOUD+
VOL
ZERO
CROSS
+
MUTE
LOUD+
VOL
BASS
BASS
LOUD(L)
9
TREBLE
TREBLE
10
FC
9
31
4
CSM
OUT(R)
CREF
IN(R)
24
LOUD(R)
BOUT(L)
BIN(L)
18
17
BOUT(R)
BIN(R)
20
19
1
TREBLE(R)
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
TREBLE(L)
32
23
28
27
26
24
25
22
OUT
LEFT
FRONT
OUT
LEFT
REAR
SCL
SDA
DIGGND
OUT
RIGHT
FRONT
OUT
RIGHT
REAR
D94AU104B
BUS
SERIAL
BUS
DECODER
+
LATCHES
MONO
INPUT
C1
C2
C6
C3
C7
C8
C4
C5
C10
C12
47nF
CSM
47nF
C14
100nF
C15
100nF
4.7K
C16
2.7nF
C19
2.7nF
C18
100nF
C17
100nF
C13
47nF
C11
R2
4.7K
21
SM
V
S
R1
BLOCK DIAGRAM
TDA7342
2/14
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
-40 to 85
C
T
stg
Storage Temperature Range
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-pins
150
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10.2
V
V
CL
Max. input signal handling
2.1
2.6
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.08
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
100
dB
Volume Control 0.3dB step
-59.7
20
dB
Treble Control 2dB step
-14
+14
dB
Bass Control 2dB step
-10
+18
dB
Fader and Balance Control 1.25dB step
-38.75
0
dB
Input Gain 3.75dB step
0
11.25
dB
Mute Attenuation
100
dB
1
2
3
5
6
4
7
8
11 12 13 14 15 16
32
30
31
29 28 27 26 25
19
18
17
24
23
22
20
21
IN R2
IN R3
LOUD R
IN R
TR R
OUT R
IN R1
MONO
LOUD
L
IN
L3
CD
GND
IN
L2
IN
L1
CSM
IN
L
OUT
L
TR
L
V
S
GND
SM
CREF
SCL
SDA
DIG
GND
BIN R
BOUT L
BIN L
OUT
LF
OUT RF
OUT LR
BOUT R
OUT RR
D94AU105A
9 10
PIN CONNECTION
TDA7342
3/14
ELECTRICAL CHARACTERISTICS (V
S
= 9V; R
L
= 10K
; R
g
= 50
; T
amb
= 25
C; all gains = 0dB;
f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INPUT SELECTOR
R
I
Input Resistance
70
100
130
K
V
CL
Clipping Level
d
0.3%
2.1
2.6
V
RMS
S
I
Input Separation
80
100
dB
R
L
Output Load Resistance
2
K
G
I MIN
Minimum Input Gain
-0.75
0
0.75
dB
G
I MAX
Maximum Input Gain
10.25
11.25
12.25
dB
G
step
Step Resolution
2.75
3.75
4.75
dB
e
N
Input Noise
20Hz to 20 KHz unweighted
2.3
V
V
DC
DC Steps
Adiacent Gain Steps
1.5
10
mV
G
IIN
to G
IMAX
3
mV
DIFFERENTIAL INPUT ( IN 3)
R
I
Input Resistance
Input selector BIT D6 = 0 (0dB)
10
15
20
K
Input selector BIT D6 = 1(-6dB)
14
20
30
K
CMRR
Common Mode Rejection Ratio
V
CM
= 1V
RMS
;
f =1KHz
48
75
dB
f = 10KHz
45
70
dB
d
Distortion
V
I
= 1V
RMS
0.01
0.08
%
e
IN
Input Noise
20Hz to 20KHz; Flat; D6 = 0
5
V
G
DIFF
Differential Gain
D6 = 0
-1
0
1
dB
D6 = 1
-7
-6
-5
dB
VOLUME CONTROL
R
I
Input Resistance
35
50
K
G
MAX
Maximum Gain
18.75
20
21.25
dB
A
MAX
Maximum Attenuation
57.7
59.7
62.7
dB
A
STEPC
Step Resolution Coarse Atten.
0.5
1.25
2.0
dB
A
STEPF
Step Resolution Fine Attenuation
0.11
0.31
0.51
dB
E
A
Attenuation Set Error
G = 20 to -20dB
-1.25
0
1.25
dB
G = -20 to -58dB
-3
2
dB
E
t
Tracking Error
2
dB
V
DC
DC Steps
Adiacent Attenuation Steps
-3
0
3
mV
From 0dB to A
MAX
0.5
5
mV
LOUDNESS CONTROL
R
I
Internal Resistor
Loud = On
35
50
65
K
A
MAX
Maximum Attenuation
17.5
18.75
20.0
dB
A
step
Step Resolution
0.5
1.25
2.0
dB
TDA7342
4/14
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ZERO CROSSING MUTE
V
TH
Zero Crossing Threshold
(note 1)
WIN = 11
20
mV
WIN = 10
40
mV
WIN = 01
80
mV
WIN = 00
160
mV
A
MUTE
Mute Attenuation
80
100
dB
V
DC
DC Step
0dB to Mute
0
3
mV
SOFT MUTE
A
MUTE
Mute Attenuation
45
60
dB
T
DON
ON Delay Time
C
CSM
= 22nF; 0 to -20dB; I = I
MAX
0.7
1
1.7
ms
C
CSM
= 22nF; 0 to -20dB; I = I
MIN
20
35
55
ms
T
DOFF
OFF Current
V
CSM
= 0V; I = I
MAX
25
50
75
A
V
CSM
= 0V; I = I
MIN
1
A
V
THSM
Soft Mute Threshold
1.5
2.5
3.5
V
R
INT
Pullup Resistor (pin 21)
(note 2)
35
50
65
K
V
SMH
(pin 21) Level High
3.5
V
V
SML
(pin 21) Level Low
Soft Mute Active
1
V
BASS CONTROL
B
BOOST
Max Bass Boost
15
18
20
dB
B
CUT
Max Bass Cut
-8.5
-10
-11.5
dB
A
step
Step Resolution
1
2
3
dB
R
g
Internal Feedback Resistance
45
65
85
K
TREBLE CONTROL
C
RANGE
Control Range
13
14
15
dB
A
step
Step Resolution
1
2
3
dB
SPEAKER ATTENUATORS
C
RANGE
Control Range
35
37.5
40
dB
A
step
Step Resolution
0.5
1.25
2.00
dB
A
MUTE
Output Mute Attenuation
Data Word = XXX11111
80
100
dB
E
A
Attenuation Set Error
1.25
dB
V
DC
DC Steps
Adjacent Attenuation Steps
0
3
mV
AUDIO OUTPUT
V
clip
Clipping Level
d = 0.3%
2.1
2.6
Vrms
R
L
Output Load Resistance
2
K
R
O
Output Impedance
30
100
V
DC
DC Voltage Level
3.5
3.8
4.1
V
TDA7342
5/14
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
GENERAL
V
CC
Supply Voltage
6
9
10.2
V
I
CC
Supply Current
5
10
15
mA
PSRR
Power Supply Rejection Ratio
f = 1KHz
60
80
dB
B = 20 to 20kHz "A" weighted
65
dB
e
NO
Output Noise
Output Muted (B = 20 to 20kHz flat)
2.5
V
All Gains 0dB (B = 20 to 20kHz flat)
5
15
V
E
t
Total Tracking Error
A
V
= 0 to -20dB
0
1
dB
A
V
= -20 to -60dB
0
2
dB
S/N
Signal to Noise Ratio
All Gains = 0dB; V
O
= 1V
rms
106
dB
S
C
Channel Separation
80
100
dB
d
Distortion
V
IN
=1V
0.01
0.08
%
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
lN
Input High Voltage
3
V
I
lN
Input Current
VIN = 0.4V
-5
5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
0.8
V
Note 1: WIN represents the MUTE programming bit pair D
6
, D
5
for the zero crossing window threshold
Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
TDA7342
6/14
Figure 4: Timing Diagram of I
2
CBUS
Figure 3: Data Validity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7342 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5: Acknowledge on the I
2
CBUS
TDA7342
7/14
MSB
LSB
FUNCTION
X
X
X
I
A3
A2
A1
A0
0
0
0
0
Input Selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker Attenuator LF
0
1
0
1
Speaker Attenuator LR
0
1
1
0
Speaker Attenuator RF
0
1
1
1
Speaker Attenuator RR
1
0
0
0
Mute
AUTO INCREMENT
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)
TRANSMITTED DATA
Send Mode
MSB
LSB
X
X
X
X
X
SM
ZM
X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
1
0
0
R/W
ACK
X
X
X
I
A3 A2 A1 A0
ACK
DATA
ACK
P
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
TDA7342
8/14
DATA BYTE SPECIFICATION
X = not relevant; set to "1" during testing
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
IN 3 (differential input)
0
1
0
0
1
IN 2
0
1
0
1
0
IN 1
0
1
0
1
1
AM mono
0
1
1
0
0
not used
0
1
1
0
1
not used
0
1
1
1
0
not allowed
0
1
1
1
1
not allowed
0
1
0
0
11.25dB gain
0
1
0
1
7.5dB gain
0
1
1
0
3.75dB gain
0
1
1
1
0dB gain
0
0dB differential input gain ( IN3 )
1
-6dB differential input gain ( IN3 )
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Input Selector
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0dB
X
X
X
0
0
0
0
1
-1.25dB
X
X
X
0
0
0
1
0
-2.5dB
X
X
X
0
0
0
1
1
-3.75dB
X
X
X
0
0
1
0
0
-5dB
X
X
X
0
0
1
0
1
-6.25dB
X
X
X
0
0
1
1
0
-7.5dB
X
X
X
0
0
1
1
1
-8.75dB
X
X
X
0
1
0
0
0
-10dB
X
X
X
0
1
0
0
1
-11.25dB
X
X
X
0
1
0
1
0
-12.5dB
X
X
X
0
1
0
1
1
-13.75dB
X
X
X
0
1
1
0
0
-15dB
X
X
X
0
1
1
0
1
-16.25dB
X
X
X
0
1
1
1
0
-17.5dB
X
X
X
0
1
1
1
1
-18.75dB
X
X
X
1
D3
D2
D1
D0
Loudness OFF (1)
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
NOTE 1:
If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat fre quency response. D0 to D3 determine the
attenuation level.
Loudness
TDA7342
9/14
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
1
Soft Mute On
0
1
Soft Mute with fast slope (I = I
MAX
)
1
1
Soft Mute with slow slope (I = I
MIN
)
1
Direct Mute
0
1
Zero Crossing Mute On
0
0
Zero Crossing Mute Off (delayed until next zero
crossing)
1
Zero Crossing Mute and Pause Detector Reset
0
0
0
160mV ZC Window Threshold (WIN = 00)
0
1
0
80mV ZC Window Threshold (WIN = 01)
1
0
0
40mV ZC Window Threshold (WIN = 10)
1
1
0
20mV ZC Window Threshold (WIN = 11)
0
Nonsymmetrical Bass Cut (note 4)
1
Symmetrical Bass Cut
An additional direct mute function is included in the Speaker Attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Mute
MSB
LSB
SPEAKER ATTENUATOR LF, LR, RF, RR
D7
D6
D5
D4
D3
D2
D1
D0
1.25dB step
X
X
X
0
0
0
0dB
X
X
X
0
0
1
-1.25dB
X
X
X
0
1
0
-2.5dB
X
X
X
0
1
1
-3.75dB
X
X
X
1
0
0
-5dB
X
X
X
1
0
1
-6.25dB
X
X
X
1
1
0
-7.5dB
X
X
X
1
1
1
-8.75dB
10dB step
X
X
X
0
0
0dB
X
X
X
0
1
-10dB
X
X
X
1
0
-20dB
X
X
X
1
1
-30dB
X
X
X
1
1
1
1
Speaker Mute
For example an attenuationof 25dB on a selected output is given by: X X X1 0 1 0 0
Speaker Attenuators
TDA7342
10/14
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
TREBLE STEP
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
BASS STEPS
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
0
0
0
1
146B
0
0
0
0
18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
Bass Treble
TDA7342
11/14
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0.31dB Fine Attenuation Steps
0
0
0dB
0
1
-0.31dB
1
0
-0.62dB
1
1
-0.94dB
1.25dB Coarse Attenuation Steps
0
0
0
0dB
0
0
1
-1.25dB
0
1
0
-2.5dB
0
1
1
-3.75dB
1
0
0
-5dB
1
0
1
-6.25dB
1
1
0
-7.5dB
1
1
1
-8.75dB
10dB Gain / Attenuation Steps
0
0
0
20dB
0
0
1
10dB
0
1
0
0dB
0
1
1
-10dB
1
0
0
-20dB
1
0
1
-30dB
1
1
0
-40dB
1
1
1
-50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1
Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
Volume
TDA7342
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TQFP32
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.60
0.063
A1
0.05
0.15
0.002
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
B
0.30
0.37
0.45
0.012
0.015
0.018
C
0.09
0.20
0.004
0.008
D
9.00
0.354
D1
7.00
0.276
D3
5.60
0.220
e
0.80
0.031
E
9.00
0.354
E1
7.00
0.276
E3
5.60
0.220
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
K
0
(min.), 7
(max.)
A
A2
A1
B
Seatin g Plane
C
8
9
16
17
24
25
32
E3
D3
E1
E
D1
D
e
1
K
B
TQFP32
L
L1
0.10 mm
.0 04
OUTLINE AND
MECHANICAL DATA
TDA7342
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Purchase of I
2
C Components of STMicrolectronics, conveys a license under the Philips I
2
C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C
Standard Specifications as defined by Philips.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parti es which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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