Document Outline
- Figure 1. Package
- Table 1. Order Codes
- 1 FEATURES
- 2 DESCRIPTION
- Figure 2. Block Diagram
- Figure 3. PIN CONNECTION
- Table 2. Absolute Maximum Ratings
- Table 3. Thermal Data
- Table 4. QUICK REFERENCE DATA
- Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25 C, VS = 9V, RL= 10KW, RG ...
- Figure 4. TEST CIRCUIT
- 3 APPLICATION SUGGESTIONS
- 3.1 Bass, Middle Stages
- Figure 5.
- 3.2 Treble Stage
- 3.3 CREF
- Figure 6. THD vs. frequency
- Figure 7. THD vs. RLOAD
- Figure 8. Channel separation vs. frequency
- Figure 9. Bass response
- Figure 10. Treble response
- Figure 11. Middle response
- Figure 12. Typical tone response
- 4 I2C BUS INTERFACE
- 4.1 Data Validity
- 4.2 Start and Stop Conditions
- 4.3 Byte Format
- 4.4 Acknowledge
- 4.5 Transmission without Acknowledge
- Figure 13. Data Validity on the I2CBUS
- Figure 14.
- Figure 15.
- 5 SOFTWARE SPECIFICATION
- 5.1 Interface Protocol
- Figure 16.
- 6 EXAMPLES
- 6.1 No Incremental Bus
- Figure 17.
- 6.2 Incremental Bus
- Figure 18.
- Table 6. POWER ON RESET CONDITION
- 7 Data bytes
- Figure 19. FUNCTION SELECTION: First byte (subaddress)
- Table 7. INPUT SELECTION
- Table 8. INPUT GAIN SELECTION
- Table 9. VOLUME SELECTION
- Table 10. BASS SELECTION
- Table 11. MIDDLE SELECTION
- Table 12. TREBLE SELECTION
- Table 13. SPEAKER ATTENUATE SELECTION
- Figure 20. PINS: 2
- Figure 21. PINS: 5, 6
- Figure 22. PINS 7, 8, 9, 10, 11, 12, 13, 14
- Figure 23. PINS 15, 17
- Figure 24. PINS 16, 18
- Figure 25. PINS 20, 25
- Figure 26. PINS 19,26
- Figure 27. PINS 21, 23
- Figure 28. PINS 22, 24
- Figure 29. PINS 27, 28
- Figure 30. PIN 30
- Figure 31. PIN 1
- Figure 32. SDIP30 Mechanical Data & Package Dimensions
- Table 14. Revision History
1/19
TDA7439
June 2004
1
FEATURES
INPUT MULTIPLEXER
4 STEREO INPUTS
SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
2
DESCRIPTION
The TDA7439 is a volume tone (bass, middle and
treble) balance (Left/Right) processor for quality
audio applications in car-radio and Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR
Figure 2. Block Diagram
0/30dB
2dB STEP
MUXOUTL
INL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
MIDDLE
MIDDLE
MUXOUTR
INR
TREBLE(R)
BOUT(L)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIG_GND
ROUT
D95AU342B
I
2
CBUS DECODER + LATCHES
100K
100K
100K
100K
G
L-IN1
L-IN2
L-IN3
L-IN4
100K
100K
100K
100K
R-IN1
R-IN2
R-IN3
R-IN4
G
INPUT MULTIPLEXER
+ GAIN
MOUT(L)
BASS
BIN(L)
BASS
SPKR ATT
RIGHT
MIN(R) MOUT(R)
BOUT(R)
BIN(R)
SUPPLY
CREF
AGND
V
S
MIN(L)
6
11
12
13
14
10
9
8
7
30
1
29
5
3
4
17
18
28
19
20
21
22
2
15
16
27
26
25
23
24
R
M
R
B
R
M
R
B
V
REF
REV. 10
Figure 1. Package
Table 1. Order Codes
Part Number
Package
TDA7439
SDIP30
SDIP30
TDA7439
2/19
Figure 3. PIN CONNECTION
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Table 4. QUICK REFERENCE DATA
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
0 to 70
C
T
stg
Storage Temperature Range
-55 to 150
C
Symbol
Parameter
Value
Unit
R
th j-pin
Thermal Resistance Junction-pins
85
C/W
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10.2
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.1
%
S/N
Signal to Noise Ratio V
out
= 1Vrms (mode = OFF)
106
dB
S
C
Channel Separation f = 1KHz
90
dB
Input Gain in (2dB step)
0
30
dB
Volume Control (1dB step)
-47
0
dB
Treble Control (2dB step)
-14
+14
dB
Middle Control (2dB step)
-14
+14
dB
Bass Control (2dB step)
-14
+14
dB
Balance Control 1dB step
-79
0
dB
Mute Attenuation
100
dB
LOUT
R-IN4
R-IN3
R-IN2
R-IN1
L-IN2
L-IN1
L-IN3
L-IN4
1
3
2
4
5
6
7
8
9
MUXOUTR
INR
MIN(R)
BIN(R)
MOUT(R)
BOUT(R)
BIN(L)
BOUT(L)
MOUT(L)
25
24
23
22
21
19
20
18
17
D95AU340A
10
11
12
13
14
30
29
28
27
26
DIG_GND
CREF
V
S
AGND
ROUT
MIN(L)
TREBLE(L)
TREBLE(R)
SCL
SDA
MUXOUTL
INL
16
15
3/19
TDA7439
Table 5. Electrical Characteristcs (refer to the test circuit T
amb
= 25C, V
S
= 9V, R
L
= 10K
, R
G
= 600
,
all controls flat (G = 0dB), unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
6
9
10.2
V
I
S
Supply Current
4
7
10
mA
SVR
Ripple Rejection
60
90
dB
INPUT STAGE
R
IN
Input Resistance
70
100
130
K
V
CL
Clipping Level
THD = 0.3%
2
2.5
Vrms
S
IN
Input Separation
The selected input is grounded
through a 2.2
capacitor
80
100
dB
G
inmin
Minimum Input Gain
-1
0
1
dB
G
inman
Maximum Input Gain
29
30
31
dB
G
step
Step Resolution
1.5
2
2.5
dB
VOLUME CONTROL
R
i
Input Resistance
20
33
50
K
C
RANGE
Control Range
45
47
49
dB
A
VMAX
Max. Attenuation
45
47
49
dB
A
STEP
Step Resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
A
V
= 0 to -24dB
-1.0
0
1.0
dB
A
V
= -24 to -47dB
-1.5
0
1.5
dB
E
Tracking Error
A
V
= 0 to -24dB
0
1
dB
A
V
= -24 to -47dB
0
2
dB
V
DC
DC Step
adjacent attenuation steps
from 0dB to
A
V
max
0
0.5
3
mV
mV
A
mute
Mute Attenuation
80
100
dB
BASS CONTROL (1)
Gb
Control Range
Max. Boost/cut
12.0
14.0
16.0
dB
B
STEP
Step Resolution
1
2
3
dB
R
B
Internal Feedback Resistance
33
44
55
K
TREBLE CONTROL (1)
Gt
Control Range
Max. Boost/cut
13.0
14.0
15.0
dB
T
STEP
Step Resolution
1
2
3
dB
MIDDLE CONTROL (1)
Gm
Control Range
Max. Boost/cut
12.0
14.0
16.0
dB
M
STEP
Step Resolution
1
2
3
dB
R
M
Internal Feedback Resistance
18.75
25
31.25
K
TDA7439
4/19
Notes: 1. The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does't reset the device.
2. BASS, MIDDLE and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
SPEAKER ATTENUATORS
C
RANGE
Control Range
70
76
82
dB
S
STEP
Step Resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
A
V
= 0 to -20dB
-1.5
0
1.5
dB
A
V
= -20 to -56dB
-2
0
2
dB
V
DC
DC Step
adjacent attenuation steps
0
3
mV
A
mute
Mute Attenuation
80
100
dB
AUDIO OUTPUTS
V
CLIP
Clipping Level
d = 0.3%
2.1
2.6
V
RMS
R
L
Output Load Resistance
2
K
R
O
Output Impedance
10
40
70
V
DC
DC Voltage Level
3.5
3.8
4.1
V
GENERAL
E
NO
Output Noise
All gains = 0dB;
BW = 20Hz to 20KHz flat
5
15
V
E
t
Total Tracking Error
A
V
= 0 to -24dB
0
1
dB
A
V
= -24 to -47dB
0
2
dB
S/N
Signal to Noise Ratio
All gains 0dB; V
O
= 1V
RMS
;
95
106
dB
S
C
Channel Separation Left/Right
80
100
dB
d
Distortion
A
V
= 0; V
I
= 1V
RMS
;
0.01
0.08
%
BUS INPUT
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
I
IN
Input Current
V
IN
= 0.4V
-5
0
5
A
V
O
Output Voltage SDA Acknowledge
I
O
= 1.6mA
0.4
0.8
V
Table 5. Electrical Characteristcs (continued)
5/19
TDA7439
Figure 4. TEST CIRCUIT
3
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free
from any noisy acoustical effect. The TDA7439 audioprocessor provides 3 bands tones control.
3.1 Bass, Middle Stages
The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44K
typical.
The Middle cell has an internal resistor Ri = 25K
typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT
pins.
Figure 5.
0/30dB
2dB STEP
MUXOUTL
INL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
MIDDLE
MIDDLE
MUXOUTR
INR
TREBLE(R)
BOUT(L)
MIN(L)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIGGND
ROUT
D95AU339B
I
2
CBUS DECODER + LATCHES
5.6nF
2.2
F
100K
100K
100K
100K
G
L-IN1
L-IN2
L-IN3
L-IN4
0.47
F
0.47
F
0.47
F
0.47
F
100K
100K
100K
100K
R-IN1
R-IN2
R-IN3
R-IN4
0.47
F
0.47
F
0.47
F
0.47
F
G
INPUT MULTIPLEXER
+ GAIN
MOUT(L)
BASS
BIN(L)
18nF
22nF
100nF
100nF
2.7K
5.6K
BASS
SPKR ATT
RIGHT
MIN(R)
MOUT(R)
BOUT(R)
BIN(R)
5.6nF
18nF
22nF
100nF
100nF
2.7K
5.6K
SUPPLY
10
F
CREF
AGND
V
S
R
M
R
B
R
M
R
B
6
11
12
13
14
10
9
8
7
30
1
29
5
3
4
17
18
28
19
20
21
22
2
15
16
27
26
25
23
24
V
REF
2.2
F
Ri internal
C
2
OUT
IN
C
1
R
2
D95AU313
TDA7439
6/19
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K
typical) and
an external capacitor connected between treble pins and ground Typical responses are reported in Figg.
10 to 13.
3.3 CREF
The suggested 10
F reference capacitor (CREF) value can be reduced to 4.7
F if the application requires
faster power ON.
F
C
1
2
R1 R2 C 1 C2
-----------------------------------------------------------------
=
A
V
R2C 2
R2C1
RiC1
+
+
R2 C1
R2C2
+
------------------------------------------------------------
=
Q
R 1 R2 C1 C2
R 2C1
R2C2
+
--------------------------------------------------
=
C1
A
V
1
2
Fc Ri Q
------------------------------------------
C2
Q
2
C1
A
V
1
Q
2
------------------------------
=
=
R2
A
V
1
Q
2
2
C1 Fc
A
V
1
(
)
Q
----------------------------------------------------------------------
=
Figure 6. THD vs. frequency
Figure 7. THD vs. RLOAD
7/19
TDA7439
Figure 8. Channel separation vs. frequency
Figure 9. Bass response
Figure 10. Treble response
Figure 11. Middle response
Figure 12. Typical tone response
TDA7439
8/19
4
I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7439 and vice versa takes place through the 2 wires
I
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 13, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.14 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (
P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
15). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission:
simply it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 13. Data Validity on the I
2
CBUS
Figure 14.
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
9/19
TDA7439
Figure 15.
5
SOFTWARE SPECIFICATION
5.1 Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7439 address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
Figure 16.
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus
The TDA7439 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incre-
mental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 17.
SCL
1
MSB
2
3
7
8
9
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU420
X
DATA
SUBADDRESS
DATA 1 to DATA n
X
X
B
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU421
X
D3
SUBADDRESS
DATA
X
X
0
D2 D1 D0
TDA7439
10/19
6.2 Incremental Bus
The TDA7439 receive a start conditions, the correct chip address, a subaddress with the B = 1 incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
Figure 18.
Table 6. POWER ON RESET CONDITION
7
DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Figure 19. FUNCTION SELECTION: First byte (subaddress)
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON'T CARE
INPUT SELECTION
IN2
INPUT GAIN
28dB
VOLUME
MUTE
BASS
0dB
MIDDLE
2dB
TREBLE
2dB
SPEAKER
MUTE
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
VOLUME
X
X
X
B
0
0
1
1
BASS
X
X
X
B
0
1
0
0
MIDDLE
X
X
X
B
0
1
0
1
TREBLE
X
X
X
B
0
1
1
0
SPEAKER ATTENUATE "R"
X
X
X
B
0
1
1
1
SPEAKER ATTENUATE "L"
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU422
X
D3
SUBADDRESS
DATA 1 to DATA n
X
X
1
D2 D1 D0
11/19
TDA7439
Table 7. INPUT SELECTION
Table 8. INPUT GAIN SELECTION
GAIN = 0 to 30dB
MSB
LSB
INPUT MULTIPLEXER
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
IN4
X
X
X
X
X
X
0
1
IN3
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
MSB
LSB
INPUT GAIN
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
0dB
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
20dB
1
0
1
1
22dB
1
1
0
0
24dB
1
1
0
1
26dB
1
1
1
0
28dB
1
1
1
1
30dB
TDA7439
12/19
Table 9. VOLUME SELECTION
VOLUME = 0 to 47dB/MUTE
Table 10. BASS SELECTION
MSB
LSB
VOLUME
D7
D6
D5
D4
D3
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
X
1
1
1
X
X
X
MUTE
MSB
LSB
BASS
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
13/19
TDA7439
Table 11. MIDDLE SELECTION
Table 12. TREBLE SELECTION
MSB
LSB
MIDDLE
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
MSB
LSB
TREBLE
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
TDA7439
14/19
Table 13. SPEAKER ATTENUATE SELECTION
SPEAKER ATTENUATION = 0 to -79dB/MUTE
MSB
LSB
SPEAKER ATTENUATION
D7
D6
D5
D4
D3
D2
D1
D0
1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
1
1
1
X
X
X
MUTE
15/19
TDA7439
Figure 20. PINS: 2
Figure 21. PINS: 5, 6
Figure 22. PINS 7, 8, 9, 10, 11, 12, 13, 14
Figure 23. PINS 15, 17
Figure 24. PINS 16, 18
Figure 25. PINS 20, 25
20K
20K
CREF
V
S
D96AU430
V
S
V
S
D96AU434
20
A
ROUT
24
LOUT
20
A
V
S
100K
V
REF
D96AU425
IN
V
S
D96AU426
20
A
V
S
MIXOUT
GND
20
A
V
S
33K
D96AU427
INL
INR
V
REF
25K
V
S
MOUT(R)
D96AU431
20
A
MOUT(L)
TDA7439
16/19
Figure 26. PINS 19,26
Figure 27. PINS 21, 23
Figure 28. PINS 22, 24
Figure 29. PINS 27, 28
Figure 30. PIN 30
Figure 31. PIN 1
25K
V
S
MOUT(R)
D96AU431
20
A
MOUT(L)
44K
V
S
BIN(R)
D96AU428
20
A
BIN(L)
44K
V
S
BOUT(R)
D96AU429
20
A
BOUT(L)
50K
V
S
TREBLE(R)
D96AU433
20
A
TREBLE(L)
D96AU424
20
A
SCL
D96AU423
20
A
SDA
17/19
TDA7439
Figure 32. SDIP30 Mechanical Data & Package Dimensions
SDIP30 (0.400")
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
5.08
0.20
A1
0.51
0.020
A2
3.05
3.81
4.57
0.12
0.15
0.18
B
0.36
0.46
0.56
0.014
0.018
0.022
B1
0.76
0.99
1.40
0.030
0.039
0.055
C
0.20
0.25
0.36
0.008
0.01
0.014
D
27.43
27.94
28.45
1.08
1.10
1.12
E
10.16
10.41
11.05
0.400
0.410
0.435
E1
8.38
8.64
9.40
0.330
0.340
0.370
e
1.778
0.070
e1
10.16
0.400
L
2.54
3.30
3.81
0.10
0.13
0.15
M
0
(min.), 15
(max.)
S
0.31
0.012
OUTLINE AND
MECHANICAL DATA
TDA7439
18/19
Table 14. Revision History
Date
Revision
Description of Changes
January 2004
9
First Issue in EDOCS DMS
June 2004
10
Changed the Style-sheet in compliance to the new "Corporate Technical
Pubblications Design Guide"
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
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19/19
TDA7439
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