TDA7467
AUDIO MATRIX WITH SRS EFFECTS
1 STEREO INPUT
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
- MUTE FUNCTION
MONO MODE (SRS 3D MONO)
STEREO MODE (SRS 3D STEREO)
SPACE AND CENTER ATTENUATORS ARE
AVAILABLE
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS (I
2
C BUS)
DESCRIPTION
The TDA7467 is a SRS (Sound Retrieval System)
audio matrix. It reproduces SRS sound process-
ing stereo and mono sources both.
The SRS sound is guaranteed by external com-
ponents and it is not affected by internal process
spreads.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers according to the SRS labs specifica-
tion.
Control of all the functions is accomplished by serial
bus. Thanks to the used BIPOLAR/CMOS/DMOS
technology, Low Distortion, Low Noise and DC
stepping are obtained.
May 1997
DIP28
The Device incorporates the SRS
(Sound Retrieval System) under
licence from SRS Labs, Inc.
ORDERING NUMBER: TDA7467
SO28
ORDERING NUMBER: TDA7467D
ADDR
SDA
AGND
PS1
PS2
PS4
PS3
PS5
PS6
1
3
2
4
5
6
7
8
9
NETW1
NETW2
VREFOUT
HP2
HP1
HP3
V
S
HP4
HP5
23
22
21
20
19
17
18
16
15
D96AU507
10
11
12
13
14
28
27
26
25
24
LOUT
RIN
LIN
DIG_GND
SCL
HP6
LP1
LP2
CREF
ROUT
PIN CONNECTION (Top view)
1/11
L-IN
MONO
0.15
F
SUPPLY
V
S
AGND
CREF
1
F
HP1
0.1
F
D96AU506
I2
C
BUS
DECODER
+
LATCHES
SCL
SDA
ADDR
R-OUT
L-OUT
22
F
-
PS1
PHASE
SHIFTER
2
SRS
PS2
PS3
100nF
PS4
3
21
8
2
7
18
20
5
7
6
2
0.15
F
31.5dB
control
R-IN
31.5dB
control
0.47
F
NETW2
NETW1
2
15
16
SRS
FIX
MONO
50K
50K
CENTER
SPACE
1K
4.42K
0.47
F
1.5K
32.4K
130K
47.5K
4.7nF
3.74K
VREFOUT
17
V
REF
FIX
+
15nF
PS5
2.2nF
PS6
27nF
4.7nF
0.47nF
PHASE
SHIFTER
1
+
-
MIX
MIX
+
HPF1
19
HP2
HP3
1
F
HP4
0.1
F
22
24
HPF2
23
HP5
HP6
LPF1
1
F
0.1
F
LP1
LP2
+
SRS
+
+
+
MONO
12
13
14
9
1
0
1
1
2
5
2
6
1
DIG_GND
4
BLOCK DIAGRAM
TDA7467
2/11
THERMAL DATA
Symbol
Description
Value
Unit
R
th j-pins
Thermal Resistance Junction-pins
Ma x.
85
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
7
9
10.2
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.1
%
S/N
Signal to Noise Ratio V
out
= 1Vrms (mode = OFF)
106
dB
S
C
Channel Separation f = 1KHz
90
dB
Input Control (0.5dB)
-31.5
0
dB
SRS Center Control (1dB step)
-31
0
dB
SRS Space Control (1dB step)
-31
0
dB
Mute Attenuation
100
dB
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
11
V
T
amb
Operating Ambient Temperature
-10 to 85
C
T
stg
Storage Temperature Range
-55 to +150
C
ELECTRICAL CHARACTERISTICS (refer to the test circuit T
amb
= 25
C, V
S
= 9V, R
L
= 10K
,
V
in
= 1Vrms; R
G
= 600
, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
7
9
10.2
V
I
S
Supply Current
25
mA
SVR
Ripple Rejection
L
CH
/ R
CH out
, Mode = OFF
60
80
dB
INPUT STAGE
R
IN
Input Resistance
37.5
50
62.5
K
V
CL
Clipping Level
THD = 0.3%
2
2.5
Vrms
A
VMIN
Min. Attenuation
-1
0
1
dB
A
VMAX
Max. Attenuation
31
31.5
32
dB
A
STEP
Step Resolution
-1
0.5
1
dB
V
DC
DC Steps
Adjacent att. step
-3
0
3
mV
SRS EFFECT CONTROL
C
range1
Center/Space Control Range
-31
0
dB
Sstep1
Center/Space Step Resolution
1
dB
TDA7467
3/11
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUDIO OUTPUTS
N
o(Off)
Output Noise (OFF)
Output muted, Flat
BW (20Hz to 20KHz)
4
5
Vrms
Vrms
N
o(srs)
Output noise (srs)
Surround Sound
BW (20Hz to 20KHz)
50
Vrms
d
Distortion
A
V
= 0; V
in
= 1Vrms
0.01
0.1
%
S
C
Channel Separation
90
dB
V
ocl
Clipping Level
d = 0.3%
2
2.5
Vrms
R
out
Output Resistance
30
V
out
DC Voltage Level
3.8
V
BUS INPUTS
V
il
Input Low Voltage
1
V
V
ih
Input High Voltage
3
V
I
in
Input Current
-5
5
A
V
o
Output Voltage SDA
Acknowledge
I
O
=1.6mA
0.4
V
SRS SURROUND SOUND MATRIX
CENTER
SRS Control Range
-31
0
dB
Step
C
Center Step Resolution
1
dB
SPACE
SRS Space Control Range
-31
0
dB
Step
S
Space Step Resolution
1
dB
P
ERSP1
Perspective 1
Input Signal of 125Hz
SPACE = 0dB, CENTER = MUTE
R
in
= GND; Li
n
R
OUT
12
dB
P
ERSP2
Perspective 2
Input Signal of 2.15KHz
SPACE = 0dB, CENTER = MUTE
R
in
= GND; Li
n
R
OUT
0
dB
L+R
L+ R SRS Curve
SPACE = MUTE, CENTER =0dB
R
in
= GND; Li
n
R
OUT
-8.5
dB
L, R
L, R SRS Curve
SPACE = MUTE, CENTER =0dB
R
in
= GND; Li
n
L
OUT
L
in
= GND; Ri
n
R
OUT
-13.4
dB
TDA7467
4/11
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7467 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I
2
CBUS
Figure 4: Timing Diagram of I
2
CBUS
Figure 5: Acknowledge on the I
2
CBUS
TDA7467
5/11
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte
A subaddress bytes
A sequence of data (N byte + achnowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
0
0
A
0 ACK B
DATA
ACK
DATA
ACK P
ACK = Achnowledge
S = Start
P = Stop
B = Auto Increment
EXAMPLES
No Incremental Bus
The TDA7467 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no in-
cremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Incremental Bus
The TDA7467 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBAD-
DRESS from "1XXXX1XX" to "1XXX1111" of DATA are ignored.
The DATA 1 concerns the subaddress sent, and the DATA 2 concerns the subaddress plus one sent in
the loop etc. and at the end, it receives the stop condition.
CHIP ADDRESS
SUBADDRESS
DATA
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
0
0
A
0 ACK 0
X
X
X
X
X D1 D0 ACK
DATA
ACK P
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
0
0
A
0 ACK 1
X
X
X
X
X D1 D0 ACK
DATA
ACK P
TDA7467
6/11
MSB
LSB
INPUT ATTENUATION
D7
D6
D5
D4
D3
D2
D1
D0
0.5 dB STEPS
0
0
0
0
0
0
1
-0.5
0
1
0
-1
0
1
1
-1.5
1
0
0
-2
1
0
1
-2.5
1
1
0
-3
1
1
1
-3.5
4 dB STEPS
0
0
0
0
0
0
0
0
1
-4
0
0
1
0
-8
0
0
1
1
-12
0
1
0
0
-16
0
1
0
1
-20
0
1
1
0
-24
0
1
1
1
-28
1
MUTE
INPUT ATTENUATION = 0
-31.5dB
SRS MODE
D7
D6
D5
D4
D3
D2
D1
D0
MODE
X
0
SRS OFF (FIX)
X
1
SRS ON
0
1
MONO SRS (MONO 3D)
1
1
STEREO SRS (STEREO 3D)
RECOMMENDED TO ATTENUATE -3dB ON "SRS OFF"
ie. MONO SRS (MONO 3D): XXXXXX01
INPUT ATTENUATION SELECTION
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
B
X
X
X
X
X
0
0
MODE
B
X
X
X
X
X
0
1
SRS/SPACE ATTENUATION
B
X
X
X
X
X
1
0
SRS/CENTER ATTENUATION
B
X
X
X
X
X
1
1
INPUT ATTENUATION
B = 1: INCREMENTAL BUS; ACTIVE
B = 0: NO INCREMENTAL BUS
X = INDIFFERENT 0, 1
The first byte (subaddress)
DATA BYTES (Address = 80(HEX) if ADDR pin is floating, 82(HEX) if ADDR pin is connected to V
S
):
FUNCTION SELECTION:
TDA7467
7/11
SPACE & CENTER ATTENUATION SELECTION
MSB
LSB
SPACE & CENTER ATT.
D7
D6
D5
D4
D3
D2
D1
D0
1 dB STEPS
0
0
0
0
0
0
1
-1
0
1
0
-2
0
1
1
-3
1
0
0
-4
1
0
1
-5
1
1
0
-6
1
1
1
-7
8 dB STEPS
0
0
0
0
0
0
1
-8
0
1
0
-16
0
1
1
-24
1
X
X
X
X
X
MUTE
X = INDIFFERENT 0, 1
SPACE & CENTER ATTENUATION = 0dB
-31dB
POWER ON RESET
INPUT
MUTE
MODE
OFF (FIX)
SPACE ATTENUATION
MUTE (MIN)
CENTER ATTENUATION
MUTR (MIN)
TDA7467
8/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.63
0.025
b
0.45
0.018
b1
0.23
0.31
0.009
0.012
b2
1.27
0.050
D
37.34
1.470
E
15.2
16.68
0.598
0.657
e
2.54
0.100
e3
33.02
1.300
F
14.1
0.555
I
4.445
0.175
L
3.3
0.130
DIP28 PACKAGE MECHANICAL DATA
TDA7467
9/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45
(typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
8
(max.)
SO28 PACKAGE MECHANICAL DATA
TDA7467
10/11
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics Printedin Italy All RightsReserved
The SoundRetrieval System and
are registered trademarks of SRS Labs, Inc.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - HongKong - Italy- Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore- Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom- U.S.A.
TDA7467
11/11
PDF 
ZIP