Dual 24-bit 40 MIPS DSP Cores
8 bit Microcontroller
4 receive and 5 transmit stereo channels of
Serial Audio Interface
Synchronous Serial Interface for communica-
tion with external processor
FIFO based mailboxes for inter-processor
communications
External Memory Interface to 128Kb SRAM or
1Mb DRAM
CORDIC co-processor
Programmable PLL to suite wide range of ex-
ternal crystal oscillation frequencies
SPI control interface
Powerful debug interfaces
1280 words Program Memory for DSP1, 768
words Program Memory for DSP0
256 words X and Y Data RAM and Data ROM
for each DSP
256 byte Data RAM for Microcontroller
768 byte Auxiliary RAM for Microcontroller
DESCRIPTION
The device is a high-performance Digital Signal
Processing IC particularly suited to Audio applica-
tions. The device contains two 24-bit 40 MIPS
DSP cores delivering a total of 80 MIPS of DSP
processing power. There is also an embedded 8-
bit Microcontroller to handle all control functions.
All data and program memories for both DSP
cores are on-chip. A variety of highly programma-
ble and flexible peripheral blocks for both the Mi-
crocontroller and the DSPs have been integrated
to form a powerful audio processing system on a
single chip.
This is preliminary information on a new product now in development. Details are subject to change without notice.
July 1999
Host
Interface 0
DEBUG
Interface
DSP0
CORE
M8051
CORE
Mi cro
Memory
Interface
Serial
Interface
Control
Interface
AUX-RAM
768 Bytes
Peripheral
C ordic
Ari thmetic
U nit
PDB1
PAB1
YDB1
YAB1
XDB1
XAB1
PDB0
PAB0
YDB0
YAB0
XDB0
XAB0
MCLK
DSP1
CORE
Host
Interface 1
Serial
Audio
Interface
Synchronous
Audio
Interface
SRAM/
D RAM
Interface
XCHG
Interface
XDB0
XAB0
XDB1
XAB1
X-RAM0
X-ROM0
Y-RAM0
Y-ROM0
P-RAM0
P-ROM0
P-RAM1
P-ROM1
Y-RAM1
Y-ROM1
X-RAM1
X-ROM1
AUX-RAM
256 Bytes
Watchdog
Timer
PLL
Clock
Oscillator
DCLK
BLOCK DIAGRAM
TQFP100
TDA7503
DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS
PRODUCT PREVIEW
1/26
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DDC
Core DC Supply voltage
-0.5 to 5
V
V
DDP
Pads DC Supply voltage
-0.5 to 6.5
V
V
I
, V
IN
Digital or analog input voltage
-0.5 to (V
DDP
+0.5)
V
T
op
Operative temperature range
-40 to 85
C
T
stg
Storage temperature range (plastic)
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal resistance Junction to Ambient
85
C/W
1
2
3
5
6
4
7
8
9
10
45
11
46
47
48
49
50
86
85
84
83
81
82
80
79
78
77
76
70
69
68
66
65
67
75
74
73
71
72
MOSI
MISO
RESET
VDDI3_CORE3
T1(P3.5)
VSSI3_CORE3
LRCKR
VDDE5_CI1
VSSE5_CI1
SCLK
SS/GPIOS
SRA_D7/DRA3
SRA_D6/DRA2
SRA_D5/DRA1
SRA_D4/DRA0
VSSE5_DR1
VDDE5_DR1
SRA_D3/DRD3
SRA_D2/DRD2
SRA_D1/DRD1
SRA_D0/DRD0
SRA12/DRA8
RD(P3.7)
WR(P3.6)
xALE
RAD0(P0.0)
RAD2(P0.2)
RAD1(P0.1)
RAD3(P0.3)
RAD4(P0.4)
RAD5(P0.5)
RAD6(P0.6)
RAD7(P0.7)
XPSEN
RA11(P2.3)
RA9(P2.1)
RA13(P2.5)
RA14(P2.6)
RA8(P2.0)
RA10(P2.2)
VSSI3_CORE4
VDDI3_CORE4
VDDE5_MI1
VSSE5_MI1
D97AU693
40
41
42
43
44
97
96
95
94
92
93
91
90
89
88
87
TXD(P3.1)
RXD(P3.0)
GPIO6(P1.6)
GPIO5(P1.5)
GPIO3(P1.3)
GPIO4(P1.4)
VDDE5_MI2
VSSE5_MI2
GPIO2(P1.2)
GPIO1(P1.1)
GPIO0(P1.0)
100 99
98
T0(P3.4)
INT0(P3.2)
INT1(P3.3)
34
35
36
37
38
39
XTI
FILT
PGND
PVCC
SCANEN
TESTEN
DBOUT
DBCK/OS1
DBIN/OS0
DBRQN
DBSEL
29
30
31
32
33
VSSE5_SA1
VDDE5_SA1
XTO
26
27
28
12
13
14
16
17
15
18
19
20
21
22
59
58
57
55
54
56
64
63
62
60
61
SDO4
SDI0
SDI1
SDI3
SCLKR
SDI2
VSSI3_CORE2
SDO0
SDO1
SDO3
SDO2
SRA9/DRA5
VDDE5_DR2
VSSE5_DR2
SRA13/RAS
VSSI3_CORE1
SRA8/DRA4
RA15(P2.7)
RA12(P2.4)
SRA10/DRA6
SRA11/DRA7
DRD
23
24
25
52
51
53
LRCKT
SCLKT
VDDI3_CORE2
DWR
ALE/CAS
VDDI3_CORE1
PIN CONNECTION
TDA7503
2/26
PIN DESCRIPTION
N.
Name
Type
Reset
Status (1)
Function
11
LRCKR
I
Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select
signal for received serial audio data. This signal has a frequency equal to
the audio sample rate.
12
SCLKR
I
Audio Serial Port Receive Bit Clock. SCLK clocks received digital audio
data into pins SDI0, SDI1, SDI2, and SDI3
16
SDI0
I
Stereo Digital Audio Data. SDI0 is a stereo digital audio data input pin
channel 0.
15
SDI1
I
Stereo Digital Audio Data. SDI1 is a stereo digital audio data input pin
channel 1.
14
SDI2
I
Stereo Digital Audio Data. SDI2 is a stereo digital audio data input pin
channel 2.
13
SDI3
I
Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital
audio data input pin and is multiplexed with the SSI's Serial Receive
Data Input channel 3.
25
LRCKT
I
Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The
Left/Right select signal for transmitted serial audio data. This signal has a
frequency equal to the audio sample rate. This signal is multiplexed with
the SSI's Frame Sync Input.
24
SCLKT
I
Audio Serial Port Transmit Bit Clock/SSI Serial Bit Clock. SCLK clocks
digital audio data out of pins SDO0, SDO1, SD02, SD03, and SD04. This
pin is multiplexed with the SSI's serial bit clock.
21
SDO0
O
High
Stereo Digital Audio Data. SDO0 is a stereo digital audio data output pin
channel 0.
20
SDO1
O
High
Stereo Digital Audio Data. SDO1 is a stereo digital audio data output pin
channel 1.
19
SDO2
O
High
Stereo Digital Audio Data. SDO2 is a stereo digital audio data output pin
channel 2.
18
SDO3
O
High
Stereo Digital Audio Data. SDO3 is a stereo digital audio data output pin
channel 3.
17
SDO4
O
High
Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital
audio data output pin and is multiplexed with the SSI's Serial Transmit
Data Output channel 4.
34
SCANEN
I
SCAN Enable. Enable SCAN Path and MUXing of SCANIN and SCANOUT
Pins.
33
TESTEN
I
Test Enable. Enable Scan Mode Clocks. An active low signal will enable
the same clock to all scan chains. This pin also makes all latches
transparent.
49
SRA_D0/DRD0
I/O
I
DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line
0.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 0. When in DRAM Mode they act as the EMI data line 0.
48
SRA_D1/DRD1
I/O
I
DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line
1.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 1. When in DRAM Mode they act as the EMI data line 1.
47
SRA_D2/DRD2
I/O
I
DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line
2.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 2. When in DRAM Mode they act as the EMI data line 2.
46
SRA_D3/DRD3
I/O
I
DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line
3.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 3. When in DRAM Mode they act as the EMI data line 3.
43
SRA_D4/DRA0
I/O
O, High
DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line
0. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 4. When in DRAM Mode they act as the EMI address line 0.
TDA7503
3/26
N.
Name
Type
Reset
Status (1)
Function
42
SRA_D5/DRA1
I/O
O, High
DSP SRAM Multiplexed Address/Data Line 5/DSP DRAM Address Line
1. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 5. When in DRAM Mode they act as the EMI address line 1.
41
SRA_D6/DRA2
I/O
O, High
DSP SRAM Multiplexed Address/Data Line 6/DSP DRAM Address Line
2. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 6. When in DRAM Mode they act as the EMI address line 2.
40
SRA_D7/DRA3
I/O
O, High
DSP SRAM Multiplexed Address/Data Line 7/DSP DRAM Address Line
3. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 7. When in DRAM Mode they act as the EMI address line 3.
56
SRA8/DRA4
O
High
DSP SRAM Address Line 8/DSP DRAM Address Line 4. When in SRAM
Mode these pins act as the EMI address line 8. When in DRAM Mode
they act as the EMI address line 4.
59
SRA9/DRA5
O
High
DSP SRAM Address Line 9/DSP DRAM Address Line 5. When in SRAM
Mode these pins act as the EMI address line 9. When in DRAM Mode
they act as the EMI address line 5.
62
SRA10/DRA6
O
High
DSP SRAM Address Line 10/DSP DRAM Address Line 6. When in
SRAM Mode these pins act as the EMI address line 10.When in DRAM
Mode they act as the EMI address line 6.
60
SRA11/DRA7
O
High
DSP SRAM Address Line 11/DSP DRAM Address Line 7. When in
SRAM Mode these pins act as the EMI address line 11. When in DRAM
Mode they act as the EMI address line 7.
50
SRA12/DRA8
O
High
DSP SRAM Address Line 12/DSP DRAM Address Line 8. When in
SRAM Mode these pins act as the EMI address line 12. When in DRAM
Mode they act as the EMI address line 8.
55
SRA13/RAS
O
High
DSP SRAM Address Line 13/DRAM Row Address Strobe. When in
SRAM Mode this pin acts as the EMI address lines 13. When in DRAM
Mode this pin acts as the row address strobe.
51
ALE/CAS
O
High
DSP SRAM Address latch enable/colomn Address. When in SRAM
Mode this pin acts as the EMI Address Latch Enable. When in DRAM
Mode this pin acts as the column address strobe.
52
DWR
O
High
DSP SRAM Write Enable/DRAM Write Enable. This pin serves as the
write enable for the EMI when in DRAM and SRAM Modes.
61
DRD
O
High
DSP SRAM Read Enable/DRAM Read Enable. This pin serves as the
read enable for the EMI when in DRAM and SRAM Modes.
36
DBCK/OS1
I/O
I
Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port
is provided when an input. When an output, together with OS0 provides
information about the chip status. Can also be used as GPIO for the
8051.
37
DBIN/OS0
I/O
I
Debug Port Serial Input/Chip Status 0. The serial data input for the
Debug Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Can also be used as
GPIO for the 8051.
35
DBOUT
I/O
I
Debug Port Serial Output. The serial data output for the Debug Port. Can
also be used as a GPIO for the 8051.
38
DBRQN
I
Debug Port Request Input. Means of entering the Debug mode of
operation.
39
DBSEL
I
Debug Port MUX Selection. Selects either DSP0 or DSP1 to be
connected to the Debug Port pins.
67
RA8(P2.0)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 8 of
a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
68
RA9(P2.1)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 9 of
a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
PIN DESCRIPTION (continued)
TDA7503
4/26
N.
Name
Type
Reset
Status (1)
Function
75
RA10(P2.2)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 10
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
69
RA11(P2.3)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 11
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
63
RA12(P2.4)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 12
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
66
RA13(P2.5)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 13
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
65
RA14(P2.6)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 14
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
64
RA15(P2.7)
I/O
I
Microcontroller High Byte Address Lines. This pin is the address line 15
of a 16 bit address, for external EPROM and memory mapped devices. It
can also act as GPIO using the P2 and P2DIR registers.
83
RAD0(P0.0)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 0 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
82
RAD1(P0.1)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 1 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
81
RAD2(P0.2)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 2 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
80
RAD3(P0.3)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 3 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
79
RAD4(P0.4)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 4 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
78
RAD5(P0.5)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 5 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
77
RAD6(P0.6)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 6 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
76
RAD7(P0.7)
I/O
I
Microcontroller Address/Data Pins. This pin is the multiplexed address
and data line bit 7 for external EPROM and memory mapped peripherals.
It can also act as GPIO using the P0 and P0DIR registers.
84
xALE
I/O
I
Microcontroller External Address Latch Enable. This pin is the address
latch enable. A logic high indicates that address/data lines 7 through 0
represent an address. Inactive for Program/Data fetches from internal
AUX.
85
WR(P3.6)
I/O
I
Microcontroller Write Strobe. External data memory write strobe. This pin
can also act as GPIO using the P3 and P3DIR registers.
86
RD(P3.7)
I/O
I
Microcontroller Read Strobe. External data memory read strobe. Active
Low, or GPIO. This pin can also act as GPIO using the P3 and P3DIR
registers. Disabled by setting the RDSEL bit in the PINCTL register.
70
XPSEN
I/O
I
Microcontroller External Program Memory Enable. External program
memory enable pin. Active Low. Changes functionality to RD when
Microcontroller is fetching instructions out of internal AUX ram.
Controlled by the PSSEL and PSBIT bits in the PINCTL register.
PIN DESCRIPTION (continued)
TDA7503
5/26
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