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PRODUCT PREVIEW

This is preliminary information on a new product now in development. Details are subject to change without notice.

TDA7522

Digital Servo & Decoder

BUILT IN 8Bit MICROCONTROLLER
(STANDARD ST7) with:

24 KByte ROM available for ST7 & Servo-Audio

DSP

1024Byte RAM, including 128byte stack

4KByte RAM for CD-Text memory (for 1block)

Built in R-W subcode buffer (Max. 144Byte

8packs) for CD-Text

24 bit general I/O port (PoartA[7-0], PortB[7-0],

PortC[7-0])

One External Interrupt (16 IRQ encoder inside)

16bit free running counter timer

8bit 1ch general purpose A/D

C bus I/F

Watch dog

Kenwood I/F

STAND-BY MODE (Stop all clocks and Shut down power of Peripheral (PON pin))

BUILT IN SERVO & AUDIO DIGITAL SIGNAL PROCESSOr (SAC-DSP) inclusive of:

1024x19bit Program RAM

512x16bit Coefficient RAM

1024x20bit Data RAM

128x6bit Decimation RAM

MAC: 16 bit (Coefficients) x 20 bit (data) multiplier with 38 bit adder

Instruction execution rate as high as 56MIPS

BUILT IN PROGRAMMABLE CLOCK GENERATOR PLL

PERIPHERALS for CD PLAYER APPLICATION

Data Acquisition, Erasure correction, CLV&CAV controller

Subcode decoder (CD-Text, CD-Graphic I/F)

Shock proof memory controller, Disturbance detector

Decimation filter

ACTUATORS DRIVING MODE SELECTABLE between PWM or PDM MODE

256Fs / 384Fs (16.9344MHz) CLOCK INPUT.

May 1998

TQFP80

(14 x 14 x 1.40mm body)

TDA7522

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1.0 DESCRIPTION

TDA7522 is a single chip processor consisting of Decoder, Servo and 1bit D/A for 4times CD-ROM / CD-
Audio. Main concept of this IC is that it is based on embedded System Micro Controller which allows cus-
tomer to develop system software very easily: just based on provided commands. Further the microcon-
troller is fully customer dedicated in terms of both software and general purpose Port.

By combination of ST Analog front-end IC (TDA7521), all CD functions including Shock Proof Memory
Controller and CD-Text function can be realized.

The TDA7522 portfolio is constituted by three different versions:

'development': which gives the possibility to have at disposal the complete sw development environ-

ment, by means of a dedicated package

`in field development': standard package but with selection of program memory: on chip RAM, on chip

ROM. The program RAM is fully patchable through the standard IIC interface, giving the possibility of
sw changing while chip is working in the real environment.

`production': standard package, but with software permanently stored in the on chip ROM.

2.0 TECHNOLOGY

All version are produced using the HCMOS6 0.35um technology which works @3.3Vdc; to avoid interface
problem with existing logics, all digital Inputs are 5V tolerant. When interfacing logic on TDA7522 outputs,
user should take care of output levels that are at CMOS level @3.3V. Depending on output type the I

and I

value are guaranteed at 4mA or 8mA; the TDA7522 output driving specification will be included in

a next issue of this data sheet.

3.0 ADDITIONAL FEATURES

16Mbit DRAM I/F allows maximum 9 seconds shock proof

Built-in 1bit Delta Sigma modulation for DAC

Subcode P,Q and R-W decoding

Error Correction is capable of Dual C1 and quadruple C2 erasure corrections

Jitter absorbing capability: +/- 6 frames

Automatic fine gain/balance/offset adjustment for tracking and focus servos

Built-in Digital Silence detection

Built-in EFM Demodulation/Sync Rear and Forward protection

Soft audio mute

Built-in Digital PLL with large capture range from 0.5 to 4 times speed

Digital Servo control for all servo loops

Capable of 2x and 4x speeds for shock proof and CD-ROM applications

Capable of wide temperature range (-40C to +85C) stable operation

Fast access times for CD-ROM applications due to wide Capture range and CAV mode run at max 4
times overspeed

CLV or CAV (lock-to-disk mode) spindle servo operations

Digital Output SPDIF (DIT CP340)

Sony LSI Output Interface (for Audio & CD-ROM)

Pulsate SLED mode support

Built in 8times Audio Over sampling filter.

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TDA7522

Figure 1. Pin Connection

MPH

I
N_A

I
N

KAD

I
N_

NRE

TDA7522

80-pin

EST

I
N_

VSS_

SEL

SEAR

MST

I
N_

PIN_DRA10

PIN_DRA11

PIN_RAS

PIN_CAS

PIN_MUTER

PIN_MUTEL

PIN_C2P0

PIN_LRCK

PIN_BSL_SAK48

PIN_BSR_SDK48

PIN_CLKOUT

PIN_DGTSYNC

PIN_DGTLIN7

PIN_CORE_VSS_1

PIN_CORE_VDD_1

PIN_DGTLIN_6

PIN_DGTLIN5

PIN_DGTLIN4

PIN_DGTLIN3

PIN_DGTLIN2

PIN_DGTLIN1_UF

PIN_DGTLIN0_OF

PIN_SERCK

PIN_SERDA

SPD

I
N

PIN_SLEDL

PIN_K_VER_HOR

PIN_WFCK

PIN_EXCK

PIN_SBSO

PIN_CORE_VDD_3

PIN_CORE_VSS_3

PIN_SCOR

PIN_DOUT

PIN_CS

PIN_SRQ

PIN_DATAS

PIN_DATAM

PIN_CLK

PIN_DRS

PIN_DWR

TDA7522 general overview is reported below.
REMARK: CONSIDERING THE SELECTION DONE BY CUSTOMER, THE DRAM I/F COULD BE
SLIGTHY MODFIED. DETAILS WILL BE GIVEN IN A LATER ISSUE OF DATA SHEET.

TDA7522

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Table 1. Pin Description

Pin Number

Name

Function

Description

SERDA

I/O

Data line for Serial I/F

SERCK

Clock line for Serial I/F

DGTLIN0_OF

HF bit 0 and Servo overflow

DGTLIN1_UF

HF bit 1 and Servo underflow

DGTLIN2

HF bit 2 and Servo bit 0

DGTLIN3

HF bit 3 and Servo bit 1

DGTLIN4

HF bit 4 and Servo bit 2

DGTLIN5

HF bit 5 and Servo bit 3

DGTLIN6

HF bit 6 and Servo bit 4

CORE_VDD_1

Vdd

Digital Power supply

CORE_VSS_1

Gnd

Digital Ground

DGTLIN7

HF bit 7 and Servo bit 5

DGTSYNC

Sync strobe for Multiplexer

CLKOUT

System clock output to TDA7521

BSR_SDK48

LSI I/F clock output or
DAC bit stream right channel output

BSL_SAK48

LSI I/F data output or DAC bit stream left channel output

LRCK

LSI I/F L/R signal

C2PO

Validity flag output for CD-ROM decoder

MUTEL

Mute left signal (active high)

MUTER

Mute right signal (Active high)

KDMPHYS

I/O

De-emphasis indication or ST7 GPIO PA2

PON

I/O

System shutdown pin for power saving mode or
ST7 GPIO PC7

AVDD_1

Vdd

Analog power supply

XTI

Crystal input

AVSS_1

Gnd

Analog ground

XTO

Crystal output

KADC_VRH

ADC top reference Voltage input

KADC_VRL

ADC bottom reference Voltage input

KADC_IN

ADC input

CORE_VDD_2

Vdd

Digital Power supply

CORE_VSS_2

Gnd

Digital Ground

Nreset

Hardware reset

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TDA7522

TESTEN

Test enable signal (Active low)

SCK

IIC I/F clock signal

SDA

I/O

IIC I/F data

SCANEN

Scan enable (active high) or select DRAM outputs as TEST
outputs when TESTEN is inactive

KASEL

I/O

DAC polarity selection pin or ST7 GPIO PA0

KTEST

I/O

User test mode selection or ST7 GPIO PA1

KSEARCH

I/O

Gain change during search or ST7 GPIO PA3

MSTOP

I/O

interrupt request/stand-by pin or ST7 GPIO PC5

SLEDL

I/O

SLED limit switch or ST7 GPIO PC6

K_VER_HOR

I/O

Indication of vertical or horizontal operation
or ST7 GPIO PA4

WFCK

Write Frame clock for Subcode P-W output

EXCK

SBSO readout clock input

SBSO

Subcode P-W serial output

SCOR

Subcode sync output

DOUT

SPDIF Digital audio output

I/O

ST7 GPIO PC4

SRQ

I/O

ST7 GPIO PC3

CORE_VDD_3

Vdd

Digital Power supply

CORE_VSS_3

Gnd

Digital Ground

DATAS

I/O

ST7 GPIO PC2

DATAM

I/O

ST7 GPIO PC1

CLK

I/O

ST7 GPIO PC0

DRS

I/O

Shock proof memory Read control

DWR

I/O

Shock proof memory Write control

CAS

I/O

Shock proof memory Column address select

RAS

I/O

Shock proof memory Row address select

DRA11

I/O

DRAM Address 11

DRA10

I/O

DRAM Address 10

DRA9

I/O

DRAM Address 9 or Mirror signal output

DRA8

I/O

DRAM Address 8 or TZC (Tracking Zero Cross) signal output

DRA7

I/O

DRAM Address 7 or FOK (Focus OK) signal output

DRA6

I/O

DRAM Address 6 or ST7 GPIO PB7 or PLLINF signal output

Pin Number

Name

Function

Description

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