March 2006
Rev 1
1/23
23
VN5050J-E
Single channel high side driver for automotive applications
Features
General
Application
All types of resistive, inductive and capacitive
loads
Main
Inrush current active management by power
limitation
Very low stand-by current
3.0V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
In compliance with the 2002/95/ec european
directive
Diagnostic Functions
Open drain status output
On state open load detection
Off state open load detection
Thermal shutdown indication
Protections
Undervoltage shut-down
Overvoltage clamp
Output stuck to Vcc detection
Load current limitation
Self limiting of fast thermal transients
Protection against loss of ground and loss of
V
CC
Thermal shut down
Reverse battery protection (see
Figure 28
)
Electrostatic discharge protection
Description
The VN5050J-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active V
CC
pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table). The device detects open load
condition both in on and off state, when STAT_DIS
is left open or driven low. Output shorted to V
CC
is
detected in the off state.
When STAT_DIS is driven high, the STATUS pin
is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long duration
overload, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
PowerSSO-12 (Slug down)
Order codes
Max supply voltage
V
CC
41V
Operating voltage range
V
CC
4.5 to 36V
Max On-State resistance
R
ON
50 m
Current limitation (typ)
I
LIMH
19A
Off state supply current (TYP)
I
S
2
A
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12 (slug down)
VN5050J-E
VN5050JTR-E
www.st.com
Contents
VN5050J-E
2/23
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
GND Protection Network Against Reverse Battery . . . . . . . . . . . . . . . . . 15
3.1.1
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Load Dump Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
C I/Os PROTECTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Package and PCB Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
PowerSSO-12 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VN5050J-E
Block diagram and pin description
3/23
1
Block diagram and pin description
Figure 1.
Block Diagram
Name
Function
Figure 2.
Configuration Diagram (Top View) & Suggested Connections For Unused
and n.c. Pins
Table 1.
Pin Function
V
CC
Battery connection
OUTPUT
Power output
GND
Ground connection. Must be reverse battery protected by an external
diode/resistor network
INPUT
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
STATUS
Open drain digital diagnostic pin
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin
LOGIC
UNDERVOLTAGE
OVERTEMP.
I
LIM
PwCLAMP
GND
INPUT
OUTPUT
DRIVER
V
CC
CLAMP
V
DSLIM
STAT_DIS
STATUS
OPENLOAD ON
OPENLOAD OFF
Pwr
LIM
V
CC
Connection / Pin
Status
N.C.
Output
Input
STAT_DIS
Floating
X
X
X
X
X
To Ground
N.R.
X
N.R.
10K
resistor 10K resistor
TAB = V
cc
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
12
11
10
9
8
7
1
2
3
4
5
6
V
CC
V
CC
INPUT
STAT_DIS
GND
STATUS
N.R. = Not recommended
Electrical specifications
VN5050J-E
4/23
2 Electrical
specifications
Figure 3.
Current and Voltage Conventions
2.1
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
INPUT
STATUS
STAT_DIS
OUTPUT
V
CC
V
F
I
GND
V
CC
GND
OUTPUT
STAT_DIS
I
SD
INPUT
I
IN
V
SD
V
IN
I
OUT
V
OUT
STATUS
I
STAT
V
STAT
V
CC
I
S
V
F
= V
OUT
- V
CC
during reverse battery condition
Table 2.
Absolute Maximum Ratings
V
CC
DC supply voltage
41
V
-V
CC
Reverse DC supply voltage
0.3
V
-I
GND
DC reverse ground pin current
200
mA
I
OUT
DC output current
Internally limited
A
-I
OUT
Reverse DC output current
12
A
I
IN
DC input current
+10 / -1
mA
I
STAT
DC status current
+10 / -1
mA
I
STAT_DIS
DC status disable current
+10 / -1
mA
E
MAX
Maximum switching energy
(L=1.5mH; R
L
=0
; V
bat
=13.5V; T
jstart
=150C; I
OUT
=
I
limL
(Typ.) )
51
mJ
V
ESD
Electrostatic Discharge (Human Body Model: R=1.5K
;
C=100pF)
4000
4000
4000
5000
5000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011)
750
V
T
j
Junction operating temperature
-40 to 150
C
T
stg
Storage temperature
-55 to 150
C
VN5050J-E
Electrical specifications
5/23
2.2 Thermal
Data
Symbol
Parameter
Max Value
Unit
C/W
C/W
2.3 Electrical
Characteristics
8V<V
CC
<36V; -40C<T
j
<150C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Table 3.
Thermal Data
R
thj-case
Thermal resistance junction-case
2.8
R
thj-amb
Thermal resistance junction-ambient
See
Figure 31
Table 4.
Power section
V
CC
Operating supply voltage
4.5
13
36
V
V
USD
Undervoltage shutdown
3.5
4.5
V
V
USDhyst
Undervoltage Shut-down
hysteresis
0.5
V
R
ON
On state resistance
I
OUT
=1A; T
j
=25C
I
OUT
=1A; T
j
=150C
I
OUT
=1A; V
CC
=5V; T
j
=25C
50
100
65
m
m
m
V
clamp
Clamp Voltage
I
S
=20mA
41
46
52
V
I
S
Supply current
Off State; V
CC
=13V; V
IN
=V
OUT
=0
T
j
=25C;
On State; V
CC
=13V; V
IN
=5V; I
OUT
=0A
2
(1)
1.9
5
(1)
3.5
A
mA
I
L(off1)
Off state output current
V
IN
=V
OUT
=0V; V
CC
=13V; T
j
=25C
V
IN
=V
OUT
=0V; V
CC
=13V; T
j
=125C
0
0
0.01
3
5
A
I
L(off2)
V
IN
=0V; V
OUT
=4V
-75
0
V
F
Output - V
CC
diode voltage
-I
OUT
=2A; T
j
=150C
0.7
V
(1) PowerMOS leakage included.
Table 5.
Switching (V
CC
=13V)
t
d(on)
Turn-on delay time
R
L
=6.5
(see
Figure 6
)
20
s
t
d(off)
Turn-off delay time
R
L
=6.5
(see
Figure 6
)
35
s
dV
OUT
/dt
(on)
Turn-on voltage slope
R
L
=6.5
see
Figure 21
V
/s
dV
OUT
/dt
(off)
Turn-off voltage slope
R
L
=6.5
see
Figure 22
V
/s
W
ON
Switching energy losses
during t
won
R
L
=6.5
(see
Figure 6
)
0.2
mJ
W
OFF
Switching energy losses
during t
woff
R
L
=6.5
(see
Figure 6
)
0.2
mJ
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