SUMMIT MICROELECTRONICS, Inc. · 300 Orchard City Drive, Suite 131 · Campbell, CA 95008 · Telephone 408-378-6461 · Fax 408-378-6586 · www.summitmicro.com

Characteristics subject to change without notice

SUMMIT

MICROELECTRONICS, Inc.

FEATURES

Digitally Controlled Electronic Potentiometer

8-Bit Digital-to-Analog Converter (DAC)

Independent Reference Inputs
Differential Non-Linearity -

0.5LSB max

 Integral Non-Linearity -

1LSB max

OUT

Value in E

PROM for Power-On Recall

 Equivalent to 256-Step Potentiometer

Unity Gain Op Amp Drives up to 1mA

Simple Trimming Adjustment

 Up/Down Counter Style Operation

Low Noise Operation

"Clickless" Transitions between DAC Steps

No Mechanical Wearout Problem
1,000,000 Stores (typical)
100 Year Data Retention

Operation from +2.7V to +5.5V Supply

Low Power, 1mW max at +5V

Nonvolatile DACPOTTM Electronic Potentiometer
With Up/Down Counter Interface

S9318

OVERVIEW

The S9318 DACPOTTM trimmer is an 8-bit nonvolatile
DAC designed to replace mechanical potentiometers.
The S9318 includes a unity-gain amplifier to buffer the
DAC output and enables V

OUT

to swing from rail to rail.

The DACPOT trimmer operates over a supply voltage
range of 2.7V to 5.5V.

The S9318's simple up/down counter input provides an
ideal interface for automatic test equipment to dither and
monitor the V

OUT

voltage. This interface allows for quick

and consistent calibration of even the most sophisticated
systems.

The S9318 is a pin-compatible performance upgrade for
other industry nonvolatile potentiometers. The S9318
offers double the resolution of these devices and provides
`clickless' transitions of V

OUT

FUNCTIONAL BLOCK DIAGRAM

Counter

Write

Control

INC

UP/DN

GND

VOUT

VDD

8-bit E2 PROM

8-bit

Data

8-bit DAC

2016 ILL2.1

AMP

S9318

2016-04 4/24/99

Analog Section
The S9318 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts an 8-bit value into equivalent analog output
voltages in proportion to the applied reference voltage.

Reference Inputs
The voltage differential between the V

and V

inputs

sets the full-scale output voltage range. V

must be equal

to or greater than ground (i.e. a positive voltage). V

must

be greater than V

and less than or equal to V

. See

table on page 3 for guaranteed operating limits.

Output Buffer Amplifier
The voltage output is a precision unity-gain follower that
can slew up to 1V/

Digital Interface
The interface is designed to emulate a simple up/down
counter, but instead of a parallel count output, a
ratiometric voltage output is provided.

PINOUT

Chip Select (

) is an active low input. Whenever

high the S9318 is in standby mode and consumes the
least power. This mode is equivalent to a potentiometer
that is adjusted to the required setting. When

is low the

S9318 will recognize transitions on the

INC

input and will

move the V

OUT

either toward the V

reference or toward

the V

reference depending upon the state of the UP/

input.

The host may exit an adjustment routine in two ways:
deselecting the S9318 while

INC

is low will not perform a

store operation (a subsequent power cycle will recall the
original data); deselecting the S9318 while

INC

is high will

store the current V

OUT

setting into nonvolatile memory.

Increment (

INC

) is an edge triggered input. Whenever

is low and a high to low transition occurs on the

INC

input, the V

OUT

voltage will either move toward V

or V

depending upon the state of the UP/

input.

UP/Down (UP/

) is an input that will determine the V

OUT

movement relative to V

and V

. When

is low, UP/

is high and there is a high to low transition on

INC

, the

OUT

voltage will move (1/256

x V

-V

) toward V

When

and UP/

are low, and there is a high to low

transition on

INC

, the V

OUT

will move (1/256

x V

-V

)

toward V

INC

UP/DN

GND

2016 ILL1.1

VDD

VOUT

PIN NAMES

Symbol

Description

INC

Increment Input, High to Low
Edge Trigger

UP/

Up/Down Input controlling relative
V

OUT

movement

V+ reference input

GND

Analog and Digital Ground

OUT

Trimmed Voltage Output

V- reference input

Active low chip select input

Supply Voltage (2.7V to 5.5V)

S9318

2016-04 4/24/99

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias

-55

C to +125

Storage Temperature

-65

C to +150

Voltage on pins with reference to GND:

Analog Inputs

-0.5V to V

+.5V

Digital Inputs

-0.5V to V

+.5V

Analog Outputs

-0.5V to V

+.5V

Digital Outputs

-0.5V to V

+.5V

Lead Solder Temperature (10 secs)

300

*COMMENT
Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to
the device. These are stress ratings only, and
functional operation of the device at these or any
other conditions outside those listed in the opera-
tion sections of this specification is not implied.
Exposure to any absolute maximum rating for
extended periods may affect device performance
and reliability.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Accuracy

INL

Integral Non-Linearity

LOAD

= 100

0.5

LSB

DNL

Differential Non-Linearity

LOAD

= 100

0.1

0.5

LSB

Guaranteed but not tested

References V

refH

Input Voltage

refL

Input Voltage

Gnd

refH

to V

refL

Resistance

38K

TCR

Temperature Coefficient

refH

to V

refL

600

ppm/

of R

Analog

EFS

Full-Scale Gain Error

DATA = FF

LSB

Output

OUT

Zero-Scale Output Voltage DATA = 00

TCV

OUT

Temperature

= +5, I

LOAD

= 50

Coefficient

refH

= +5V, V

refL

= 0V

Guaranteed but not tested

Amplifier Output Load Current

-200

+1000

OUT

Amplifier Output Resistance I

= 100

A V

= +5V

= +3V

PSRR

Power Supply Rejection

LOAD

= 10

LSB/V

Amplifier Output Noise

f = 1KHz, V

= +5V

nV/ H

THD

Total Harmonic Distortion

= 1V rms, f = 1KHz

0.08

Bandwidth - 3dB

= 100mV rms

300

kHz

DAC DC ELECTRICAL CHARACTERISTICS
V

= +2.7V to +5.5V, V

refH

= V

, V

refL

= 0V, T

= -40

C to +85

C, unless specified otherwise

2016 PGM T3.4

Condition

Min

Max

Temperature

-40

+85

+2.7V

+5.5V

RECOMMENDED OPERATING CONDITIONS

2016 PGM T1.1

S9318

2016-04 4/24/99

Symbol

Parameter

Conditions

Min

Max

Units

Supply Current

CS = V

1.2

during store, note 1

Supply Standby Current

CS = V

200

Input Leakage Current

= V

Input Leakage Current, note 2

= 0V

-25

High Level Input Voltage

Low Level Input Voltage

0.8

2016 PGM T4.3

DC ELECTRICAL CHARACTERISTICS V

= +2.7V to +5.5V, V

= V

, V

= 0V, Unless otherwise specified

Notes:

1. I

is the supply current drawn while the EEPROM is being updated. I

does not include the current that flows through the Reference

resistor chain.

UP/

and

INC

have internal pull-up resistors of approximately 200k

. When the input is pulled to ground the resulting output

current will be V

/200k

Symbol

Parameter

Min

Max

Unit

Test Method

VZAP

ESD Susceptibility

2000

MS-883, TM 3015

ILTH

Latch-Up

100

JEDEC Standard 17

TDR

Data Retention

100

Years

MS-883, TM 1008

NEND

Endurance

1,000,000

Stores

MS-883, TM 1033

RELIABILITY CHARACTERISTICS

2016 PGM T2.0

S9318

2016-04 4/24/99

INC

UP/

Operation

OUT

toward V

OUT

toward V

Store Setting

Maintain Setting, NO Store

Standby

2016 PGM T5.1

OPERATIONAL TRUTH TABLE

Symbol

Parameter

Min

Max

Units

CLIL

INC

Setup

100

IHDC

INC

High to UP/

Change

100

DCIL

UP/

INC

Setup

100

INC

Low Period

200

INC

High Period

200

IHCH

INC

Inactive to

Inactive

100

Write

Cycle Time

ILVOUT

INC

to V

OUT

Delay

2016 PGM T6.1

AC TIMING CHARACTERISTICS V

= +4.5V to +5.5V

AC TIMING DIAGRAM

CLIL

IHDC

IHDHLD

IHCH

ILVOUT

INC

UP/DN

VOUT

2016 ILL3.1

S9318

2016-04 4/24/99

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

ORDERING INFORMATION

.228 (5.80)

.244 (6.20)

.016 (.40)

.035 (.90)

.020 (.50)
.010 (.25)

x45

.0192 (.49)
.0138 (.35)

.061 (1.75)
.053 (1.35)

.0098 (.25)
.004 (.127)

.05 (1.27) TYP.

.275 (6.99) TYP.

.030 (.762) TYP.
8 Places

.050 (1.27) TYP.

.050 (1.270) TYP.
8 Places

.157 (4.00)
.150 (3.80)

.196 (5.00)

.189 (4.80)

FOOTPRINT

8pn JEDEC SOIC ILL.2

Package
S = 8 Pin SOIC

Base Part Number

S9318

2016 ILL4.1

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S9318S

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S9318S