1
Characteristics subject to change without notice
2051 4.4 3/15/01
SMH4803A
Preliminary
SUMMIT
MICROELECTRONICS, Inc.
SUMMIT MICROELECTRONICS, Inc., 2000 300 Orchard City Dr., Suite 131 Campbell, CA 95008 Phone 408-378-6461 FAX 408-378-6586 www.summitmicro.com
l
Soft Starts Main Power Supply on Card Insertion
or System Power Up
l
Senses Card Insertion via Short Pins or Ejector
Switches
l
Master Enable to Allow System Control of Power
Up or Down
w
Can be used as a Temperature Sense Input
l
Programmable Independent Controls of 3 DC/DC
Converters
w
Not Enabled until Host Supply Fully Soft
Started
w
Programmable Time Delay Between each
Enable Signal
w
Available Input to hold off Dependant Enables
until Conditions are Satisfied
l
Highly Programmable Circuit Breaker
w
Programmable Quick-Trip
TM
Values
w
Programmable Current Limiting
Distributed Power Hot Swap Controller
FEATURES
SIMPLIFIED APPLICATION DRAWING
VDD
VSS
CBSENSE
PD1#
PD2#
UV
OV
PG3#
2.5VREF
PG2#
PG1#
5.0VREF
2051 SAD 1.2
0V
48V
VGATE
Pin Detect
Pin Detect
DC/DC
DC/DC
DC/DC
SMH4803A
FAULT#
ENPGA
ENPGB
Disable / Enable
DRAIN
SENSE
R3
R1
R2
w
Programmable Circuit Breaker Mode:
Latched (Volatile or Nonvolatile)
w
Programmable Duty Cycle Times
w
Programmable Over-current Filter
l
Programmable Host Voltage Fault Monitoring
w
Programmable Under- voltage Hysteresis
w
Programmable UV/OV Voltage Filter
w
Programmable Fault Mode: Latched or Duty
Cycle
l
Nonvolatile Programming to Customize Features
w
Available Pre-programmed from Summit
l
2.5V and 5.0V Reference Outputs
w
Eliminates the Need or Other Primary Volt-
ages
w
Easy Expansion of External Monitor Func-
tions
l
Supply Range 20VDC to >500VDC
2
SMH4803A
2051 4.4 3/15/01
Preliminary
SUMMIT MICROELECTRONICS, Inc.
FUNCTIONAL BLOCK DIAGRAM
PROGRAMM-
ABLE
DELAY
PROGRAMM-
ABLE
DELAY
PROGRAMM-
ABLE
DELAY
+
+
+
Programmable
Quick Trip
Ref. Voltage
50mV
FAULT
LATCH
AND
DUTY
CYCLE
TIMER
FILTER
+
+
5V
2.5V
12V
VGATE
SENSE
+
VDD
VSS
MODE
RESET#
CBSENSE
EN/TS
PD1#
PD2#
UV
OV
PG3#
ENPGA
ENPGB
2.5VREF
PG2#
PG1#
DRAIN
SENSE
VGATE
FAULT#
5.0VREF
12VREF
50k
200k
50k
2051 BD 1.3
3
4
5
15
16
20
12
11
1
10
8
7
9
6
2
18
13
19
17
14
50k
50k
50k
50k
3
2051 4.4 3/15/01
SMH4803A
Preliminary
SUMMIT MICROELECTRONICS, Inc.
PIN CONFIGURATION
PIN DESCRIPTIONS
DRAIN SENSE (1)
The DRAIN SENSE input monitors the voltage at the drain
of the external power MOSFET switch with respect to V
SS
.
An internal 10A source pulls the DRAIN SENSE signal
towards the 5V reference level. DRAIN SENSE must be
held below 2.5V to enable the PG outputs.
VGATE (2)
The VGATE output activates an external power MOSFET
switch. This signal supplies a constant current output
(100A typical), which allows easy adjustment of the
MOSFET turn on slew rate.
EN/TS (3)
The Enable/Temperature Sense input is the master en-
able input. If EN/TS is less than 2.5V, VGATE will be
disabled. This pin has an internal 200k
pull-up to 5V.
PD1# and PD2# (4 & 5)
These are logic level active low inputs that can optionally
be employed to enable VGATE and the PG outputs when
they are at V
SS
. These pins each have an internal 50k
pull-up to 5V.
FAULT# (6)
This is an open-drain, active-low output that indicates the
fault status of the device.
RESET# (7)
Reset# is used to clear latched fault conditions. When this
pin is held low the VGATE and PG outputs are disabled.
Refer to the Circuit Breaker Operation and the associated
timing diagrams for detailed characteristics. This pin has
an internal 50k
pull-up to 5V.
MODE (8)
The state of the MODE signal determines how fault
conditions are cleared. The device is in the latched mode
when the signal is held at V
SS
, and the cycle mode when
held at 5V or left floating. This pin has an internal 50k
pull-up to 5V.
CBSENSE (9)
The circuit breaker sense input is used to detect over-
current conditions across an external, low value sense
resistor (R
S
) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than t
CBD
will trip the circuit breaker. A program-
mable Quick-TripTM sense point is also available.
20-Pin SOIC
2051 PCon 1.0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DRAIN SENSE
VGATE
EN/TS
PD1#
PD2#
FAULT#
RESET#
MODE
CBSENSE
VSS
VDD
PG2#
PG1#
PG3#
ENPGA
ENPGB
2.5VREF
5.0VREF
OV
UV
PRODUCT DESCRIPTION
The SMH4803A is an integrated solution for high reliability
systems to monitor and react to events that could have a
detrimental effect on a system. It can contain or limit faults
to a single circuit board before that fault propagates to the
system. Its programmability lets a single board satisfy
multiple circuit demands while customized to meet special
requirements.
The SMH4803A monitors and controls the primary voltage
in a distributed power system while providing for both hot-
swapping and secondary voltage sequencing in multi-
supply systems. The primary power source can be shut
down if events are sensed that could result in damage to
either the circuit board or the system supply. An external
FET switch is used to soft start the primary voltage once
normal operating conditions are met. The external FET
also uses an external shunt to monitor current for the
circuit breaker function.
The SMH4803A sequences secondary voltage by timed
or externally controlled outputs that enable DC/DC con-
verters. Its reference voltages provide isolation between
primary and secondary voltages, but allow expansion of its
features.
4
SMH4803A
2051 4.4 3/15/01
Preliminary
SUMMIT MICROELECTRONICS, Inc.
*Comment
Stresses listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias ...................... 55
C to 125
C
Storage Temperature ........................... 65
C to 150
C
Lead Solder Temperature (10s) ........................... 300
C
Terminal Voltage with Respect to V
SS
:
VGATE ......................................... V
DD
+ 0.5V
UV, OV, CBSENSE, DRAIN SENSE,
FAULT#, PG1#, PG2#,
and PG3# ...................... 0.5V to V
DD
+ 0.5V
ABSOLUTE MAXIMUM RATINGS*
UV (11)
The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program-
mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.
OV (12)
The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if OV is greater than 2.5V. A filter
delay is available on the OV input.
5.0VREF & 2.5VREF (13 & 14)
These are precision 5V and 2.5V output reference volt-
ages that may be use to expand the logic input functions
on the SMH4803A. The reference outputs are with re-
spect to V
SS
.
ENPGA (16)
This is an active high input that controls the PG2# and
PG3# outputs. When ENPGA is pulled low the PG2# and
PG3# outputs are immediately placed in a high impedance
state. When ENPGA is driven high or left floating then
PG2# will be driven low at a time period of t
PGD
after PG1#
has been active. This pin has an internal 50k
pull-up to
5V.
ENPGB (15)
This is an active high input that controls the PG3# output.
When ENPGB is pulled low the PG3# output is immedi-
ately placed in a high impedance state. When ENPGB is
driven high or left floating then PG3# will be driven low at
a time period of t
PGD
after PG2# has been active. This pin
has an internal 50k
pull-up to 5V.
PG1#, PG2#, & PG3# (18, 19, & 17)
The PGn# pins are open-drain, active-low outputs with no
internal pull-up resistor. They can be used to switch a load
or enable a DC/DC converter. PG1# is enabled immedi-
ately after VGATE reaches V
DD
V
GT
and the DRAIN
SENSE voltage is less than 2.5V. Each successive PG
output is enabled t
PGD
after its predecessor, provided also
that the appropriate ENPG input(s) are high. Voltage on
these pins cannot exceed 12V, as referenced to V
SS.
V
DD
(20)
V
DD
is the positive supply connection. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the V
DD
pin to limit the regulator current (R
D
in
the application illustrations).
V
SS
(10)
V
SS
is connected to the negative side of the supply.
PD1#, PD2#, MODE, RESET#,
ENPGA, ENPGB, EN/TS ......................... 10V
RECOMMENDED OPERATING CONDITIONS
Temperature
40
C to 85
C.
5
2051 4.4 3/15/01
SMH4803A
Preliminary
SUMMIT MICROELECTRONICS, Inc.
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to V
SS
, except V
GT
)
2051 Elect Table 2.2
(1) TA = 25C.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
.
n
i
M
.
p
y
T
.
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
v
y
l
p
p
u
S
I
D
D
A
m
3
=
1
1
2
1
3
1
V
F
E
R
V
0
.
5
t
u
p
t
u
o
e
c
n
e
r
e
f
e
r
V
5
I
D
D
A
m
3
=
5
7
.
4
0
0
.
5
5
2
.
5
V
I
5
D
A
O
L
t
n
e
r
r
u
c
t
u
p
t
u
o
e
c
n
e
r
e
f
e
r
V
5
I
D
D
A
m
3
=
1
1
A
m
F
E
R
V
5
.
2
t
u
p
t
u
o
e
c
n
e
r
e
f
e
r
V
5
.
2
I
D
D
A
m
3
=
)
1
(
5
7
4
.
2
0
0
5
.
2
5
2
5
.
2
V
I
D
D
A
m
3
=
5
2
4
.
2
0
0
5
.
2
5
7
5
.
2
V
I
5
.
2
D
A
O
L
t
n
e
r
r
u
c
t
u
p
t
u
o
e
c
n
e
r
e
f
e
r
V
5
.
2
I
D
D
A
m
3
=
2
.
0
1
A
m
I
D
D
t
n
e
r
r
u
c
y
l
p
p
u
s
r
e
w
o
P
d
e
l
b
a
n
e
t
u
p
t
u
O
2
0
1
A
m
V
V
U
d
l
o
h
s
e
r
h
t
e
g
a
t
l
o
V
-
r
e
d
n
U
I
D
D
A
m
3
=
)
1
(
5
7
4
.
2
0
0
5
.
2
5
2
5
.
2
V
I
D
D
A
m
3
=
5
2
4
.
2
0
0
5
.
2
5
7
5
.
2
V
V
T
S
Y
H
V
U
s
i
s
e
r
e
t
s
y
h
e
g
a
t
l
o
V
-
r
e
d
n
U
I
D
D
A
m
3
=
0
1
V
m
V
V
O
d
l
o
h
s
e
r
h
t
e
g
a
t
l
o
V
-
r
e
v
O
I
D
D
A
m
3
=
)
1
(
5
7
4
.
2
0
0
5
.
2
5
2
5
.
2
V
I
D
D
A
m
3
=
5
2
4
.
2
0
0
5
.
2
5
7
5
.
2
V
V
T
S
Y
H
V
O
s
i
s
e
r
e
t
s
y
h
e
g
a
t
l
o
V
-
r
e
v
O
I
D
D
A
m
3
=
0
1
V
m
V
E
T
A
G
V
e
g
a
t
l
o
v
t
u
p
t
u
o
E
T
A
G
V
V
D
D
V
I
E
T
A
G
V
t
u
p
t
u
o
t
n
e
r
r
u
c
E
T
A
G
V
0
0
1
A
V
E
S
N
E
S
d
l
o
h
s
e
r
h
t
E
S
N
E
S
N
I
A
R
D
I
D
D
A
m
3
=
)
1
(
5
7
4
.
2
0
0
5
.
2
5
2
5
.
2
V
I
D
D
A
m
3
=
5
2
4
.
2
0
0
5
.
2
5
7
5
.
2
V
I
E
S
N
E
S
t
u
p
t
u
o
t
n
e
r
r
u
c
E
S
N
E
S
N
I
A
R
D
V
E
S
N
E
S
V
=
S
S
)
1
(
9
0
1
1
1
A
V
B
C
d
l
o
h
s
e
r
h
t
r
e
k
a
e
r
b
t
i
u
c
r
i
C
I
D
D
A
m
3
=
0
4
0
5
0
6
V
m
V
B
C
Q
t
i
u
c
r
i
c
p
i
r
T
k
c
i
u
Q
e
l
b
a
m
m
a
r
g
o
r
P
d
l
o
h
s
e
r
h
t
r
e
k
a
e
r
b
0
0
2
V
m
0
0
1
V
m
0
6
V
m
f
f
O
--
V
S
T
N
E
d
l
o
h
s
e
r
h
t
S
T
/
N
E
I
D
D
A
m
3
=
)
1
(
5
7
4
.
2
0
0
5
.
2
5
2
5
.
2
V
I
D
D
A
m
3
=
5
2
4
.
2
0
0
5
.
2
5
7
5
.
2
V
V
T
S
Y
H
S
T
N
E
s
i
s
e
r
e
t
s
y
h
S
T
/
N
E
I
D
D
A
m
3
=
0
1
V
m
V
H
I
,
B
/
A
G
P
N
E
:
e
g
a
t
l
o
v
h
g
i
h
t
u
p
n
I
#
T
E
S
E
R
,
E
D
O
M
2
F
E
R
V
0
.
5
V
V
L
I
,
B
/
A
G
P
N
E
:
e
g
a
t
l
o
v
w
o
l
t
u
p
n
I
#
T
E
S
E
R
,
E
D
O
M
1
.
0
8
.
0
V
V
L
O
#
T
L
U
A
F
:
e
g
a
t
l
o
v
w
o
l
t
u
p
t
u
O
I
L
O
A
m
2
=
0
4
.
0
V
#
3
/
#
2
/
#
1
G
P
:
e
g
a
t
l
o
v
w
o
l
t
u
p
t
u
O
I
K
N
I
S
A
m
2
=
0
4
.
0
V
V
T
G
d
l
o
h
s
e
r
h
t
e
t
a
G
7
.
0
8
.
1
0
.
3
V
PDF 
ZIP