SMM105

Preliminary Information

(See Last Page)

© SUMMIT Microelectronics, Inc. 2005 ·

1717 Fox Drive · San Jose CA 95131 · Phone 408 436-9890 · FAX 408 436-9897

www.summitmicro.com

2068 1.8 09/20/05

FEATURES & APPLICATIONS

· Extremely accurate (±0.1%) Active

DC Output Control (ADOC

)

· ADOC Automatically adjusts supply output

voltage level under all DC load conditions

· Capable of margining supplies with trim inputs

using either positive or negative trim pin control

· Wide Margin/ADOC range from 0.3V to VDD

· Uses either an internal or external VREF

· Operates from any intermediate bus supply

from 8V to 15V and from 2.7V to 5.5V

· Programmable START and READY pins

· Two programmable general purpose monitor

sensors UV and OV with FAULT Output Flag

· General Purpose 1k EEPROM with Write Protect

· I

C 2-wire serial bus for programming

configuration and monitoring status.

· 28 pad QFN or 25 ball Ultra CSP

(Chip-Scale)

package

Applications

· In-system test and control of Point-of-Load

(POL) Power Supplies for Multi-voltage
Processors, DSPs and ASICs

· Enterprise and edge routers, servers, Storage

Area Networks

INTRODUCTION

The SMM105 actively controls the output voltage level
of a DC/DC converter that uses a Trim or VADJ/FB pin
to adjust the output. An Active DC Output Control
(ADOC

) feature is used during normal operation to

maintain extremely accurate settings of supply
voltages and, during system test, to control margining
of the supplies using I

C commands. Total accuracy

with a ±0.1% external reference is ±0.2%, and ±0.5%
using the internal reference. The device can margin
supplies with either positive or negative trim pin control
within a range of 0.3V to VDD. The SMM105 supply
can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to
accommodate any intermediate bus supply.

The voltage settings (margin high/low and nominal)
are programmed into nonvolatile memory through the
industry standard I

C 2-wire data bus. The I

C bus is

also used to enable margin high, margin low, ADOC or
normal operation. When margining, the SMM105 will
check the voltage output of the converter and make
adjustments to the trim pin via a feedback loop to bring
the voltage to the margin setting. A margining status
register is set to indicate that the system is ready for
test. The SMM105 ADOC will continue to monitor and
adjust the channel output at the specified level.

SIMPLIFIED APPLICATIONS DRAWING

VIN

TRIM

V+

V-

FILT_CAP

TRIM_CAP

SMM105

uP/

DSP/

FPGA/

ASIC

Internal or

External

Voltage

Reference

VREF_CNTL

GND

1.2 VIN

SDA

SCL

BUS

3.3/5Vin (2.7V to 5.5V)

READY

VDD

VIN

12VIN (6V to 15V)

VDD_CAP

START

POWER GOOD

WP#

FAULT#

COMP1

COMP2

DC/DC

Converter

TRIM

ON/OFF

GND

Figure 1 Applications Schematic using the SMM105 Controller to actively control the DC output level
(ADOC) of a DC/DC Converter as well as margin control. The SMM105 can operate over a wide supply range

Note: This is an applications example only. Some pins, components and values are not shown.

Single-Channel Supply Voltage Marginer and Active DC Output Controller

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

GENERAL DESCRIPTION

The SMM105 is capable of controlling and margining
the DC output voltage of LDOs or DC/DC converters
that use a trim/adjust pin and to automatically change
the level using a unique Active DC Output Control
(ADOC

). The ADOC function is programmable over

a standard 2-wire I

C serial data interface and can be

used to set the nominal DC output voltage as well as
the margin high and low settings. The part actively
controls the programmed set levels to maintain tight
control over load variations and voltage drops at the
point of load. The margin range will vary depending on
the supply manufacturer and model but the normal
range is 10% adjustment around the nominal output
setting. However, the SMM105 has the capability to
margin from VREF_CNTL to VDD.
The user can set the desired voltage settings
(nominal, margin high and margin low) into the EE
memory array for the device. Then, volatile registers
are used to select one of these settings. The registers
are accessed over the I

C bus.

In normal operation, Active DC Output Control is set to
adjust the nominal output voltage of the converter.
Typical converters have

±2% accuracy ratings for their

output voltage. Using the Active DC Output Control
feature of the SMM105 can increase the accuracy to
±0.1%. This high accuracy control of the converter
output voltage is extremely important in low voltage
applications where deviations in power supply voltage
can result in lower system performance. Active DC
Output Control can also be used for margining a
supply during system test or may be turned off by de-
selecting the function in the Control Select Register.
The margin high and margin low voltage settings can
range from 0.3V to VDD around the converters'

nominal output voltage setting depending on the
specified margin range of the DC-DC converter.
When the SMM105 receives the command to margin,
the Active DC Output Control will adjust the supply to
the selected margin voltage. Once the supply has
reached its margined set point, the Ready bit in the
status register will set and the READY pin will go
active. If Active DC Control is disabled, a margined
supply can return to its nominal voltage by writing to
the margin command register.
In order to obtain maximum accuracy, the SMM105
requires an external voltage reference. An external
reference with ±0.1% accuracy will enable an overall
±0.2% accuracy for the device. A configuration option
also exists so that an internal voltage reference can be
used, but with less accuracy. Total accuracy using the
internal reference is ±0.5%. The SMM105 can be
powered from either a 12V or 8V input via an internal
regulator or the VDD input (Figure 3).
The SMM105 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the
VREF_CNTL input or the internal reference (VREF).
Each comparator can be independently programmed
to monitor for UV or OV. When either of the COMP1
or COMP2 inputs are in fault the open-drain FAULT#
output will be pulled low. A configuration option exists
to disable the FAULT# output during margining.
Programming of the SMM105 is performed over the
industry standard I

C 2-wire serial data interface. A

status register is available to read the state of the part
and a Write Protect (WP#) pin is available to prevent
writing to the configuration registers and EE memory.

Figure 2 Example Power Supply Margining using the SMM105. The waveform on the left is margin low to
high from 1.6V to 2.0V and the waveform on the right is margin high to nominal from 2.0V to 1.8V. The ADOC
function guarantees the output level to be within ±0.2% with a ±0.1% external reference. The bottom
waveform is the READY signal indicating margin is complete.

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

W P#

SDA

SCL

VREF_CNTL

TRIM

TRIM_CAP

V+

V-

12VIN

VDD_CAP

VDD

READY

START

COMP1

COMP2

OV/UV

FAULT#

Output

Control

MUX

R EF

Input Voltage

Sensing and

Signal

Conditioning

Configuration

Registers

& M emory

C Serial

Interface

3.6/5V

Regulator

Trim

Drive

Supply

Arbitration

Figure 3 SMM105 Controller Internal Block Diagram.

PACKAGE AND PIN CONFIGURATION

SMM105

Pin 1

SCL

START

READY

GND

WP#

VREF_CNTL

FILT_

CAP

FAULT#

COMP2

VDD
TRIM
COMP1
TRIM_CAP
NC
NC
NC

SDA

NC NC NC

VDD

_
CAP

12VIN

INTERNAL BLOCK DIAGRAM

28 Pin QFN

Top View

SCL

VDD_CAP

VDD

START

SDA

TRIM

READY

GND VREF_CNTL FAULT#

WP# FILT_CAP COMP2

Pin 1

12VIN

COMP1 TRIM_CAP

25 Ball Ultra CSP

Bottom View

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

PIN DESCRIPTIONS

QFN

Pad

Number

Ultra

CSP

Ball

Number

Pin

Type

Pin Name

Pin Description

DATA

SDA

C Bi-directional data line

CLK

SCL

C clock input.

The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.

WP#

Write Protect active low input. When asserted, writes to the
configuration registers and general purpose EE are not allowed.

CAP

FILT_CAP

External capacitor input used to filter the VM input.

CAP

TRIM_CAP

External capacitor input used for Active Control and margining.

TRIM

Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.

Voltage monitor input. Connect to the DC-DC converter positive
sense line or its' +Vout pin.

VREF_CNTL

Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V
reference. Pin should be left open if using VREF internal

PWR

VDD

Power supply of the part.

GND

GND

Ground of the part. The SMM105 ground pin should be connected
to the ground of the device under control or to a star point ground.
PCB layout should take into consideration ground drops.

PWR

12VIN

12V power supply input internally regulated to either 3.6V or 5.5V.
When using the 3.6V internal regulator option, the 12VIN input can
be as low as 8V. It can be as high as 15V using the 5.5V internal
regulator.

START

Programmable active high/low input. The START input is used
solely for enabling Active Control and/or margining. There is also
a programmable start delay time, T

START

to delay ADOC/Margin

control.

I/O

READY

Programmable active high/low open drain output indicates that VM
is at its set point. When programmed as an active high output,
READY can also be used as an input. When pulled low, it will latch
the state of the comparator inputs.

CAP

VDD_CAP

External capacitor input used to filter the internal supply rail.

COMP1

COMP2

COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the VREF_CNTL
input. Each comparator can be independently programmed to
monitor for UV or OV. The monitor level is set externally with a
resistive voltage divider.

FAULT#

When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option
exists to disable the FAULT# output while the device is margining.

13,15,16

17,24-27

B3,C3,
D4,D5,

No Connect. Leave floating; do not connect anything to the NC
pins.

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ...................... -55

C to 125

Storage Temperature QFN ................... -65

C to 150

Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
12VIN Supply Voltage......................-0.3V to 15.0V
All Others ................................-0.3V to V

+ 0.7V

Output Short Circuit Current ............................... 100mA
Junction Temperature..........................................125°C
ESD Rating per JEDEC..................................2000V
Latch-Up testing per JEDEC..........................

100mA

Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.

RECOMMENDED OPERATING CONDITIONS

Temperature Range (Industrial) .......... 40

C to +85

(Commercial)............ 5

C to +70

VDD Supply Voltage.................................. 2.7V to 5.5V
12VIN Supply Voltage (1)........................ 8.0V to 14.0V
VIN.............................................................GND to VDD
VOUT.......................................................GND to 15.0V
Package Thermal Resistance (

)

28 Pad QFN............................................80

C/W

25 Ball Ultra

CSP

..................................TBD

C/W

Moisture Classification Level 1 (MSL 1) per J-STD- 020

Note 1 Range depends on internal regulator set to 3.6V or 5.5V, see
12VIN specification below.

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes

Min.

Typ.

Max

Unit

VDD Supply

Voltage

2.7 3.3 5.5 V

Internally regulated to 5.5V

12VIN Supply

Voltage

Internally regulated to 3.6V

Positive Sense Voltage

VM pin

-0.3

VDD

Power Supply Current from
VDD

All TRIM pins and 12VIN floating

12VIN

Power Supply Current from
12VIN

All TRIM pins and VDD floating

TRIM Sourcing Max Current

1.5

TRIM

TRIM output current
through 100

to 1.0V

TRIM Sinking Max Current

1.5

ADOC

Margin Control/ADOC
Range

Depends on Trim range of DC-
DC Converter

VREF_CNTL

VDD

VDD = 2.7V

0.9xVDD

VDD

Input High Voltage

VDD = 5.0V

0.7xVDD

VDD

VDD = 2.7V

0.1xVDD

Input Low Voltage

VDD = 5.0V

0.3xVDD

Programmable Open Drain
Output (READY)

ISINK = TBD

0.2

OV/UV

Monitor Voltage Range

COMP1 and COMP2 pins

-0.3

VDD

HYST

Base DC Hysteresis

COMP1 and COMP2 pins,
V

-V

Note 1

3 10

Note 1 The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High, V

-V

while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC

Hysteresis is derived from the equation: (V

REF

)(Base Hysteresis). For example, if V

=2.5V and V

REF

=1.25V then Actual DC Hysteresis=

(2.5V/1.25V)(0.003V)=6mV.

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

DC OPERATING CHARACTERISTICS (CONTINUED)

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes

Min.

Typ.

Max

Unit

VREF

1.25VREF Output Voltage

LOAD

= 2K

to GND

1.24 1.25 1.26 V

REF_CNTL

External V

REF

Voltage

Range

0.25

VDD

External VREF=1.25V, ±0.1%

-0.2

0.1

+0.2 %

ADOC

ACC

ADOC/Margin

Accuracy

ADOC trimmed to internal VREF

-0.5

0.3

+0.5 %

AC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes

Min.

Typ.

Max

Unit

DC_CONTROl

Active DC Control sampling period

Update period for Active
DC Control

1.7 ms

settling

Settling Time

+ 10% change in voltage
with 0.1% ripple

100 ms

Fast Margin, nom to high,
TRIM_CAP=1

µF

20 ms

TRIM

Trim

Speed

Slow Margin, nom to high,
TRIM_CAP=1

µF

200 ms

0.2 ms

12.8 ms

25.6 ms

start

Programmable Start Time

ADOC/Margining Start
time delay after Start pin is
enabled

51.2 ms

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

C 2-WIRE SERIAL INTERFACE AC OPERATING

CHARACTERISTICS 100/400kHz

Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram.

100kHz 400kHz

Symbol Description

Conditions

Min Typ Max Min Typ Max Units

SCL

SCL Clock Frequency

100

400

KHz

LOW

Clock Low Period

4.7

1.3

µs

HIGH

Clock

High

Period

4.0 0.6 µs

BUF

Bus Free Time

Before New Transmission

Note 1/

4.7 1.3 µs

SU:STA

Start Condition Setup Time

4.7

0.6

µs

HD:STA

Start Condition Hold Time

4.0

0.6

µs

SU:STO

Stop Condition Setup Time

4.7

0.6

µs

Clock Edge to Data Valid

SCL low to valid
SDA (cycle n)

0.2 3.5 0.2 0.9 µs

Data Output Hold Time

SCL low (cycle n+1)
to SDA change

0.2 0.2 µs

SCL and SDA Rise Time

Note 1/

1000

SCL and SDA Fall Time

Note 1/

300 300 ns

SU:DAT

Data In Setup Time

250

150

HD:DAT

Data In Hold Time

Noise Filter SCL and SDA

Noise suppression

100

Write

Cycle

Time

5 5 ms

Note: 1/ - Guaranteed by Design.

HIGH

LOW

SU:SDA

HD:SDA

SU:DAT

HD:DAT

SU:STO

BUF

SCL

SDA

(IN)

SDA

(OUT)

W R (For W rite Operation Only)

Figure 4 . Basic I

C Serial Interface Timing

TIMING DIAGRAMS

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

APPLICATIONS INFORMATION

DEVICE OPERATION

POWER SUPPLY
The SMM105 can be powered by either an 8V to 15V
input through the 12VIN pin or by a 2.7V to 5.5V input
through the VDD pin (Figure 5). The 12VIN pin feeds
an internal programmable regulator that internally
generates either 5.5V or 3.6V. The internal regulator
must be set to 3.6V if using an 8V supply. A voltage
arbitration circuit allows the device to be powered by
the highest voltage from either the regulator output or
the VDD input. This voltage arbitration circuit
continuously checks for these voltages to determine
which will power the SMM105. The resultant internal
power supply rail is connected to the VDD_CAP pin
that allows both filtering and hold-up of the internal
power supply.
VOLTAGE REFERENCE
The SMM105 can operate using either an internal or
external voltage reference, VREF. The internal VREF
is set to 1.25V. Total accuracy with a ±0.1% external
reference is ±0.2% and ±0.5% using the internal
reference.
MODES OF OPERATION
The SMM105 has two basic modes of operation: UV
and OV monitoring mode and supply margining mode
,and one key feature, Active DC Output Control
(ADOC

). A detailed description of each mode and

feature follows.
ACTIVE DC OUTPUT CONTROL (ADOC

)

The SMM105 can control the DC output voltage of
bricks or DC/DC converters that have a trim pin. The
TRIM pin on the SMM105 is connected to the trim
input pin on the power supply converter. A sense line
from the channel's point-of-load connects to the VM
input. The Active DC Control function cycles every
1.7ms making slight adjustments to the voltage on the
TRIM output pin based on the voltage input on the VM
pin. This voltage adjustment allows the SMM105 to
control the output voltage of the power supply
converter to within ±0.2% when using a ±0.1%
external voltage reference.

The voltage on the TRIM_CAP pins is buffered and
applied to the TRIM pin. The voltage adjustments on
the TRIM pin cause a slight ripple of less than 1mV on
the power supply voltage. The amplitude of this ripple
is a function of the TRIM_CAP capacitor and the trim
gain of the converter. Calculation of the TRIM_CAP
capacitor to achieve a desired minimum ripple is
detailed in Application Note 37.
The device can be programmed to either enable or
disable the ADOC function. When disabled or not
active, the TRIM pin on the SMM105 is a high
impedance input. The voltage on the TRIM pin is
buffered and applied to the TRIM_CAP pin charging
the capacitor. This allows a smooth transition from the
converter's nominal voltage to the SMM105 controlling
that voltage to the ADOC nominal setting.
There are programmable Start times, T

START

, which are

used to delay the ADOC function to allow the
controlled supply to turn fully on before changing the
output voltage level. There is also a programmable
Speed-Up Convergence option. This option
decreases the time required to bring a supply voltage
from the converter's nominal output voltage to the
Active DC Output Control nominal voltage setting.
MONITORING
The SMM105 monitors the COMP1 and COMP2
inputs as well as the VM pin. COMP1 and COMP2
are high impedance inputs, each connected internally
to a comparator and compared against the
VREF_CNTL input. Each comparator can be
independently programmed to monitor for either UV or
OV. The monitor level is set externally with a resistive
voltage divider. The part can be programmed to trigger
the FAULT# pin when either COMPx comparator has
exceeded the UV or OV range. The READY and
FAULT# outputs of the SMM105 are active as long as
the triggering limit remains in a fault condition. The
READY pin is programmable active high/low open
drain output indicates that VM is at its' set point.
When programmed as an active high output, READY
can also be used as an input. When pulled low, it will
latch the state of the comparator inputs. When either
of the COMP1 or COMP2 inputs are in fault, the open-
drain FAULT# output will be pulled low. A
configuration option exists to disable the FAULT#
output while the device is margining mode.

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

STATUS REGISTER
A status register exists for I

C polling of the status of

the COMP1 and COMP2 inputs. Two bits in this
status register reflect the current state of the inputs (1
= fault, 0 = no fault). Two additional bits show the
state of the inputs latched by one of two events
programmed in the configuration. The first event
option is the FAULT# output going active. The second
event option is the READY pin going low. The READY
pin is an I/O. As an output, the READY output pin
goes active when the DC controlled voltages are at
their set point. As an input programmed to active high,
it can be pulled low externally and latch the state of
the COMP inputs. This second event option allows
the state of the COMP inputs on multiple devices to be
latched at the same time while a host monitors their
FAULT# outputs.

MARGINING
The SMM105 has two additional Active DC Output
Control voltage settings: margin high and margin low.
The margin high and margin low settings can be as
much as

±10% of the nominal setting depending on

the manufacturer. The SMM105 range can be as
large as VREF_CNTL to VDD. These settings are
stored in the configuration registers and are loaded
into the Active DC Output Control voltage setting by
margin commands issued via the I

C bus. The device

must be enabled for Active DC Output Control in order
to enable margining.

The margin command registers contain two bits that
decode the commands to margin high, margin low, or
control to the nominal setting. Once the SMM105
receives the command to margin the supply voltage, it
begins adjusting the supply voltage to move toward
the desired setting. When this voltage setting is
reached, a bit is set in the margin status registers and
the READY signal becomes active. (Figure 5)
Note: Configuration writes or reads of registers 00

HEX

to 03

HEX

should not be performed while the SMM105 is

margining.
WRITE PROTECTION
Write protection for the SMM105 is located in a volatile
register where the power-on state is defaulted to write
protect. There are separate write protect modes for the
configuration registers and memory. In order to
remove write protection, the code 55

HEX

is written to

the write protection register. Other codes will enable
write protection. For example, writing 59

HEX

will allow

writes to the configuration register but not to the
memory, while writing 35

HEX

will allow writes to the

memory but not to the configuration registers. The
SMM105 also features a Write Protect pin (WP# input)
which, when asserted, prevents writing to the
configuration registers and EE memory. In addition to
these two forms of write protection there is a
configuration register lock bit which, once
programmed, does not allow the configuration
registers to be changed.

Figure 5 SMM105 margin example. The nominal setting is 1.8V. The device margins the DC-DC converter
from nominal to high, 2.0V then to nominal, then to low, 1.6V. Next it margins to nominal then high and then
from high to low and to high again. The READY signals goes low when margining and high when complete.

APPLICATIONS INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

VOUT

C1 1uF

Vdd

The SMM105 and the DC-DC Converter
Can Operate with either 12V or VDD
If 12V is used, VDD can be left floating
If VDD is used, 12V can be left floating

10K

0.01uF

If the SMM105 internal VREF
is used, the VREF_CNTL pin
becomes an output

Vdd

Gnd

SCL

Gnd3

SDA

Rsrv5

+10V

Rsrv8

+5V

Rsrv10

U4 LM4121

Ref

VIn

VOut

DC-DC ENABLE

0.01uF

0.1uF

RT2

~10K

10K

0.1uF

FAULT#

0.02uF

Ext VRef

10K

~10K

01uF

READY

C10

0.01uF

VDD (+2.7V to +5.5V)

DIODE

START

SMX3200 I2C Programming

Connector 10 pin Header

0.1uF

SMM105

15 16 17

24 25 26 27

SCL

START

READY

GND

WP#

EF_C

FILT_CAP

FAULT#

COMP2

NC NC NC

TRIM_CAP

COMP1

TRIM

12VI

DD_

NC NC NC NC

SDA

Supply

+12VIN (+10V to +15V)

10K

DC-DC Converter

5 6

+Vout

Sense

+Vout

+Vin

Trim

Enable

Figure 6 SMM105 Applications schematic. The accuracy of the external (U4) or internal reference sets the
accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% with the
internal reference. The 12V supply can go as low as 8V if the internal regulator is set to 3.6V.

APPLICATIONS INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

RTRIM(R3) is calculated as follows:
VTRIMlow=0.3V, Regulator VREF=0.8V
The current through R3 is ITRIM=(0.8-0.3)/RTRIM
(ITRIM)(R4) > 15% of VOUT
RTRIMmax should be < the calculated value

0.02uF

R6 10K

C1 1uF

START

R7 10K

20k

0.01uF

For Example:
If Vout=3.3V, R4=63.4K, 15% of Vout=0.5V
ITRIM=8uA, RTRIM=62.5K
Therefore Rtrim standard 1% value down from 62.

Gnd

SCL

Gnd3

SDA

Rsrv5

+10V

Rsrv8

+5V

Rsrv10

START

SMM105

15 16 17

24 25 26 27

SCL

START

READY

GND

WP#

VREF_

NTL

FILT_CAP

FAULT#

COMP2

NC NC NC

TRIM_CAP

COMP1

TRIM

VDD

12V

VDD_CAP

NC NC NC NC

SDA

RTRIM

FAULT#

DIODE

READY

VOUT

SMX3200 I2C Programming
Connector 10 pin Header
R1 and R2 need only be
placed once on the I2C bus

0.1uF

R1 10K

R2 10K

R8 10K

0.1uF

Switching Regulator

+Vout

Gnd

+Vin

VADJ (VREF)

PGOOD

The SMM105 START pin must be inactive during power-up so
that the TRIM pin is high impedence. Once power is nominal,
the START pin can be active to start margin and ADOC
functions

RSET1

+12VIN (+10V to +15V)

Figure 7 SMM105 Applications schematic for an adjustable switching regulator (Full regulator circuit not
shown).

APPLICATIONS INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

The end user can obtain the Summit SMX3200
programming system for device prototype
development. The SMX3200 system consists of a
programming Dongle, cable and Windows

GUI

software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
SMX3200 is available from the website
(

www.summitmicro.com

The SMX3200 programming Dongle/cable interfaces
directly between a PC's parallel port and the target
application. The device is then configured on-screen
via an intuitive graphical user interface employing
drop-down menus.

The Windows GUI software will generate the data and
send it in I

C serial bus format so that it can be directly

downloaded to the SMM105 via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 8.

When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations. This will ensure proper device
operation in the end application.

Pin 9, 5V

Pin 7, 10V

Pin 5, Reserved
Pin 3, GND
Pin 1, GND

Pin 6, MR#
Pin 4, SDA

Pin 2, SCL

Pin 8, Reserved

Pin 10, Reserved

Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.

9
7
5
3
1

8
6
4
2

SMM105

SDA

SCL

VDD_CAP

GND

0.1

Positive

Supply

Com m on

Ground

W P#

1N4148

Figure 8 SMX3200 Programmer I

C serial bus connections to program the SMM105. The SMM105 has a

Write Protect pin (WP# input) which when, asserted, prevents writing to the configuration registers and EE
memory. In addition, there is a configuration register lock bit which, once programmed, does not allow the
configuration registers to be changed.

DEVELOPMENT HARDWARE & SOFTWARE

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I

C). SDA is a bi-directional data line and SCL is a

clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (t

HIGH

)

is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing. The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM105.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
It can be programmed to any four bit number 0000

BIN

through 1111

BIN

The bus address bits A[2:0] are hard wired only
though address pins 2, 4 and 6 (A2, A1 and A0). The
bus address accessed in the address byte of the serial
data stream must match the setting on the SMM105
address pins.

WRITE
Writing to the memory or a configuration register is
illustrated in Figures 9, 10, 11, 13, 14 and 16. A Start
condition followed by the address byte is provided by
the host; the SMM105 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM105 responds with an acknowledge;
the host then clocks in one byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM105. This is accomplished by issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 12, 15 and 17 for an
illustration of the read sequence.
WRITE PROTECTION
The SMM105 powers up into a write protected mode.
Writing a code to the volatile write protection register
(write only) can disable the write protection. The write
protection register is located at address 42

HEX

. Writing

to the write protection register is shown in Figure 9.
Writing 0101

BIN

to bits [7:4] of the write protection

BIN

to bits [3:0] allow writes to the

configuration registers. The write protection can be re-
enabled by writing other codes (not 0101

BIN

) to the

write protection register.

C PROGRAMMING INFORMATION

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

CONFIGURATION REGISTERS
The majority of the configuration registers are grouped
with the general-purpose memory. Writing and reading
the configuration registers is shown in Figures 10, 11
and 12.
Note: Configuration writes or reads of registers 00

HEX

to 03

HEX

should not be performed while the SMM105

is margining.
GENERAL-PURPOSE MEMORY
The 1k-bit general-purpose memory is located at any
slave address. The bus address bits are hard wired
by the address pins A2, A1 and A0. Memory writes
and reads are shown in Figures 13, 14 and 15.

COMMAND AND STATUS REGISTERS
Writes and reads of the command and status registers
are shown in Figures 16 and 17.
GRAPHICAL USER INTERFACE (GUI)
Device configuration utilizing the Windows based
SMM105 graphical user interface (GUI) is highly
recommended. The software is available from the
Summit website (

www.summitmicro.com

). Using the

GUI in conjunction with this datasheet and Application
Note 38, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMM105. The
Dongle connects directly to the parallel port of a PC
and programs the device through a cable using the I

bus protocol. See figure 8 and the SMX3200 Data
Sheet.

Slave Address Bus Address Register Type

Configuration Registers are located in
00

HEX

thru 45

HEX

ANY

A2 A1 A0

General-Purpose Memory is located in
80

HEX

thru FF

HEX

Table 1 - Address bytes used by the SMM105.

C PROGRAMMING INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

S
T
A
R
T

A
C
K

M aster

Slave

A
C
K

Configuration

Register Address = 42

HEX

S
T

Data = 55

HEX

A
C
K

Bus Address

HEX

Unlocks

General Purpose

HEX

Unlocks

Configuration

Registers

W rite Protection

Register Address

S
A

HEX

Figure 9 Write Protection Register Write

S
T
A
R
T

Bus Address

A
C
K

M aster

Slave

A
C
K

Configuration

Register Address

S
T

Data

A
C
K

S
A

Figure 10 Configuration Register Byte Write

S
T
A
R
T

Bus Address

A
C
K

S
T

M aster

Slave

A
C
K

Data (16)

Configuration

Register Address

A
C
K

Data (1)

A
C
K

Data (2)

A
C
K

S
A

Figure 11 Configuration Register Page Write

C PROGRAMMING INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

S
T
A
R
T

Bus Address

A
C
K

S
T

N
A
C
K

M aster

Slave

A
C
K

Data (n)

Configuration

Register Address

S
T
A
R
T

A
C
K

Bus Address

A
C
K

Data (1)

S
A

Figure 12 - Configuration Register Read

S
T
A
R
T

Bus Address

A
C
K

M aster

Slave

A
C
K

Configuration

Register Address

S
T

Data

A
C
K

S
A

Figure 13 General Purpose Memory Byte Write

Bus Address

S
T
A
R
T

A
C
K

S
T

M aster

Slave

A
C
K

Data (16)

Configuration

Register Address

A
C
K

Data (1)

A
C
K

Data (2)

A
C
K

S
A

Figure 14 - General Purpose Memory Page Write

C PROGRAMMING INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

S
T
A
R
T

A
C
K

S
T

N
A
C
K

M aster

Slave

A
C
K

Data (n)

Configuration

Register Address

S
T
A
R
T

A
C
K

Data (1)

Bus Address

S
A

Figure 15 - General Purpose Memory Read

S
T
A
R
T

A
C
K

M aster

Slave

A
C
K

Command and Status

Register Address

S
T

Data

A
C
K

Bus Address

S
A

Figure 16 Command and Status Register Write

S
T
A
R
T

A
C
K

S
T

N
A
C
K

M aster

Slave

A
C
K

Data (n)

Command and Status

Register Address

S
T
A
R
T

A
C
K

Data (1)

Bus Address

S
A

Figure 17 - Command and Status Register Read

C PROGRAMMING INFORMATION (CONTINUED)

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

DEFAULT CONFIGURATION REGISTER SETTINGS SMM105NC-160

Register Contents

Function

R00

Nominal Voltage is set to 1.800V (MSB)

R01

Nominal Voltage is set to 1.800V (LSB)

R04 25

ADOC is enabled, Trim polarity is inverse, Fast Convergence, VREF External, Fault
Latched by a Fault Condition

R05

Slave address is 0101, Start Delay set to 0.2ms

R06 03

No Write Command Required to Activate ADOC, Internal Regulator set to 3.6V,
Fault Output Enabled While Margining, Configuration Registers Unlocked, COMP1
and COMP2 are set to sense OV

R08

Margin Command Bits

R0C

Stores VREF_CNTL value set to 1.25

R0D

Stores VREF_CNTL value set to 1.25

R20

Margin High Voltage is set to 1.902V (MSB)

R21

Margin High Voltage is set to 1.902V (LSB)

R30

Margin Low Voltage is set to 1.702V (MSB)

R31

Margin Low Voltage is set to 1.702V (LSB)

R40

Margin Command Status Bits

R41

READY and START pin Polarities set to Active High

R42 FF

Write

Protect

R44

Fault Status Bits

RC1

The default device ordering number is SMM105NC-160, is programmed as described above
and tested over the commercial temperature range. Application Note 38 contains a
complete description of the Windows GUI and the default settings of each of the 16
individual Configuration Registers.

SMM105

Preliminary Information

Summit Microelectronics, Inc

2068 1.8 09/20/05

PART MARKING

SUMMIT

SMM105N

AYYWW

Pin 1

Annn

Summit
Part Number

Date Code (YYWW)

Part Number suffix
(Contains Customer specific
ordering requirements)

Lot tracking code (Summit use)

Drawing not

to scale

Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)

Product Tracking Code (Summit use)

100% Sn, RoHS compliant, Green

ORDERING INFORMATION

NOTICE

NOTE 1 - This is a

Preliminary Information

data sheet that describes a Summit product currently in pre-production with limited characterization.

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.

Revision 1.8 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at

http://www.summitmicro.com/prod_select/summary/SMM105/SMM105.htm

for data sheet updates.

PROGRAMMABLE POWER FOR A DIGITAL WORLDTM

ADOC

is a trademark of Summit Microelectronics Inc. I2C is a trademark of Philips Corporation.

SMM105

nnn

Package

Part Number Suffix (see page 18)

Summit
Part
Number

Customer specific requirements are contained
in the suffix such as Hex code, Hex code
revision, etc.

Temp Range

C=Commercial
Blank=Industrial

N=28 Pad QFN
E=25 Ball Ultra CSP

is the Lead-Free Attribute for the CSP

(E Package),

is for the QFN (N package)

25 Ball Ultra CSP

28 Pad QFN

SMMX05V

XSSYW

Ball A1

Identifier

Date Code
Y = Single digit year
(4=2004, 5=2005, etc)

Drawing not

to scale

Summit Part Number

X is the sequential letter per wafer
(i.e. A for the first wafer, B for the second wafer,
C for the third wafer, etc.)

100% Sn, RoHS
compliant, Green

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SMM105NER00

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SMM105NER00